98 lines
2.3 KiB
VHDL
98 lines
2.3 KiB
VHDL
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-- VHDL Architecture Memory.fifo_minimal
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--
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-- Created:
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-- by - uadmin.UNKNOWN (WE3877)
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-- at - 13:54:33 11.07.2012
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--
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-- using Mentor Graphics HDL Designer(TM) 2009.2 (Build 10)
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--
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library Common;
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use Common.CommonLib.all;
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architecture RTL_minimal of FIFO is
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subtype register_type is std_ulogic_vector(dataIn'high downto 0);
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type memory_type is array (0 to depth-1) of register_type;
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signal writeCounter: unsigned(requiredBitNb(depth)-1 downto 0);
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signal readCounter: unsigned(writeCounter'range);
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signal memoryArray : memory_type;
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begin
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updateWriteCounter: process(reset, clock)
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begin
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if reset = '1' then
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writeCounter <= (others => '0');
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elsif rising_edge(clock) then
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if write = '1' then
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writeCounter <= writeCounter + 1;
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end if;
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end if;
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end process updateWriteCounter;
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updateReadCounter: process(reset, clock)
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begin
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if reset = '1' then
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readCounter <= (others => '0');
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elsif rising_edge(clock) then
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if read = '1' then
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readCounter <= readCounter + 1;
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end if;
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end if;
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end process updateReadCounter;
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writeMem: process(clock)
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begin
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if rising_edge(clock) then
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if write = '1' then
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memoryArray(to_integer(writeCounter)) <= dataIn;
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end if;
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end if;
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end process writeMem;
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dataOut <= memoryArray(to_integer(readCounter));
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-- checkStatus: process(reset, clock)
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-- begin
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-- if reset = '1' then
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-- empty <= '1';
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-- full <= '0';
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-- elsif rising_edge(clock) then
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-- if readCounter+1 = writeCounter then
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-- if read = '1' then
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-- empty <= '1';
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-- end if;
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-- elsif writeCounter = readCounter then
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-- if write = '1' then
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-- empty <= '0';
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-- end if;
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-- if read = '1' then
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-- full <= '0';
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-- end if;
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-- elsif writeCounter+1 = readCounter then
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-- if write = '1' then
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-- full <= '1';
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-- end if;
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-- end if;
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-- end if;
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-- end process checkStatus;
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checkStatus: process(readCounter, writeCounter)
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begin
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if readCounter = writeCounter then
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empty <= '1';
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else
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empty <= '0';
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end if;
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if writeCounter+1 = readCounter then
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full <= '1';
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else
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full <= '0';
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end if;
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end process checkStatus;
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END ARCHITECTURE RTL_minimal;
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