25 lines
564 B
VHDL
25 lines
564 B
VHDL
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ARCHITECTURE RTL OF programCounter IS
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signal pCounter: unsigned(progCounter'range);
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BEGIN
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updateProgramCounter: process(reset, clock)
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begin
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if reset = '1' then
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pCounter <= (others => '0');
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elsif rising_edge(clock) then
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if incPC = '1' then
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pCounter <= pCounter + 1;
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elsif loadInstrAddress = '1' then
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pCounter <= instrAddress;
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elsif loadStoredPC = '1' then
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pCounter <= storedProgCounter;
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end if;
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end if;
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end process updateProgramCounter;
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progCounter <= pCounter;
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END ARCHITECTURE RTL;
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