41 lines
1.2 KiB
VHDL
41 lines
1.2 KiB
VHDL
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-- Risc-V ed. 2022 page 250 (pdf page 273)
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ARCHITECTURE rtl OF ALU IS
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signal lvec_res : std_ulogic_vector(res'range);
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signal lsig_zero : std_ulogic;
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BEGIN
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lsig_zero <= '1' when lvec_res = (lvec_res'range => '0') else '0';
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zero <= lsig_zero after g_tALU;
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res <= lvec_res after g_tALU;
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alu : process(srcA, srcB, ctrl)
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begin
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case ctrl is
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when "000" => -- add
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lvec_res <= std_ulogic_vector(resize(
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unsigned(srcA) + unsigned(srcB), lvec_res'length
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));
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when "001" => -- substract
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lvec_res <= std_ulogic_vector(resize(
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unsigned(srcA) - unsigned(srcB), lvec_res'length
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));
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when "010" => -- AND
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lvec_res <= srcA and srcB;
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when "011" => -- OR
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lvec_res <= srcA or srcB;
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when "101" => -- SLT
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if srcA < srcB then
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lvec_res <= (lvec_res'high downto 1 => '0') & '1';
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else
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lvec_res <= (lvec_res'high downto 1 => '0') & '0';
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end if;
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when others => -- unknown
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lvec_res <= (others => '-');
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end case;
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end process alu;
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END ARCHITECTURE rtl;
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