32 lines
846 B
Plaintext
32 lines
846 B
Plaintext
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-- VHDL Entity Lissajous_test.lissajousGenerator_tester.interface
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--
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-- Created:
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-- by - axel.amand.UNKNOWN (WE7860)
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-- at - 14:48:11 28.04.2023
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--
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-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5)
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--
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LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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USE ieee.numeric_std.ALL;
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ENTITY lissajousGenerator_tester IS
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GENERIC(
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signalBitNb : positive := 16;
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clockFrequency : real := 60.0E6
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);
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PORT(
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triggerOut : IN std_ulogic;
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xLowapss : IN unsigned (signalBitNb-1 DOWNTO 0);
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xSerial : IN std_ulogic;
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yLowpass : IN unsigned (signalBitNb-1 DOWNTO 0);
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ySerial : IN std_ulogic;
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clock : OUT std_ulogic;
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reset : OUT std_ulogic
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);
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-- Declarations
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END lissajousGenerator_tester ;
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