23 lines
1.0 KiB
Plaintext
23 lines
1.0 KiB
Plaintext
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<?xml version="1.0" encoding="UTF-8"?>
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<BaliProject version="3.2" title="MyProjectTitle" device="LFE5U-25F-6BG256C" default_implementation="toplevel">
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<Options/>
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<Implementation title="toplevel" dir="toplevel" description="toplevel" synthesis="synplify" default_strategy="Strategy">
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<Source name="../concat/did-synchro.vhd" type="VHDL" type_short="VHDL">
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<Options/>
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</Source>
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<Source name="../concat/did-synchro.lpf" type="Logic Preference" type_short="LPF">
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<Options/>
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</Source>
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<Source name="reveal_analyze.rva" type="Reveal Analyzer Project File" type_short="RVA">
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<Options/>
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</Source>
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<Source name="reveal_config.rvl" type="Reveal" type_short="Reveal" excluded="TRUE">
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<Options/>
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</Source>
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<Source name="programmer.xcf" type="Programming Project File" type_short="Programming">
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<Options/>
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</Source>
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</Implementation>
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<Strategy name="Strategy" file="strategy.sty"/>
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</BaliProject>
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