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SEm-Labos/06-07-08-09-SystemOnChip/Prefs/hds_user-linux/v2019.3/hds_user_prefs

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version "49.1"
SaPreferences [
(BasePreferences
version "1.1"
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win32DefaultEditor "Builtin"
win32DefaultViewer "Builtin"
unixDefaultEditor "Sublime"
unixDefaultViewer "Builtin"
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ASICDesigner 1
FPGADesigner 1
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userDefinedSynthesisTasks [
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tempDirectory "/tmp"
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]
libMappingsRootDir ""
teamLibMappingsRootDir ""
defaultUserLibRootDir ""
projectSetupRootDir ""
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USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
"
defaultVerilogPackages ""
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tableFont "courier,10,0"
pageSetupInfo (PageSetupInfo
toPrinter 1
exportedDirectories [
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exportStdIncludeRefs 1
exportStdPackageRefs 1
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pageSizes [
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exportPageSetupInfo (PageSetupInfo
ptrCmd "FrameMaker MIF"
toPrinter 1
exportedDirectories [
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exportStdIncludeRefs 1
exportStdPackageRefs 1
)
exportHTMLPageSetupInfo (PageSetupInfo
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exportHTMLPrintHierInfo (PrintHierInfo
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height 288
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commentGraphicShapeVaSet (VaSet
vasetType 1
fg "49152,49152,49152"
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pageConnTextVaSet (VaSet
fg "0,0,50000"
font "courier,8,1"
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teamPrefsPath ""
remoteSimPath "$HDS_TEAM_VER/remote"
mwMVL4 1
mwVerilogUseSynthesisPragmas 0
mwVhdlUseBusSlicesChkBox 0
mwVerilogUseBusSlicesChkBox 0
vmCheckInDesc ""
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second "concatenated"
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(pair
first "task_ModelSimPath"
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)
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1
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defaultCategoryTemplatesPrefs [
1
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"USER:ModelSim Simulate"
"USER:ModelSim Flow"
"USER:Prepare for Synthesis"
"USER:Xilinx Project Navigator"
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]
tasksMenubarOrder [
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"\"USER:ModelSim Flow\""
]
tasksShortcutbarOrder [
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"\"USER:ModelSim Compile\""
"\"USER:ModelSim Flow\""
"\"USER:ModelSim Simulate\""
"USER:Generate"
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]
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(TaskPref
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