30 lines
692 B
VHDL
30 lines
692 B
VHDL
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ARCHITECTURE Spartan2 OF blockRAM IS
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subtype register_type is std_ulogic_vector(dataBitNb-1 downto 0);
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type memory_type is array (0 to 2**addressBitNb-1) of register_type;
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signal memoryArray : memory_type;
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BEGIN
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portA: process(clock)
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begin
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if rising_edge(clock) then
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if (en = '1') then
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if (write = '1') then
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memoryArray(to_integer(addr)) <= dataIn;
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end if;
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if reset = '1' then
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dataOut <= (others => '0');
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elsif (write = '1') then
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dataOut <= dataIn;
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else
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dataOut <= memoryArray(to_integer(addr));
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end if;
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end if;
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end if;
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end process portA;
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END ARCHITECTURE Spartan2;
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