46 lines
1.3 KiB
VHDL
46 lines
1.3 KiB
VHDL
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ARCHITECTURE noPipe OF pipelineAdder IS
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constant stageBitNb : positive := sum'length/stageNb;
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subtype stageOperandType is signed(stageBitNb-1 downto 0);
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type stageOperandArrayType is array(stageNb-1 downto 0) of stageOperandType;
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subtype carryType is std_ulogic_vector(stageNb downto 0);
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signal a_int, b_int, sum_int : stageOperandArrayType;
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signal carryIn : carryType;
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COMPONENT parallelAdder
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GENERIC (
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bitNb : positive := 32
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);
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PORT (
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sum : OUT signed (bitNb-1 DOWNTO 0);
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cIn : IN std_ulogic ;
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cOut : OUT std_ulogic ;
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a : IN signed (bitNb-1 DOWNTO 0);
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b : IN signed (bitNb-1 DOWNTO 0)
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);
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END COMPONENT;
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BEGIN
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carryIn(0) <= cIn;
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pipeline: for index in stageOperandArrayType'range generate
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a_int(index) <= a(index*stageBitNb+stageBitNb-1 downto index*stageBitNb);
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b_int(index) <= b(index*stageBitNb+stageBitNb-1 downto index*stageBitNb);
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partialAdder: parallelAdder
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GENERIC MAP (bitNb => stageBitNb)
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PORT MAP (
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a => a_int(index),
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b => b_int(index),
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sum => sum_int(index),
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cIn => carryIn(index),
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cOut => carryIn(index+1)
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);
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sum(index*stageBitNb+stageBitNb-1 downto index*stageBitNb) <= sum_int(index);
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end generate pipeline;
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cOut <= carryIn(carryIn'high);
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END ARCHITECTURE noPipe;
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