80 lines
2.7 KiB
VHDL
80 lines
2.7 KiB
VHDL
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LIBRARY Common_test;
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USE Common_test.testUtils.all;
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ARCHITECTURE RTL OF uvmRs232Monitor IS
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constant uartDataBitNb: positive := 8;
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signal baudPeriod: time;
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signal rxWord, txWord: natural;
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signal startup, rxReceived, txReceived: std_ulogic;
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BEGIN
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------------------------------------------------------------------------------
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baudPeriod <= 1.0/baudRate * 1 sec;
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------------------------------------------------------------------------------
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-- receive RxD
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receiveRxD: process
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variable rxData: unsigned(uartDataBitNb-1 downto 0);
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begin
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rxReceived <= '0';
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-- start bit
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wait until falling_edge(RxD);
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wait for 1.5 * baudPeriod;
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-- data bits
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for index in rxData'reverse_range loop
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rxData(index) := RxD;
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wait for baudPeriod;
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end loop;
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-- store information
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rxWord <= to_integer(rxData);
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rxReceived <= '1';
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wait for 0 ns;
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end process receiveRxD;
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------------------------------------------------------------------------------
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-- receive RxD
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receiveTxD: process
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variable txData: unsigned(uartDataBitNb-1 downto 0);
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begin
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txReceived <= '0';
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-- start bit
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wait until falling_edge(TxD);
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wait for 1.5 * baudPeriod;
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-- data bits
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for index in txData'reverse_range loop
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txData(index) := TxD;
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wait for baudPeriod;
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end loop;
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-- store information
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txWord <= to_integer(txData);
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txReceived <= '1';
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wait for 0 ns;
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end process receiveTxD;
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--============================================================================
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-- monitor acesses
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startup <= '1', '0' after 1 ns;
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reportBusAccess: process(startup, rxReceived, txReceived)
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begin
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if startup = '1' then
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monitorTransaction <= pad(
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"idle",
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monitorTransaction'length
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);
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elsif rising_edge(rxReceived) then
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monitorTransaction <= pad(
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reportStart & " sent " & sprintf("%02X", rxWord),
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monitorTransaction'length
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);
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elsif rising_edge(txReceived) then
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monitorTransaction <= pad(
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reportStart & " received " & sprintf("%02X", txWord),
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monitorTransaction'length
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);
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end if;
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end process reportBusAccess;
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END ARCHITECTURE RTL;
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