22 lines
393 B
Plaintext
22 lines
393 B
Plaintext
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-- VHDL Entity Board.inverterIn.symbol
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--
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-- Created:
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-- by - francois.francois (Aphelia)
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-- at - 13:07:14 02/19/19
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--
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-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5)
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--
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LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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ENTITY inverterIn IS
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PORT(
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in1 : IN std_uLogic;
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out1 : OUT std_uLogic
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);
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-- Declarations
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END inverterIn ;
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