39 lines
1.1 KiB
Plaintext
39 lines
1.1 KiB
Plaintext
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-- VHDL Entity AhbLiteComponents.ahbUart.symbol
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--
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-- Created:
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-- by - remi.heredero.UNKNOWN (WE2330808)
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-- at - 15:08:33 23.02.2024
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--
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-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5)
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--
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LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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USE ieee.numeric_std.all;
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LIBRARY AhbLite;
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USE AhbLite.ahbLite.all;
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ENTITY ahbUart IS
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GENERIC(
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txFifoDepth : positive := 8;
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rxFifoDepth : positive := 1
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);
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PORT(
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RxD : IN std_ulogic;
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hAddr : IN unsigned ( ahbAddressBitNb-1 DOWNTO 0 );
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hClk : IN std_uLogic;
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hReset_n : IN std_uLogic;
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hSel : IN std_uLogic;
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hTrans : IN std_ulogic_vector (ahbTransBitNb-1 DOWNTO 0);
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hWData : IN std_ulogic_vector (ahbDataBitNb-1 DOWNTO 0);
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hWrite : IN std_uLogic;
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TxD : OUT std_ulogic;
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hRData : OUT std_ulogic_vector (ahbDataBitNb-1 DOWNTO 0);
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hReady : OUT std_uLogic;
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hResp : OUT std_uLogic
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);
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-- Declarations
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END ahbUart ;
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