1572 lines
19 KiB
Plaintext
1572 lines
19 KiB
Plaintext
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DocumentHdrVersion "1.1"
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Header (DocumentHdr
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version 2
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dmPackageRefs [
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(DmPackageRef
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library "ieee"
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unitName "std_logic_1164"
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)
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(DmPackageRef
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library "ieee"
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unitName "numeric_std"
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itemName "ALL"
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)
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]
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libraryRefs [
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"ieee"
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]
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)
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version "24.1"
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appVersion "2007.1a (Build 13)"
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model (Symbol
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commonDM (CommonDM
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ldm (LogicalDM
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suid 2009,0
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usingSuid 1
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emptyRow *1 (LEmptyRow
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)
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uid 151,0
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optionalChildren [
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*2 (RefLabelRowHdr
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)
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*3 (TitleRowHdr
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)
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||
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*4 (FilterRowHdr
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||
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)
|
||
|
*5 (RefLabelColHdr
|
||
|
tm "RefLabelColHdrMgr"
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||
|
)
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||
|
*6 (RowExpandColHdr
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|
tm "RowExpandColHdrMgr"
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||
|
)
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|
*7 (GroupColHdr
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tm "GroupColHdrMgr"
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|
)
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|
*8 (NameColHdr
|
||
|
tm "NameColHdrMgr"
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||
|
)
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||
|
*9 (ModeColHdr
|
||
|
tm "ModeColHdrMgr"
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||
|
)
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||
|
*10 (TypeColHdr
|
||
|
tm "TypeColHdrMgr"
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||
|
)
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|
*11 (BoundsColHdr
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||
|
tm "BoundsColHdrMgr"
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||
|
)
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||
|
*12 (InitColHdr
|
||
|
tm "InitColHdrMgr"
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||
|
)
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|
*13 (EolColHdr
|
||
|
tm "EolColHdrMgr"
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||
|
)
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|
*14 (LogPort
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|
port (LogicalPort
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|
m 1
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|
decl (Decl
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||
|
n "clock"
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||
|
t "std_ulogic"
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|
o 3
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|
suid 2005,0
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|
)
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|
)
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||
|
uid 208,0
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||
|
)
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|
*15 (LogPort
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port (LogicalPort
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||
|
m 1
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|
decl (Decl
|
||
|
n "reset"
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||
|
t "std_ulogic"
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||
|
o 2
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|
suid 2006,0
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|
)
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|
)
|
||
|
uid 210,0
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||
|
)
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|
*16 (LogPort
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||
|
port (LogicalPort
|
||
|
decl (Decl
|
||
|
n "triggerOut"
|
||
|
t "std_ulogic"
|
||
|
o 4
|
||
|
suid 2007,0
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||
|
)
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||
|
)
|
||
|
uid 212,0
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||
|
)
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||
|
*17 (LogPort
|
||
|
port (LogicalPort
|
||
|
decl (Decl
|
||
|
n "xOut"
|
||
|
t "std_ulogic"
|
||
|
o 5
|
||
|
suid 2008,0
|
||
|
)
|
||
|
)
|
||
|
uid 214,0
|
||
|
)
|
||
|
*18 (LogPort
|
||
|
port (LogicalPort
|
||
|
decl (Decl
|
||
|
n "yOut"
|
||
|
t "std_ulogic"
|
||
|
o 8
|
||
|
suid 2009,0
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||
|
)
|
||
|
)
|
||
|
uid 216,0
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||
|
)
|
||
|
]
|
||
|
)
|
||
|
pdm (PhysicalDM
|
||
|
uid 156,0
|
||
|
optionalChildren [
|
||
|
*19 (Sheet
|
||
|
sheetRow (SheetRow
|
||
|
headerVa (MVa
|
||
|
cellColor "49152,49152,49152"
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||
|
fontColor "0,0,0"
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||
|
font "Tahoma,10,0"
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||
|
)
|
||
|
cellVa (MVa
|
||
|
cellColor "65535,65535,65535"
|
||
|
fontColor "0,0,0"
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||
|
font "Tahoma,10,0"
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|
)
|
||
|
groupVa (MVa
|
||
|
cellColor "39936,56832,65280"
|
||
|
fontColor "0,0,0"
|
||
|
font "Tahoma,10,0"
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||
|
)
|
||
|
emptyMRCItem *20 (MRCItem
|
||
|
litem &1
|
||
|
pos 3
|
||
|
dimension 20
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||
|
)
|
||
|
uid 93,0
|
||
|
optionalChildren [
|
||
|
*21 (MRCItem
|
||
|
litem &2
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||
|
pos 0
|
||
|
dimension 20
|
||
|
uid 96,0
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||
|
)
|
||
|
*22 (MRCItem
|
||
|
litem &3
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||
|
pos 1
|
||
|
dimension 23
|
||
|
uid 98,0
|
||
|
)
|
||
|
*23 (MRCItem
|
||
|
litem &4
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||
|
pos 2
|
||
|
hidden 1
|
||
|
dimension 20
|
||
|
uid 100,0
|
||
|
)
|
||
|
*24 (MRCItem
|
||
|
litem &14
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||
|
pos 0
|
||
|
dimension 20
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||
|
uid 209,0
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||
|
)
|
||
|
*25 (MRCItem
|
||
|
litem &15
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||
|
pos 1
|
||
|
dimension 20
|
||
|
uid 211,0
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||
|
)
|
||
|
*26 (MRCItem
|
||
|
litem &16
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||
|
pos 2
|
||
|
dimension 20
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||
|
uid 213,0
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||
|
)
|
||
|
*27 (MRCItem
|
||
|
litem &17
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||
|
pos 3
|
||
|
dimension 20
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||
|
uid 215,0
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||
|
)
|
||
|
*28 (MRCItem
|
||
|
litem &18
|
||
|
pos 4
|
||
|
dimension 20
|
||
|
uid 217,0
|
||
|
)
|
||
|
]
|
||
|
)
|
||
|
sheetCol (SheetCol
|
||
|
propVa (MVa
|
||
|
cellColor "0,49152,49152"
|
||
|
fontColor "0,0,0"
|
||
|
font "Tahoma,10,0"
|
||
|
textAngle 90
|
||
|
)
|
||
|
uid 94,0
|
||
|
optionalChildren [
|
||
|
*29 (MRCItem
|
||
|
litem &5
|
||
|
pos 0
|
||
|
dimension 20
|
||
|
uid 102,0
|
||
|
)
|
||
|
*30 (MRCItem
|
||
|
litem &7
|
||
|
pos 1
|
||
|
dimension 50
|
||
|
uid 106,0
|
||
|
)
|
||
|
*31 (MRCItem
|
||
|
litem &8
|
||
|
pos 2
|
||
|
dimension 100
|
||
|
uid 108,0
|
||
|
)
|
||
|
*32 (MRCItem
|
||
|
litem &9
|
||
|
pos 3
|
||
|
dimension 50
|
||
|
uid 110,0
|
||
|
)
|
||
|
*33 (MRCItem
|
||
|
litem &10
|
||
|
pos 4
|
||
|
dimension 100
|
||
|
uid 112,0
|
||
|
)
|
||
|
*34 (MRCItem
|
||
|
litem &11
|
||
|
pos 5
|
||
|
dimension 100
|
||
|
uid 114,0
|
||
|
)
|
||
|
*35 (MRCItem
|
||
|
litem &12
|
||
|
pos 6
|
||
|
dimension 50
|
||
|
uid 116,0
|
||
|
)
|
||
|
*36 (MRCItem
|
||
|
litem &13
|
||
|
pos 7
|
||
|
dimension 80
|
||
|
uid 118,0
|
||
|
)
|
||
|
]
|
||
|
)
|
||
|
fixedCol 4
|
||
|
fixedRow 2
|
||
|
name "Ports"
|
||
|
uid 92,0
|
||
|
vaOverrides [
|
||
|
]
|
||
|
)
|
||
|
]
|
||
|
)
|
||
|
uid 150,0
|
||
|
)
|
||
|
genericsCommonDM (CommonDM
|
||
|
ldm (LogicalDM
|
||
|
emptyRow *37 (LEmptyRow
|
||
|
)
|
||
|
uid 158,0
|
||
|
optionalChildren [
|
||
|
*38 (RefLabelRowHdr
|
||
|
)
|
||
|
*39 (TitleRowHdr
|
||
|
)
|
||
|
*40 (FilterRowHdr
|
||
|
)
|
||
|
*41 (RefLabelColHdr
|
||
|
tm "RefLabelColHdrMgr"
|
||
|
)
|
||
|
*42 (RowExpandColHdr
|
||
|
tm "RowExpandColHdrMgr"
|
||
|
)
|
||
|
*43 (GroupColHdr
|
||
|
tm "GroupColHdrMgr"
|
||
|
)
|
||
|
*44 (NameColHdr
|
||
|
tm "GenericNameColHdrMgr"
|
||
|
)
|
||
|
*45 (TypeColHdr
|
||
|
tm "GenericTypeColHdrMgr"
|
||
|
)
|
||
|
*46 (InitColHdr
|
||
|
tm "GenericValueColHdrMgr"
|
||
|
)
|
||
|
*47 (PragmaColHdr
|
||
|
tm "GenericPragmaColHdrMgr"
|
||
|
)
|
||
|
*48 (EolColHdr
|
||
|
tm "GenericEolColHdrMgr"
|
||
|
)
|
||
|
*49 (LogGeneric
|
||
|
generic (GiElement
|
||
|
name "signalBitNb"
|
||
|
type "positive"
|
||
|
value "16"
|
||
|
)
|
||
|
uid 148,0
|
||
|
)
|
||
|
]
|
||
|
)
|
||
|
pdm (PhysicalDM
|
||
|
uid 159,0
|
||
|
optionalChildren [
|
||
|
*50 (Sheet
|
||
|
sheetRow (SheetRow
|
||
|
headerVa (MVa
|
||
|
cellColor "49152,49152,49152"
|
||
|
fontColor "0,0,0"
|
||
|
font "Tahoma,10,0"
|
||
|
)
|
||
|
cellVa (MVa
|
||
|
cellColor "65535,65535,65535"
|
||
|
fontColor "0,0,0"
|
||
|
font "Tahoma,10,0"
|
||
|
)
|
||
|
groupVa (MVa
|
||
|
cellColor "39936,56832,65280"
|
||
|
fontColor "0,0,0"
|
||
|
font "Tahoma,10,0"
|
||
|
)
|
||
|
emptyMRCItem *51 (MRCItem
|
||
|
litem &37
|
||
|
pos 3
|
||
|
dimension 20
|
||
|
)
|
||
|
uid 124,0
|
||
|
optionalChildren [
|
||
|
*52 (MRCItem
|
||
|
litem &38
|
||
|
pos 0
|
||
|
dimension 20
|
||
|
uid 127,0
|
||
|
)
|
||
|
*53 (MRCItem
|
||
|
litem &39
|
||
|
pos 1
|
||
|
dimension 23
|
||
|
uid 129,0
|
||
|
)
|
||
|
*54 (MRCItem
|
||
|
litem &40
|
||
|
pos 2
|
||
|
hidden 1
|
||
|
dimension 20
|
||
|
uid 131,0
|
||
|
)
|
||
|
*55 (MRCItem
|
||
|
litem &49
|
||
|
pos 0
|
||
|
dimension 20
|
||
|
uid 149,0
|
||
|
)
|
||
|
]
|
||
|
)
|
||
|
sheetCol (SheetCol
|
||
|
propVa (MVa
|
||
|
cellColor "0,49152,49152"
|
||
|
fontColor "0,0,0"
|
||
|
font "Tahoma,10,0"
|
||
|
textAngle 90
|
||
|
)
|
||
|
uid 125,0
|
||
|
optionalChildren [
|
||
|
*56 (MRCItem
|
||
|
litem &41
|
||
|
pos 0
|
||
|
dimension 20
|
||
|
uid 133,0
|
||
|
)
|
||
|
*57 (MRCItem
|
||
|
litem &43
|
||
|
pos 1
|
||
|
dimension 50
|
||
|
uid 137,0
|
||
|
)
|
||
|
*58 (MRCItem
|
||
|
litem &44
|
||
|
pos 2
|
||
|
dimension 100
|
||
|
uid 139,0
|
||
|
)
|
||
|
*59 (MRCItem
|
||
|
litem &45
|
||
|
pos 3
|
||
|
dimension 100
|
||
|
uid 141,0
|
||
|
)
|
||
|
*60 (MRCItem
|
||
|
litem &46
|
||
|
pos 4
|
||
|
dimension 50
|
||
|
uid 143,0
|
||
|
)
|
||
|
*61 (MRCItem
|
||
|
litem &47
|
||
|
pos 5
|
||
|
dimension 50
|
||
|
uid 145,0
|
||
|
)
|
||
|
*62 (MRCItem
|
||
|
litem &48
|
||
|
pos 6
|
||
|
dimension 80
|
||
|
uid 147,0
|
||
|
)
|
||
|
]
|
||
|
)
|
||
|
fixedCol 3
|
||
|
fixedRow 2
|
||
|
name "Ports"
|
||
|
uid 123,0
|
||
|
vaOverrides [
|
||
|
]
|
||
|
)
|
||
|
]
|
||
|
)
|
||
|
uid 157,0
|
||
|
type 1
|
||
|
)
|
||
|
VExpander (VariableExpander
|
||
|
vvMap [
|
||
|
(vvPair
|
||
|
variable " "
|
||
|
value " "
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "HDLDir"
|
||
|
value "U:\\SEm_labs\\Prefs\\..\\Board\\hdl"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "HDSDir"
|
||
|
value "U:\\SEm_labs\\Prefs\\..\\Board\\hds"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "SideDataDesignDir"
|
||
|
value "U:\\SEm_labs\\Prefs\\..\\Board\\hds\\@f@p@g@a_sine@gen_tester\\interface.info"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "SideDataUserDir"
|
||
|
value "U:\\SEm_labs\\Prefs\\..\\Board\\hds\\@f@p@g@a_sine@gen_tester\\interface.user"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "SourceDir"
|
||
|
value "U:\\SEm_labs\\Prefs\\..\\Board\\hds"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "appl"
|
||
|
value "HDL Designer"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "arch_name"
|
||
|
value "interface"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "concat_file"
|
||
|
value "chronometer"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "config"
|
||
|
value "%(unit)_config"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "d"
|
||
|
value "U:\\SEm_labs\\Prefs\\..\\Board\\hds\\@f@p@g@a_sine@gen_tester"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "d_logical"
|
||
|
value "U:\\SEm_labs\\Prefs\\..\\Board\\hds\\FPGA_sineGen_tester"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "date"
|
||
|
value "27.01.2010"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "day"
|
||
|
value "mer."
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "day_long"
|
||
|
value "mercredi"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "dd"
|
||
|
value "27"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "entity_name"
|
||
|
value "FPGA_sineGen_tester"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "ext"
|
||
|
value "<TBD>"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "f"
|
||
|
value "interface"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "f_logical"
|
||
|
value "interface"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "f_noext"
|
||
|
value "interface"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "group"
|
||
|
value "UNKNOWN"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "host"
|
||
|
value "WE3195"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "language"
|
||
|
value "VHDL"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "library"
|
||
|
value "Board"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "library_downstream_Concatenation"
|
||
|
value "$HDS_PROJECT_DIR/../Board/concat"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "library_downstream_Generic_1_file"
|
||
|
value "U:\\SEm_curves\\Synthesis"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "library_downstream_ModelSim"
|
||
|
value "D:\\Users\\ELN_labs\\VHDL_comp"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "library_downstream_ModelSimCompiler"
|
||
|
value "D:/Labs/ElN/Chronometer/Board/work"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "library_downstream_SpyGlass"
|
||
|
value "U:\\SEm_curves\\Synthesis"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "mm"
|
||
|
value "01"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "module_name"
|
||
|
value "FPGA_sineGen_tester"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "month"
|
||
|
value "janv."
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "month_long"
|
||
|
value "janvier"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "p"
|
||
|
value "U:\\SEm_labs\\Prefs\\..\\Board\\hds\\@f@p@g@a_sine@gen_tester\\interface"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "p_logical"
|
||
|
value "U:\\SEm_labs\\Prefs\\..\\Board\\hds\\FPGA_sineGen_tester\\interface"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "package_name"
|
||
|
value "<Undefined Variable>"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "project_name"
|
||
|
value "hds"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "series"
|
||
|
value "HDL Designer Series"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "task_ADMS"
|
||
|
value "<TBD>"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "task_DesignCompilerPath"
|
||
|
value "<TBD>"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "task_ISEPath"
|
||
|
value "D:\\Labs\\ElN\\Chronometer\\Board\\ise"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "task_LeonardoPath"
|
||
|
value "<TBD>"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "task_ModelSimPath"
|
||
|
value "C:\\EDA\\Modelsim\\win32"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "task_NC"
|
||
|
value "<TBD>"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "task_PrecisionRTLPath"
|
||
|
value "<TBD>"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "task_QuestaSimPath"
|
||
|
value "<TBD>"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "task_VCSPath"
|
||
|
value "<TBD>"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "this_ext"
|
||
|
value "<TBD>"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "this_file"
|
||
|
value "interface"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "this_file_logical"
|
||
|
value "interface"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "time"
|
||
|
value "11:20:56"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "unit"
|
||
|
value "FPGA_sineGen_tester"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "user"
|
||
|
value "cof"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "version"
|
||
|
value "2007.1a (Build 13)"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "view"
|
||
|
value "interface"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "year"
|
||
|
value "2010"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "yy"
|
||
|
value "10"
|
||
|
)
|
||
|
]
|
||
|
)
|
||
|
LanguageMgr "VhdlLangMgr"
|
||
|
uid 71,0
|
||
|
optionalChildren [
|
||
|
*63 (SymbolBody
|
||
|
uid 8,0
|
||
|
optionalChildren [
|
||
|
*64 (CptPort
|
||
|
uid 183,0
|
||
|
ps "OnEdgeStrategy"
|
||
|
shape (Triangle
|
||
|
uid 184,0
|
||
|
va (VaSet
|
||
|
vasetType 1
|
||
|
fg "0,65535,0"
|
||
|
)
|
||
|
xt "22625,5250,23375,6000"
|
||
|
)
|
||
|
tg (CPTG
|
||
|
uid 185,0
|
||
|
ps "CptPortTextPlaceStrategy"
|
||
|
stg "RightVerticalLayoutStrategy"
|
||
|
f (Text
|
||
|
uid 186,0
|
||
|
ro 270
|
||
|
va (VaSet
|
||
|
)
|
||
|
xt "22500,7000,23500,9100"
|
||
|
st "clock"
|
||
|
ju 2
|
||
|
blo "23300,7000"
|
||
|
tm "CptPortNameMgr"
|
||
|
)
|
||
|
)
|
||
|
dt (MLText
|
||
|
uid 187,0
|
||
|
va (VaSet
|
||
|
font "Courier New,8,0"
|
||
|
)
|
||
|
xt "44000,4400,62000,5200"
|
||
|
st "clock : OUT std_ulogic ;
|
||
|
"
|
||
|
)
|
||
|
thePort (LogicalPort
|
||
|
m 1
|
||
|
decl (Decl
|
||
|
n "clock"
|
||
|
t "std_ulogic"
|
||
|
o 3
|
||
|
suid 2005,0
|
||
|
)
|
||
|
)
|
||
|
)
|
||
|
*65 (CptPort
|
||
|
uid 188,0
|
||
|
ps "OnEdgeStrategy"
|
||
|
shape (Triangle
|
||
|
uid 189,0
|
||
|
va (VaSet
|
||
|
vasetType 1
|
||
|
fg "0,65535,0"
|
||
|
)
|
||
|
xt "24625,5250,25375,6000"
|
||
|
)
|
||
|
tg (CPTG
|
||
|
uid 190,0
|
||
|
ps "CptPortTextPlaceStrategy"
|
||
|
stg "RightVerticalLayoutStrategy"
|
||
|
f (Text
|
||
|
uid 191,0
|
||
|
ro 270
|
||
|
va (VaSet
|
||
|
)
|
||
|
xt "24500,7000,25500,9100"
|
||
|
st "reset"
|
||
|
ju 2
|
||
|
blo "25300,7000"
|
||
|
tm "CptPortNameMgr"
|
||
|
)
|
||
|
)
|
||
|
dt (MLText
|
||
|
uid 192,0
|
||
|
va (VaSet
|
||
|
font "Courier New,8,0"
|
||
|
)
|
||
|
xt "44000,5200,61000,6000"
|
||
|
st "reset : OUT std_ulogic
|
||
|
"
|
||
|
)
|
||
|
thePort (LogicalPort
|
||
|
m 1
|
||
|
decl (Decl
|
||
|
n "reset"
|
||
|
t "std_ulogic"
|
||
|
o 2
|
||
|
suid 2006,0
|
||
|
)
|
||
|
)
|
||
|
)
|
||
|
*66 (CptPort
|
||
|
uid 193,0
|
||
|
ps "OnEdgeStrategy"
|
||
|
shape (Triangle
|
||
|
uid 194,0
|
||
|
ro 180
|
||
|
va (VaSet
|
||
|
vasetType 1
|
||
|
fg "0,65535,0"
|
||
|
)
|
||
|
xt "56625,5250,57375,6000"
|
||
|
)
|
||
|
tg (CPTG
|
||
|
uid 195,0
|
||
|
ps "CptPortTextPlaceStrategy"
|
||
|
stg "RightVerticalLayoutStrategy"
|
||
|
f (Text
|
||
|
uid 196,0
|
||
|
ro 270
|
||
|
va (VaSet
|
||
|
)
|
||
|
xt "56500,7000,57500,11400"
|
||
|
st "triggerOut"
|
||
|
ju 2
|
||
|
blo "57300,7000"
|
||
|
tm "CptPortNameMgr"
|
||
|
)
|
||
|
)
|
||
|
dt (MLText
|
||
|
uid 197,0
|
||
|
va (VaSet
|
||
|
font "Courier New,8,0"
|
||
|
)
|
||
|
xt "44000,2000,62000,2800"
|
||
|
st "triggerOut : IN std_ulogic ;
|
||
|
"
|
||
|
)
|
||
|
thePort (LogicalPort
|
||
|
decl (Decl
|
||
|
n "triggerOut"
|
||
|
t "std_ulogic"
|
||
|
o 4
|
||
|
suid 2007,0
|
||
|
)
|
||
|
)
|
||
|
)
|
||
|
*67 (CptPort
|
||
|
uid 198,0
|
||
|
ps "OnEdgeStrategy"
|
||
|
shape (Triangle
|
||
|
uid 199,0
|
||
|
ro 180
|
||
|
va (VaSet
|
||
|
vasetType 1
|
||
|
fg "0,65535,0"
|
||
|
)
|
||
|
xt "58625,5250,59375,6000"
|
||
|
)
|
||
|
tg (CPTG
|
||
|
uid 200,0
|
||
|
ps "CptPortTextPlaceStrategy"
|
||
|
stg "RightVerticalLayoutStrategy"
|
||
|
f (Text
|
||
|
uid 201,0
|
||
|
ro 270
|
||
|
va (VaSet
|
||
|
)
|
||
|
xt "58500,7000,59500,8900"
|
||
|
st "xOut"
|
||
|
ju 2
|
||
|
blo "59300,7000"
|
||
|
tm "CptPortNameMgr"
|
||
|
)
|
||
|
)
|
||
|
dt (MLText
|
||
|
uid 202,0
|
||
|
va (VaSet
|
||
|
font "Courier New,8,0"
|
||
|
)
|
||
|
xt "44000,2800,62000,3600"
|
||
|
st "xOut : IN std_ulogic ;
|
||
|
"
|
||
|
)
|
||
|
thePort (LogicalPort
|
||
|
decl (Decl
|
||
|
n "xOut"
|
||
|
t "std_ulogic"
|
||
|
o 5
|
||
|
suid 2008,0
|
||
|
)
|
||
|
)
|
||
|
)
|
||
|
*68 (CptPort
|
||
|
uid 203,0
|
||
|
ps "OnEdgeStrategy"
|
||
|
shape (Triangle
|
||
|
uid 204,0
|
||
|
ro 180
|
||
|
va (VaSet
|
||
|
vasetType 1
|
||
|
fg "0,65535,0"
|
||
|
)
|
||
|
xt "60625,5250,61375,6000"
|
||
|
)
|
||
|
tg (CPTG
|
||
|
uid 205,0
|
||
|
ps "CptPortTextPlaceStrategy"
|
||
|
stg "RightVerticalLayoutStrategy"
|
||
|
f (Text
|
||
|
uid 206,0
|
||
|
ro 270
|
||
|
va (VaSet
|
||
|
)
|
||
|
xt "60500,7000,61500,8900"
|
||
|
st "yOut"
|
||
|
ju 2
|
||
|
blo "61300,7000"
|
||
|
tm "CptPortNameMgr"
|
||
|
)
|
||
|
)
|
||
|
dt (MLText
|
||
|
uid 207,0
|
||
|
va (VaSet
|
||
|
font "Courier New,8,0"
|
||
|
)
|
||
|
xt "44000,3600,62000,4400"
|
||
|
st "yOut : IN std_ulogic ;
|
||
|
"
|
||
|
)
|
||
|
thePort (LogicalPort
|
||
|
decl (Decl
|
||
|
n "yOut"
|
||
|
t "std_ulogic"
|
||
|
o 8
|
||
|
suid 2009,0
|
||
|
)
|
||
|
)
|
||
|
)
|
||
|
]
|
||
|
shape (Rectangle
|
||
|
uid 9,0
|
||
|
va (VaSet
|
||
|
vasetType 1
|
||
|
fg "0,65535,0"
|
||
|
lineColor "0,32896,0"
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||
|
lineWidth 2
|
||
|
)
|
||
|
xt "15000,6000,67000,14000"
|
||
|
)
|
||
|
oxt "15000,6000,59000,14000"
|
||
|
biTextGroup (BiTextGroup
|
||
|
uid 10,0
|
||
|
ps "CenterOffsetStrategy"
|
||
|
stg "VerticalLayoutStrategy"
|
||
|
first (Text
|
||
|
uid 11,0
|
||
|
va (VaSet
|
||
|
font "Verdana,9,1"
|
||
|
)
|
||
|
xt "34900,8800,38400,10000"
|
||
|
st "Board"
|
||
|
blo "34900,9800"
|
||
|
)
|
||
|
second (Text
|
||
|
uid 12,0
|
||
|
va (VaSet
|
||
|
font "Verdana,9,1"
|
||
|
)
|
||
|
xt "34900,10000,47100,11200"
|
||
|
st "FPGA_sineGen_tester"
|
||
|
blo "34900,11000"
|
||
|
)
|
||
|
)
|
||
|
gi *69 (GenericInterface
|
||
|
uid 13,0
|
||
|
ps "CenterOffsetStrategy"
|
||
|
matrix (Matrix
|
||
|
uid 14,0
|
||
|
text (MLText
|
||
|
uid 15,0
|
||
|
va (VaSet
|
||
|
font "Courier New,8,0"
|
||
|
)
|
||
|
xt "16000,6000,30000,8400"
|
||
|
st "Generic Declarations
|
||
|
|
||
|
signalBitNb positive 16
|
||
|
"
|
||
|
)
|
||
|
header "Generic Declarations"
|
||
|
showHdrWhenContentsEmpty 1
|
||
|
)
|
||
|
elements [
|
||
|
(GiElement
|
||
|
name "signalBitNb"
|
||
|
type "positive"
|
||
|
value "16"
|
||
|
)
|
||
|
]
|
||
|
)
|
||
|
portInstanceVisAsIs 1
|
||
|
portInstanceVis (PortSigDisplay
|
||
|
sTC 0
|
||
|
sF 0
|
||
|
)
|
||
|
portVis (PortSigDisplay
|
||
|
sTC 0
|
||
|
sF 0
|
||
|
)
|
||
|
)
|
||
|
*70 (Grouping
|
||
|
uid 16,0
|
||
|
optionalChildren [
|
||
|
*71 (CommentText
|
||
|
uid 18,0
|
||
|
shape (Rectangle
|
||
|
uid 19,0
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||
|
sl 0
|
||
|
va (VaSet
|
||
|
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||
|
fg "65280,65280,46080"
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|
)
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||
|
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|
||
|
)
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||
|
oxt "18000,70000,35000,71000"
|
||
|
text (MLText
|
||
|
uid 20,0
|
||
|
va (VaSet
|
||
|
fg "0,0,32768"
|
||
|
bg "0,0,32768"
|
||
|
)
|
||
|
xt "36200,48000,44800,49000"
|
||
|
st "
|
||
|
by %user on %dd %month %year
|
||
|
"
|
||
|
tm "CommentText"
|
||
|
wrapOption 3
|
||
|
visibleHeight 1000
|
||
|
visibleWidth 17000
|
||
|
)
|
||
|
position 1
|
||
|
ignorePrefs 1
|
||
|
)
|
||
|
*72 (CommentText
|
||
|
uid 21,0
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|
shape (Rectangle
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||
|
uid 22,0
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|
sl 0
|
||
|
va (VaSet
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||
|
vasetType 1
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||
|
fg "65280,65280,46080"
|
||
|
)
|
||
|
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|
||
|
)
|
||
|
oxt "35000,66000,39000,67000"
|
||
|
text (MLText
|
||
|
uid 23,0
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|
va (VaSet
|
||
|
fg "0,0,32768"
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|
bg "0,0,32768"
|
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|
)
|
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|
xt "53200,44000,56200,45000"
|
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|
st "
|
||
|
Project:
|
||
|
"
|
||
|
tm "CommentText"
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|
wrapOption 3
|
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|
visibleHeight 1000
|
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|
visibleWidth 4000
|
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|
)
|
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|
position 1
|
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|
ignorePrefs 1
|
||
|
)
|
||
|
*73 (CommentText
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|
uid 24,0
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|
shape (Rectangle
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|
uid 25,0
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|
sl 0
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|
va (VaSet
|
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|
vasetType 1
|
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|
fg "65280,65280,46080"
|
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|
)
|
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isHidden 1
|
||
|
font "Courier New,8,0"
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||
|
)
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||
|
xt "42000,0,42000,0"
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tm "SyDeclarativeTextMgr"
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||
|
)
|
||
|
)
|
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|
lastUid 217,0
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||
|
)
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