1330 lines
17 KiB
Plaintext
1330 lines
17 KiB
Plaintext
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DocumentHdrVersion "1.1"
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Header (DocumentHdr
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version 2
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dialect 11
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dmPackageRefs [
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(DmPackageRef
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library "ieee"
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unitName "std_logic_1164"
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)
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(DmPackageRef
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library "ieee"
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unitName "numeric_std"
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)
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(DmPackageRef
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library "gates"
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unitName "gates"
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)
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]
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libraryRefs [
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"ieee"
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"gates"
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]
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)
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version "27.1"
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appVersion "2019.2 (Build 5)"
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model (Symbol
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commonDM (CommonDM
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ldm (LogicalDM
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suid 1,0
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usingSuid 1
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emptyRow *1 (LEmptyRow
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)
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uid 60,0
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|
optionalChildren [
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|
*2 (RefLabelRowHdr
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)
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*3 (TitleRowHdr
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|
)
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||
|
*4 (FilterRowHdr
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||
|
)
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||
|
*5 (RefLabelColHdr
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||
|
tm "RefLabelColHdrMgr"
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||
|
)
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||
|
*6 (RowExpandColHdr
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|
tm "RowExpandColHdrMgr"
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||
|
)
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||
|
*7 (GroupColHdr
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||
|
tm "GroupColHdrMgr"
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||
|
)
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|
*8 (NameColHdr
|
||
|
tm "NameColHdrMgr"
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||
|
)
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|
*9 (ModeColHdr
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|
tm "ModeColHdrMgr"
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|
)
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||
|
*10 (TypeColHdr
|
||
|
tm "TypeColHdrMgr"
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||
|
)
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||
|
*11 (BoundsColHdr
|
||
|
tm "BoundsColHdrMgr"
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||
|
)
|
||
|
*12 (InitColHdr
|
||
|
tm "InitColHdrMgr"
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|
)
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|
*13 (EolColHdr
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||
|
tm "EolColHdrMgr"
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||
|
)
|
||
|
*14 (LogPort
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|
port (LogicalPort
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||
|
lang 11
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|
decl (Decl
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|
n "PC"
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|
t "unsigned"
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||
|
b "(g_bitNb - 1 DOWNTO 0)"
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|
o 32
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|
suid 1,0
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)
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)
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|
uid 56,0
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)
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]
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|
)
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|
pdm (PhysicalDM
|
||
|
displayShortBounds 1
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||
|
editShortBounds 1
|
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|
uid 73,0
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||
|
optionalChildren [
|
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|
*15 (Sheet
|
||
|
sheetRow (SheetRow
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|
headerVa (MVa
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|
cellColor "49152,49152,49152"
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||
|
fontColor "0,0,0"
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||
|
font "Tahoma,10,0"
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|
)
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|
cellVa (MVa
|
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|
cellColor "65535,65535,65535"
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||
|
fontColor "0,0,0"
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||
|
font "Tahoma,10,0"
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|
)
|
||
|
groupVa (MVa
|
||
|
cellColor "39936,56832,65280"
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||
|
fontColor "0,0,0"
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||
|
font "Tahoma,10,0"
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||
|
)
|
||
|
emptyMRCItem *16 (MRCItem
|
||
|
litem &1
|
||
|
pos 3
|
||
|
dimension 20
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||
|
)
|
||
|
uid 75,0
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|
optionalChildren [
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||
|
*17 (MRCItem
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||
|
litem &2
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||
|
pos 0
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||
|
dimension 20
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|
uid 76,0
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)
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*18 (MRCItem
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|
litem &3
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|
pos 1
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|
dimension 23
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|
uid 77,0
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)
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*19 (MRCItem
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|
litem &4
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pos 2
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|
hidden 1
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|
dimension 20
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uid 78,0
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||
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)
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*20 (MRCItem
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|
litem &14
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pos 0
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dimension 20
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uid 57,0
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)
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]
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|
)
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|
sheetCol (SheetCol
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||
|
propVa (MVa
|
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|
cellColor "0,49152,49152"
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||
|
fontColor "0,0,0"
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||
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font "Tahoma,10,0"
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|
textAngle 90
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|
)
|
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|
uid 79,0
|
||
|
optionalChildren [
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|
*21 (MRCItem
|
||
|
litem &5
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|
pos 0
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|
dimension 20
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|
uid 80,0
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)
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|
*22 (MRCItem
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|
litem &7
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|
pos 1
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|
dimension 50
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|
uid 81,0
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||
|
)
|
||
|
*23 (MRCItem
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||
|
litem &8
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||
|
pos 2
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|
dimension 100
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||
|
uid 82,0
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||
|
)
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|
*24 (MRCItem
|
||
|
litem &9
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||
|
pos 3
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|
dimension 50
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|
uid 83,0
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|
)
|
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|
*25 (MRCItem
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||
|
litem &10
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|
pos 4
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|
dimension 100
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||
|
uid 84,0
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||
|
)
|
||
|
*26 (MRCItem
|
||
|
litem &11
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||
|
pos 5
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||
|
dimension 100
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||
|
uid 85,0
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||
|
)
|
||
|
*27 (MRCItem
|
||
|
litem &12
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||
|
pos 6
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|
dimension 50
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||
|
uid 86,0
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||
|
)
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||
|
*28 (MRCItem
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||
|
litem &13
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||
|
pos 7
|
||
|
dimension 80
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||
|
uid 87,0
|
||
|
)
|
||
|
]
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||
|
)
|
||
|
fixedCol 4
|
||
|
fixedRow 2
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||
|
name "Ports"
|
||
|
uid 74,0
|
||
|
vaOverrides [
|
||
|
]
|
||
|
)
|
||
|
]
|
||
|
)
|
||
|
uid 59,0
|
||
|
)
|
||
|
genericsCommonDM (CommonDM
|
||
|
ldm (LogicalDM
|
||
|
emptyRow *29 (LEmptyRow
|
||
|
)
|
||
|
uid 89,0
|
||
|
optionalChildren [
|
||
|
*30 (RefLabelRowHdr
|
||
|
)
|
||
|
*31 (TitleRowHdr
|
||
|
)
|
||
|
*32 (FilterRowHdr
|
||
|
)
|
||
|
*33 (RefLabelColHdr
|
||
|
tm "RefLabelColHdrMgr"
|
||
|
)
|
||
|
*34 (RowExpandColHdr
|
||
|
tm "RowExpandColHdrMgr"
|
||
|
)
|
||
|
*35 (GroupColHdr
|
||
|
tm "GroupColHdrMgr"
|
||
|
)
|
||
|
*36 (NameColHdr
|
||
|
tm "GenericNameColHdrMgr"
|
||
|
)
|
||
|
*37 (TypeColHdr
|
||
|
tm "GenericTypeColHdrMgr"
|
||
|
)
|
||
|
*38 (InitColHdr
|
||
|
tm "GenericValueColHdrMgr"
|
||
|
)
|
||
|
*39 (PragmaColHdr
|
||
|
tm "GenericPragmaColHdrMgr"
|
||
|
)
|
||
|
*40 (EolColHdr
|
||
|
tm "GenericEolColHdrMgr"
|
||
|
)
|
||
|
]
|
||
|
)
|
||
|
pdm (PhysicalDM
|
||
|
displayShortBounds 1
|
||
|
editShortBounds 1
|
||
|
uid 101,0
|
||
|
optionalChildren [
|
||
|
*41 (Sheet
|
||
|
sheetRow (SheetRow
|
||
|
headerVa (MVa
|
||
|
cellColor "49152,49152,49152"
|
||
|
fontColor "0,0,0"
|
||
|
font "Tahoma,10,0"
|
||
|
)
|
||
|
cellVa (MVa
|
||
|
cellColor "65535,65535,65535"
|
||
|
fontColor "0,0,0"
|
||
|
font "Tahoma,10,0"
|
||
|
)
|
||
|
groupVa (MVa
|
||
|
cellColor "39936,56832,65280"
|
||
|
fontColor "0,0,0"
|
||
|
font "Tahoma,10,0"
|
||
|
)
|
||
|
emptyMRCItem *42 (MRCItem
|
||
|
litem &29
|
||
|
pos 3
|
||
|
dimension 20
|
||
|
)
|
||
|
uid 103,0
|
||
|
optionalChildren [
|
||
|
*43 (MRCItem
|
||
|
litem &30
|
||
|
pos 0
|
||
|
dimension 20
|
||
|
uid 104,0
|
||
|
)
|
||
|
*44 (MRCItem
|
||
|
litem &31
|
||
|
pos 1
|
||
|
dimension 23
|
||
|
uid 105,0
|
||
|
)
|
||
|
*45 (MRCItem
|
||
|
litem &32
|
||
|
pos 2
|
||
|
hidden 1
|
||
|
dimension 20
|
||
|
uid 106,0
|
||
|
)
|
||
|
]
|
||
|
)
|
||
|
sheetCol (SheetCol
|
||
|
propVa (MVa
|
||
|
cellColor "0,49152,49152"
|
||
|
fontColor "0,0,0"
|
||
|
font "Tahoma,10,0"
|
||
|
textAngle 90
|
||
|
)
|
||
|
uid 107,0
|
||
|
optionalChildren [
|
||
|
*46 (MRCItem
|
||
|
litem &33
|
||
|
pos 0
|
||
|
dimension 20
|
||
|
uid 108,0
|
||
|
)
|
||
|
*47 (MRCItem
|
||
|
litem &35
|
||
|
pos 1
|
||
|
dimension 50
|
||
|
uid 109,0
|
||
|
)
|
||
|
*48 (MRCItem
|
||
|
litem &36
|
||
|
pos 2
|
||
|
dimension 100
|
||
|
uid 110,0
|
||
|
)
|
||
|
*49 (MRCItem
|
||
|
litem &37
|
||
|
pos 3
|
||
|
dimension 100
|
||
|
uid 111,0
|
||
|
)
|
||
|
*50 (MRCItem
|
||
|
litem &38
|
||
|
pos 4
|
||
|
dimension 50
|
||
|
uid 112,0
|
||
|
)
|
||
|
*51 (MRCItem
|
||
|
litem &39
|
||
|
pos 5
|
||
|
dimension 50
|
||
|
uid 113,0
|
||
|
)
|
||
|
*52 (MRCItem
|
||
|
litem &40
|
||
|
pos 6
|
||
|
dimension 80
|
||
|
uid 114,0
|
||
|
)
|
||
|
]
|
||
|
)
|
||
|
fixedCol 3
|
||
|
fixedRow 2
|
||
|
name "Ports"
|
||
|
uid 102,0
|
||
|
vaOverrides [
|
||
|
]
|
||
|
)
|
||
|
]
|
||
|
)
|
||
|
uid 88,0
|
||
|
type 1
|
||
|
)
|
||
|
VExpander (VariableExpander
|
||
|
vvMap [
|
||
|
(vvPair
|
||
|
variable "HDLDir"
|
||
|
value "C:\\dev\\car-labs\\hdl\\Prefs\\..\\RiscV\\HEIRV32\\SingleCycle\\hdl"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "HDSDir"
|
||
|
value "C:\\dev\\car-labs\\hdl\\Prefs\\..\\RiscV\\HEIRV32\\SingleCycle\\hds"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "SideDataDesignDir"
|
||
|
value "C:\\dev\\car-labs\\hdl\\Prefs\\..\\RiscV\\HEIRV32\\SingleCycle\\hds\\rtl\\interface.info"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "SideDataUserDir"
|
||
|
value "C:\\dev\\car-labs\\hdl\\Prefs\\..\\RiscV\\HEIRV32\\SingleCycle\\hds\\rtl\\interface.user"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "SourceDir"
|
||
|
value "C:\\dev\\car-labs\\hdl\\Prefs\\..\\RiscV\\HEIRV32\\SingleCycle\\hds"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "appl"
|
||
|
value "HDL Designer"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "arch_name"
|
||
|
value "interface"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "concat_file"
|
||
|
value "concatenated"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "config"
|
||
|
value "%(unit)_%(view)_config"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "d"
|
||
|
value "C:\\dev\\car-labs\\hdl\\Prefs\\..\\RiscV\\HEIRV32\\SingleCycle\\hds\\rtl"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "d_logical"
|
||
|
value "C:\\dev\\car-labs\\hdl\\Prefs\\..\\RiscV\\HEIRV32\\SingleCycle\\hds\\rtl"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "date"
|
||
|
value "03.11.2022"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "day"
|
||
|
value "jeu."
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "day_long"
|
||
|
value "jeudi"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "dd"
|
||
|
value "03"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "entity_name"
|
||
|
value "rtl"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "ext"
|
||
|
value "<TBD>"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "f"
|
||
|
value "interface"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "f_logical"
|
||
|
value "interface"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "f_noext"
|
||
|
value "interface"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "graphical_source_author"
|
||
|
value "axel.amand"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "graphical_source_date"
|
||
|
value "03.11.2022"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "graphical_source_group"
|
||
|
value "UNKNOWN"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "graphical_source_host"
|
||
|
value "WE7860"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "graphical_source_time"
|
||
|
value "13:14:50"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "group"
|
||
|
value "UNKNOWN"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "host"
|
||
|
value "WE7860"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "language"
|
||
|
value "VHDL"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "library"
|
||
|
value "HEIRV32_SC"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "library_downstream_Concatenation"
|
||
|
value "$HDS_PROJECT_DIR/../Board/concat"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "library_downstream_ModelSimCompiler"
|
||
|
value "$SCRATCH_DIR/CAr/RiscV/HEIRV32/SingleCycle/work"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "mm"
|
||
|
value "11"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "module_name"
|
||
|
value "rtl"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "month"
|
||
|
value "nov."
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "month_long"
|
||
|
value "novembre"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "p"
|
||
|
value "C:\\dev\\car-labs\\hdl\\Prefs\\..\\RiscV\\HEIRV32\\SingleCycle\\hds\\rtl\\interface"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "p_logical"
|
||
|
value "C:\\dev\\car-labs\\hdl\\Prefs\\..\\RiscV\\HEIRV32\\SingleCycle\\hds\\rtl\\interface"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "package_name"
|
||
|
value "<Undefined Variable>"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "project_name"
|
||
|
value "hds"
|
||
|
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variable "version"
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