49 lines
1.6 KiB
VHDL
49 lines
1.6 KiB
VHDL
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ARCHITECTURE test OF parallelAdder_tester IS
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constant clockPeriod: time := (1.0/clockFrequency) * 1 sec;
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signal sClock: std_uLogic := '1';
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signal sReset: std_uLogic := '1';
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constant aMax: signed(a'range) := (a'high => '0', others => '1');
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constant aIncr: signed(a'range) := shift_right(aMax, 4)+1;
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constant bIncr: signed(b'range) := shift_right(aMax, 4)+1;
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signal a_int, b_int, sum_int: signed(a'range);
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BEGIN
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------------------------------------------------------------------------------
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-- clock and reset
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sClock <= not sClock after clockPeriod/2;
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sReset <= '1', '0' after 2*clockPeriod;
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------------------------------------------------------------------------------
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-- test sequence
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process
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begin
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a_int <= (a_int'high => '1', others => '0');
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b_int <= (b_int'high => '1', others => '0');
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wait until sReset = '0';
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-- data values
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while a_int < aMax-aIncr loop
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a_int <= a_int + aIncr;
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b_int <= b_int + bIncr;
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wait until rising_edge(sClock);
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assert sum = a_int + b_int
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report "sum is wrong !"
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severity error;
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end loop;
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-- stop simulation
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assert false
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report cr & cr &
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"End of Simulation" &
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cr
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severity failure;
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wait;
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end process;
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cIn <= '0';
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a <= a_int;
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b <= b_int;
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sum_int <= a_int + b_int;
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END ARCHITECTURE test;
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