25 lines
749 B
VHDL
25 lines
749 B
VHDL
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--
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-- VHDL Architecture PipelinedOperators_test.PipelineCounter_tester.test
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--
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-- Created:
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-- by - zas.UNKNOWN (ZELL)
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-- at - 16:00:38 02/20/2020
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--
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-- using Mentor Graphics HDL Designer(TM) 2019.2 (Build 5)
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--
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ARCHITECTURE test OF PipelineCounter_tester IS
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constant clockFrequency: real := 66.0E6;
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constant clockPeriod: time := (1.0/clockFrequency) * 1 sec;
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signal sClock: std_uLogic := '1';
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BEGIN
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------------------------------------------------------------------------------
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-- clock and reset
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sClock <= not sClock after clockPeriod/2;
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clock <= transport sClock after clockPeriod*9/10;
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reset <= '1', '0' after 2*clockPeriod;
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END ARCHITECTURE test;
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