SEm-Labos/zz-solutions/03-DigitalToAnalogConverter/DigitalToAnalogConverter_test/hdl/dac_tb_struct.vhg

--
-- VHDL Architecture DigitalToAnalogConverter_test.DAC_tb.struct
--
-- Created:
--          by - axel.amand.UNKNOWN (WE7860)
--          at - 14:43:18 28.04.2023
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5)
--
LIBRARY ieee;
  USE ieee.std_logic_1164.all;
  USE ieee.numeric_std.ALL;

LIBRARY DigitalToAnalogConverter;
LIBRARY DigitalToAnalogConverter_test;
LIBRARY WaveformGenerator;

ARCHITECTURE struct OF DAC_tb IS

    -- Architecture declarations
    constant signalBitNb: positive := 16;
    constant lowpassShiftBitNb: positive := 8;
    constant clockFrequency: real := 60.0E6;
    --constant clockFrequency: real := 66.0E6;

    -- Internal signal declarations
    SIGNAL clock      : std_ulogic;
    SIGNAL lowpassIn  : unsigned(signalBitNb-1 DOWNTO 0);
    SIGNAL lowpassOut : unsigned(signalBitNb-1 DOWNTO 0);
    SIGNAL parallelIn : unsigned(signalBitNb-1 DOWNTO 0);
    SIGNAL reset      : std_ulogic;
    SIGNAL serialOut  : std_ulogic;


    -- Component Declarations
    COMPONENT DAC
    GENERIC (
        signalBitNb : positive := 16
    );
    PORT (
        serialOut  : OUT    std_ulogic ;
        parallelIn : IN     unsigned (signalBitNb-1 DOWNTO 0);
        clock      : IN     std_ulogic ;
        reset      : IN     std_ulogic 
    );
    END COMPONENT;
    COMPONENT DAC_tester
    GENERIC (
        signalBitNb    : positive := 16;
        clockFrequency : real     := 60.0E6
    );
    PORT (
        lowpassOut : IN     unsigned (signalBitNb-1 DOWNTO 0);
        serialOut  : IN     std_ulogic ;
        clock      : OUT    std_ulogic ;
        parallelIn : OUT    unsigned (signalBitNb-1 DOWNTO 0);
        reset      : OUT    std_ulogic 
    );
    END COMPONENT;
    COMPONENT lowpass
    GENERIC (
        signalBitNb : positive := 16;
        shiftBitNb  : positive := 12
    );
    PORT (
        lowpassOut : OUT    unsigned (signalBitNb-1 DOWNTO 0);
        clock      : IN     std_ulogic ;
        reset      : IN     std_ulogic ;
        lowpassIn  : IN     unsigned (signalBitNb-1 DOWNTO 0)
    );
    END COMPONENT;

    -- Optional embedded configurations
    -- pragma synthesis_off
    FOR ALL : DAC USE ENTITY DigitalToAnalogConverter.DAC;
    FOR ALL : DAC_tester USE ENTITY DigitalToAnalogConverter_test.DAC_tester;
    FOR ALL : lowpass USE ENTITY WaveformGenerator.lowpass;
    -- pragma synthesis_on


BEGIN
    -- Architecture concurrent statements
    -- HDL Embedded Text Block 1 eb1
    LowpassIn <= (others => serialOut);


    -- Instance port mappings.
    I_DUT : DAC
        GENERIC MAP (
            signalBitNb => signalBitNb
        )
        PORT MAP (
            serialOut  => serialOut,
            parallelIn => parallelIn,
            clock      => clock,
            reset      => reset
        );
    I_tester : DAC_tester
        GENERIC MAP (
            signalBitNb    => signalBitNb,
            clockFrequency => clockFrequency
        )
        PORT MAP (
            lowpassOut => lowpassOut,
            serialOut  => serialOut,
            clock      => clock,
            parallelIn => parallelIn,
            reset      => reset
        );
    I_filt : lowpass
        GENERIC MAP (
            signalBitNb => signalBitNb,
            shiftBitNb  => lowpassShiftBitNb
        )
        PORT MAP (
            lowpassOut => lowpassOut,
            clock      => clock,
            reset      => reset,
            lowpassIn  => lowpassIn
        );

END struct;