1941 lines
24 KiB
Plaintext
1941 lines
24 KiB
Plaintext
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DocumentHdrVersion "1.1"
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Header (DocumentHdr
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version 2
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dialect 11
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dmPackageRefs [
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(DmPackageRef
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library "ieee"
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unitName "std_logic_1164"
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)
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(DmPackageRef
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library "ieee"
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unitName "numeric_std"
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itemName "ALL"
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)
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]
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libraryRefs [
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"ieee"
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]
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)
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version "27.1"
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appVersion "2019.2 (Build 5)"
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model (Symbol
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commonDM (CommonDM
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ldm (LogicalDM
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suid 2192,0
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usingSuid 1
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emptyRow *1 (LEmptyRow
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)
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uid 296,0
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optionalChildren [
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*2 (RefLabelRowHdr
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)
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*3 (TitleRowHdr
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)
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*4 (FilterRowHdr
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)
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||
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*5 (RefLabelColHdr
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tm "RefLabelColHdrMgr"
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)
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*6 (RowExpandColHdr
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tm "RowExpandColHdrMgr"
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)
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*7 (GroupColHdr
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tm "GroupColHdrMgr"
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)
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*8 (NameColHdr
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tm "NameColHdrMgr"
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)
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*9 (ModeColHdr
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tm "ModeColHdrMgr"
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)
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*10 (TypeColHdr
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tm "TypeColHdrMgr"
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)
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*11 (BoundsColHdr
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tm "BoundsColHdrMgr"
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)
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*12 (InitColHdr
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tm "InitColHdrMgr"
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)
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*13 (EolColHdr
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tm "EolColHdrMgr"
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)
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*14 (LogPort
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port (LogicalPort
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m 1
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decl (Decl
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n "clock"
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t "std_ulogic"
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o 3
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suid 2184,0
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)
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)
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uid 2232,0
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)
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*15 (LogPort
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port (LogicalPort
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m 2
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decl (Decl
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n "io"
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t "std_logic_vector"
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b "(ioNb-1 DOWNTO 0)"
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o 4
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suid 2185,0
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)
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)
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|
uid 2234,0
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)
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*16 (LogPort
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port (LogicalPort
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decl (Decl
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n "lowpassOutY"
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|
t "unsigned"
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|
b "(signalBitNb-1 DOWNTO 0)"
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|
o 9
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suid 2186,0
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)
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)
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uid 2236,0
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)
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|
*17 (LogPort
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port (LogicalPort
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|
decl (Decl
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|
n "outX"
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|
t "std_ulogic"
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|
o 10
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suid 2187,0
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)
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)
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|
uid 2238,0
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)
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*18 (LogPort
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port (LogicalPort
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|
decl (Decl
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n "outY"
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|
t "std_ulogic"
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|
o 11
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suid 2188,0
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)
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)
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uid 2240,0
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)
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*19 (LogPort
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port (LogicalPort
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m 1
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decl (Decl
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n "reset"
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t "std_ulogic"
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o 12
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suid 2189,0
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)
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)
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uid 2242,0
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)
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*20 (LogPort
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port (LogicalPort
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|
m 1
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decl (Decl
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|
n "RxD"
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t "std_ulogic"
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|
o 1
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suid 2190,0
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|
)
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)
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uid 2244,0
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|
)
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*21 (LogPort
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port (LogicalPort
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|
m 1
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|
decl (Decl
|
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|
n "selSinCos"
|
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|
t "std_ulogic"
|
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|
o 13
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|
suid 2191,0
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|
)
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)
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|
uid 2246,0
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|
)
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|
*22 (LogPort
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|
port (LogicalPort
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||
|
decl (Decl
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||
|
n "TxD"
|
||
|
t "std_ulogic"
|
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|
o 2
|
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suid 2192,0
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|
)
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)
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|
uid 2248,0
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|
)
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]
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|
)
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|
pdm (PhysicalDM
|
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|
uid 309,0
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|
optionalChildren [
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|
*23 (Sheet
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|
sheetRow (SheetRow
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|
headerVa (MVa
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||
|
cellColor "49152,49152,49152"
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||
|
fontColor "0,0,0"
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||
|
font "Tahoma,10,0"
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)
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|
cellVa (MVa
|
||
|
cellColor "65535,65535,65535"
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||
|
fontColor "0,0,0"
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||
|
font "Tahoma,10,0"
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|
)
|
||
|
groupVa (MVa
|
||
|
cellColor "39936,56832,65280"
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|
fontColor "0,0,0"
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||
|
font "Tahoma,10,0"
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|
)
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|
emptyMRCItem *24 (MRCItem
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|
litem &1
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|
pos 9
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dimension 20
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)
|
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|
uid 228,0
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||
|
optionalChildren [
|
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|
*25 (MRCItem
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||
|
litem &2
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|
pos 0
|
||
|
dimension 20
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||
|
uid 231,0
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)
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|
*26 (MRCItem
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|
litem &3
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||
|
pos 1
|
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|
dimension 23
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||
|
uid 233,0
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||
|
)
|
||
|
*27 (MRCItem
|
||
|
litem &4
|
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|
pos 2
|
||
|
hidden 1
|
||
|
dimension 20
|
||
|
uid 235,0
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||
|
)
|
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|
*28 (MRCItem
|
||
|
litem &14
|
||
|
pos 0
|
||
|
dimension 20
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|
uid 2233,0
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||
|
)
|
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|
*29 (MRCItem
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|
litem &15
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|
pos 1
|
||
|
dimension 20
|
||
|
uid 2235,0
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||
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)
|
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|
*30 (MRCItem
|
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|
litem &16
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|
pos 2
|
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|
dimension 20
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|
uid 2237,0
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||
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)
|
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|
*31 (MRCItem
|
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|
litem &17
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pos 3
|
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dimension 20
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|
uid 2239,0
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)
|
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*32 (MRCItem
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|
litem &18
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pos 4
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dimension 20
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uid 2241,0
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)
|
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*33 (MRCItem
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|
litem &19
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pos 5
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dimension 20
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|
uid 2243,0
|
||
|
)
|
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|
*34 (MRCItem
|
||
|
litem &20
|
||
|
pos 6
|
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|
dimension 20
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|
uid 2245,0
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||
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)
|
||
|
*35 (MRCItem
|
||
|
litem &21
|
||
|
pos 7
|
||
|
dimension 20
|
||
|
uid 2247,0
|
||
|
)
|
||
|
*36 (MRCItem
|
||
|
litem &22
|
||
|
pos 8
|
||
|
dimension 20
|
||
|
uid 2249,0
|
||
|
)
|
||
|
]
|
||
|
)
|
||
|
sheetCol (SheetCol
|
||
|
propVa (MVa
|
||
|
cellColor "0,49152,49152"
|
||
|
fontColor "0,0,0"
|
||
|
font "Tahoma,10,0"
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||
|
textAngle 90
|
||
|
)
|
||
|
uid 229,0
|
||
|
optionalChildren [
|
||
|
*37 (MRCItem
|
||
|
litem &5
|
||
|
pos 0
|
||
|
dimension 20
|
||
|
uid 237,0
|
||
|
)
|
||
|
*38 (MRCItem
|
||
|
litem &7
|
||
|
pos 1
|
||
|
dimension 50
|
||
|
uid 241,0
|
||
|
)
|
||
|
*39 (MRCItem
|
||
|
litem &8
|
||
|
pos 2
|
||
|
dimension 100
|
||
|
uid 243,0
|
||
|
)
|
||
|
*40 (MRCItem
|
||
|
litem &9
|
||
|
pos 3
|
||
|
dimension 50
|
||
|
uid 245,0
|
||
|
)
|
||
|
*41 (MRCItem
|
||
|
litem &10
|
||
|
pos 4
|
||
|
dimension 100
|
||
|
uid 247,0
|
||
|
)
|
||
|
*42 (MRCItem
|
||
|
litem &11
|
||
|
pos 5
|
||
|
dimension 100
|
||
|
uid 249,0
|
||
|
)
|
||
|
*43 (MRCItem
|
||
|
litem &12
|
||
|
pos 6
|
||
|
dimension 50
|
||
|
uid 251,0
|
||
|
)
|
||
|
*44 (MRCItem
|
||
|
litem &13
|
||
|
pos 7
|
||
|
dimension 80
|
||
|
uid 253,0
|
||
|
)
|
||
|
]
|
||
|
)
|
||
|
fixedCol 4
|
||
|
fixedRow 2
|
||
|
name "Ports"
|
||
|
uid 227,0
|
||
|
vaOverrides [
|
||
|
]
|
||
|
)
|
||
|
]
|
||
|
)
|
||
|
uid 295,0
|
||
|
)
|
||
|
genericsCommonDM (CommonDM
|
||
|
ldm (LogicalDM
|
||
|
emptyRow *45 (LEmptyRow
|
||
|
)
|
||
|
uid 311,0
|
||
|
optionalChildren [
|
||
|
*46 (RefLabelRowHdr
|
||
|
)
|
||
|
*47 (TitleRowHdr
|
||
|
)
|
||
|
*48 (FilterRowHdr
|
||
|
)
|
||
|
*49 (RefLabelColHdr
|
||
|
tm "RefLabelColHdrMgr"
|
||
|
)
|
||
|
*50 (RowExpandColHdr
|
||
|
tm "RowExpandColHdrMgr"
|
||
|
)
|
||
|
*51 (GroupColHdr
|
||
|
tm "GroupColHdrMgr"
|
||
|
)
|
||
|
*52 (NameColHdr
|
||
|
tm "GenericNameColHdrMgr"
|
||
|
)
|
||
|
*53 (TypeColHdr
|
||
|
tm "GenericTypeColHdrMgr"
|
||
|
)
|
||
|
*54 (InitColHdr
|
||
|
tm "GenericValueColHdrMgr"
|
||
|
)
|
||
|
*55 (PragmaColHdr
|
||
|
tm "GenericPragmaColHdrMgr"
|
||
|
)
|
||
|
*56 (EolColHdr
|
||
|
tm "GenericEolColHdrMgr"
|
||
|
)
|
||
|
*57 (LogGeneric
|
||
|
generic (GiElement
|
||
|
name "ioNb"
|
||
|
type "positive"
|
||
|
value ""
|
||
|
)
|
||
|
uid 680,0
|
||
|
)
|
||
|
*58 (LogGeneric
|
||
|
generic (GiElement
|
||
|
name "signalBitNb"
|
||
|
type "positive"
|
||
|
value ""
|
||
|
)
|
||
|
uid 1770,0
|
||
|
)
|
||
|
*59 (LogGeneric
|
||
|
generic (GiElement
|
||
|
name "clockFrequency"
|
||
|
type "real"
|
||
|
value "60.0E6"
|
||
|
)
|
||
|
uid 2162,0
|
||
|
)
|
||
|
]
|
||
|
)
|
||
|
pdm (PhysicalDM
|
||
|
uid 312,0
|
||
|
optionalChildren [
|
||
|
*60 (Sheet
|
||
|
sheetRow (SheetRow
|
||
|
headerVa (MVa
|
||
|
cellColor "49152,49152,49152"
|
||
|
fontColor "0,0,0"
|
||
|
font "Tahoma,10,0"
|
||
|
)
|
||
|
cellVa (MVa
|
||
|
cellColor "65535,65535,65535"
|
||
|
fontColor "0,0,0"
|
||
|
font "Tahoma,10,0"
|
||
|
)
|
||
|
groupVa (MVa
|
||
|
cellColor "39936,56832,65280"
|
||
|
fontColor "0,0,0"
|
||
|
font "Tahoma,10,0"
|
||
|
)
|
||
|
emptyMRCItem *61 (MRCItem
|
||
|
litem &45
|
||
|
pos 3
|
||
|
dimension 20
|
||
|
)
|
||
|
uid 267,0
|
||
|
optionalChildren [
|
||
|
*62 (MRCItem
|
||
|
litem &46
|
||
|
pos 0
|
||
|
dimension 20
|
||
|
uid 270,0
|
||
|
)
|
||
|
*63 (MRCItem
|
||
|
litem &47
|
||
|
pos 1
|
||
|
dimension 23
|
||
|
uid 272,0
|
||
|
)
|
||
|
*64 (MRCItem
|
||
|
litem &48
|
||
|
pos 2
|
||
|
hidden 1
|
||
|
dimension 20
|
||
|
uid 274,0
|
||
|
)
|
||
|
*65 (MRCItem
|
||
|
litem &57
|
||
|
pos 0
|
||
|
dimension 20
|
||
|
uid 681,0
|
||
|
)
|
||
|
*66 (MRCItem
|
||
|
litem &58
|
||
|
pos 1
|
||
|
dimension 20
|
||
|
uid 1771,0
|
||
|
)
|
||
|
*67 (MRCItem
|
||
|
litem &59
|
||
|
pos 2
|
||
|
dimension 20
|
||
|
uid 2163,0
|
||
|
)
|
||
|
]
|
||
|
)
|
||
|
sheetCol (SheetCol
|
||
|
propVa (MVa
|
||
|
cellColor "0,49152,49152"
|
||
|
fontColor "0,0,0"
|
||
|
font "Tahoma,10,0"
|
||
|
textAngle 90
|
||
|
)
|
||
|
uid 268,0
|
||
|
optionalChildren [
|
||
|
*68 (MRCItem
|
||
|
litem &49
|
||
|
pos 0
|
||
|
dimension 20
|
||
|
uid 276,0
|
||
|
)
|
||
|
*69 (MRCItem
|
||
|
litem &51
|
||
|
pos 1
|
||
|
dimension 50
|
||
|
uid 280,0
|
||
|
)
|
||
|
*70 (MRCItem
|
||
|
litem &52
|
||
|
pos 2
|
||
|
dimension 100
|
||
|
uid 282,0
|
||
|
)
|
||
|
*71 (MRCItem
|
||
|
litem &53
|
||
|
pos 3
|
||
|
dimension 100
|
||
|
uid 284,0
|
||
|
)
|
||
|
*72 (MRCItem
|
||
|
litem &54
|
||
|
pos 4
|
||
|
dimension 50
|
||
|
uid 286,0
|
||
|
)
|
||
|
*73 (MRCItem
|
||
|
litem &55
|
||
|
pos 5
|
||
|
dimension 50
|
||
|
uid 288,0
|
||
|
)
|
||
|
*74 (MRCItem
|
||
|
litem &56
|
||
|
pos 6
|
||
|
dimension 80
|
||
|
uid 290,0
|
||
|
)
|
||
|
]
|
||
|
)
|
||
|
fixedCol 3
|
||
|
fixedRow 2
|
||
|
name "Ports"
|
||
|
uid 266,0
|
||
|
vaOverrides [
|
||
|
]
|
||
|
)
|
||
|
]
|
||
|
)
|
||
|
uid 310,0
|
||
|
type 1
|
||
|
)
|
||
|
VExpander (VariableExpander
|
||
|
vvMap [
|
||
|
(vvPair
|
||
|
variable " "
|
||
|
value " "
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "HDLDir"
|
||
|
value "C:\\dev\\sem-labs\\06-07-08-09-SystemOnChip\\Prefs\\..\\SystemOnChip_test\\hdl"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "HDSDir"
|
||
|
value "C:\\dev\\sem-labs\\06-07-08-09-SystemOnChip\\Prefs\\..\\SystemOnChip_test\\hds"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "SideDataDesignDir"
|
||
|
value "C:\\dev\\sem-labs\\06-07-08-09-SystemOnChip\\Prefs\\..\\SystemOnChip_test\\hds\\beamer@soc_tester\\interface.info"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "SideDataUserDir"
|
||
|
value "C:\\dev\\sem-labs\\06-07-08-09-SystemOnChip\\Prefs\\..\\SystemOnChip_test\\hds\\beamer@soc_tester\\interface.user"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "SourceDir"
|
||
|
value "C:\\dev\\sem-labs\\06-07-08-09-SystemOnChip\\Prefs\\..\\SystemOnChip_test\\hds"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "appl"
|
||
|
value "HDL Designer"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "arch_name"
|
||
|
value "interface"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "asm_file"
|
||
|
value "beamer.asm"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "concat_file"
|
||
|
value "concatenated"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "config"
|
||
|
value "%(unit)_%(view)_config"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "d"
|
||
|
value "C:\\dev\\sem-labs\\06-07-08-09-SystemOnChip\\Prefs\\..\\SystemOnChip_test\\hds\\beamer@soc_tester"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "d_logical"
|
||
|
value "C:\\dev\\sem-labs\\06-07-08-09-SystemOnChip\\Prefs\\..\\SystemOnChip_test\\hds\\beamerSoc_tester"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "date"
|
||
|
value "28.04.2023"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "day"
|
||
|
value "ven."
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "day_long"
|
||
|
value "vendredi"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "dd"
|
||
|
value "28"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "designName"
|
||
|
value "$DESIGN_NAME"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "entity_name"
|
||
|
value "beamerSoc_tester"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "ext"
|
||
|
value "<TBD>"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "f"
|
||
|
value "interface"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "f_logical"
|
||
|
value "interface"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "f_noext"
|
||
|
value "interface"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "graphical_source_author"
|
||
|
value "axel.amand"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "graphical_source_date"
|
||
|
value "28.04.2023"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "graphical_source_group"
|
||
|
value "UNKNOWN"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "graphical_source_host"
|
||
|
value "WE7860"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "graphical_source_time"
|
||
|
value "15:06:16"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "group"
|
||
|
value "UNKNOWN"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "host"
|
||
|
value "WE7860"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "language"
|
||
|
value "VHDL"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "library"
|
||
|
value "SystemOnChip_test"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "library_downstream_ModelSim"
|
||
|
value "D:\\Users\\ELN_labs\\VHDL_comp"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "library_downstream_ModelSimCompiler"
|
||
|
value "$SCRATCH_DIR/SystemOnChip_test"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "mm"
|
||
|
value "04"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "module_name"
|
||
|
value "beamerSoc_tester"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "month"
|
||
|
value "avr."
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "month_long"
|
||
|
value "avril"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "p"
|
||
|
value "C:\\dev\\sem-labs\\06-07-08-09-SystemOnChip\\Prefs\\..\\SystemOnChip_test\\hds\\beamer@soc_tester\\interface"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "p_logical"
|
||
|
value "C:\\dev\\sem-labs\\06-07-08-09-SystemOnChip\\Prefs\\..\\SystemOnChip_test\\hds\\beamerSoc_tester\\interface"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "package_name"
|
||
|
value "<Undefined Variable>"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "project_name"
|
||
|
value "hds"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "series"
|
||
|
value "HDL Designer Series"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "task_ADMS"
|
||
|
value "<TBD>"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "task_AsmPath"
|
||
|
value "$HEI_LIBS_DIR/NanoBlaze/hdl"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "task_DesignCompilerPath"
|
||
|
value "<TBD>"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "task_HDSPath"
|
||
|
value "$HDS_HOME"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "task_ISEBinPath"
|
||
|
value "$ISE_HOME"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "task_ISEPath"
|
||
|
value "$ISE_WORK_DIR"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "task_LeonardoPath"
|
||
|
value "<TBD>"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "task_ModelSimPath"
|
||
|
value "$MODELSIM_HOME/modeltech/bin"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "task_NC"
|
||
|
value "<TBD>"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "task_NC-SimPath"
|
||
|
value "<TBD>"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "task_PrecisionRTLPath"
|
||
|
value "<TBD>"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "task_QuestaSimPath"
|
||
|
value "<TBD>"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "task_VCSPath"
|
||
|
value "<TBD>"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "this_ext"
|
||
|
value "<TBD>"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "this_file"
|
||
|
value "interface"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "this_file_logical"
|
||
|
value "interface"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "time"
|
||
|
value "15:06:16"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "unit"
|
||
|
value "beamerSoc_tester"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "user"
|
||
|
value "axel.amand"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "version"
|
||
|
value "2019.2 (Build 5)"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "view"
|
||
|
value "interface"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "year"
|
||
|
value "2023"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "yy"
|
||
|
value "23"
|
||
|
)
|
||
|
]
|
||
|
)
|
||
|
LanguageMgr "Vhdl2008LangMgr"
|
||
|
uid 106,0
|
||
|
optionalChildren [
|
||
|
*75 (SymbolBody
|
||
|
uid 8,0
|
||
|
optionalChildren [
|
||
|
*76 (CptPort
|
||
|
uid 2187,0
|
||
|
ps "OnEdgeStrategy"
|
||
|
shape (Triangle
|
||
|
uid 2188,0
|
||
|
va (VaSet
|
||
|
vasetType 1
|
||
|
fg "0,65535,0"
|
||
|
)
|
||
|
xt "28625,5250,29375,6000"
|
||
|
)
|
||
|
tg (CPTG
|
||
|
uid 2189,0
|
||
|
ps "CptPortTextPlaceStrategy"
|
||
|
stg "RightVerticalLayoutStrategy"
|
||
|
f (Text
|
||
|
uid 2190,0
|
||
|
ro 270
|
||
|
va (VaSet
|
||
|
font "Verdana,12,0"
|
||
|
)
|
||
|
xt "28300,7000,29700,10800"
|
||
|
st "clock"
|
||
|
ju 2
|
||
|
blo "29500,7000"
|
||
|
tm "CptPortNameMgr"
|
||
|
)
|
||
|
)
|
||
|
dt (MLText
|
||
|
uid 2191,0
|
||
|
va (VaSet
|
||
|
font "Courier New,8,0"
|
||
|
)
|
||
|
xt "44000,6000,62500,6800"
|
||
|
st "clock : OUT std_ulogic ;
|
||
|
"
|
||
|
)
|
||
|
thePort (LogicalPort
|
||
|
m 1
|
||
|
decl (Decl
|
||
|
n "clock"
|
||
|
t "std_ulogic"
|
||
|
o 3
|
||
|
suid 2184,0
|
||
|
)
|
||
|
)
|
||
|
)
|
||
|
*77 (CptPort
|
||
|
uid 2192,0
|
||
|
ps "OnEdgeStrategy"
|
||
|
shape (Diamond
|
||
|
uid 2193,0
|
||
|
va (VaSet
|
||
|
vasetType 1
|
||
|
fg "0,65535,0"
|
||
|
)
|
||
|
xt "84625,5250,85375,6000"
|
||
|
)
|
||
|
tg (CPTG
|
||
|
uid 2194,0
|
||
|
ps "CptPortTextPlaceStrategy"
|
||
|
stg "VerticalLayoutStrategy"
|
||
|
f (Text
|
||
|
uid 2195,0
|
||
|
va (VaSet
|
||
|
font "Verdana,12,0"
|
||
|
)
|
||
|
xt "86000,6000,87900,7400"
|
||
|
st "io"
|
||
|
blo "86000,7200"
|
||
|
tm "CptPortNameMgr"
|
||
|
)
|
||
|
)
|
||
|
dt (MLText
|
||
|
uid 2196,0
|
||
|
va (VaSet
|
||
|
font "Courier New,8,0"
|
||
|
)
|
||
|
xt "44000,8400,73500,9200"
|
||
|
st "io : INOUT std_logic_vector (ioNb-1 DOWNTO 0)
|
||
|
"
|
||
|
)
|
||
|
thePort (LogicalPort
|
||
|
m 2
|
||
|
decl (Decl
|
||
|
n "io"
|
||
|
t "std_logic_vector"
|
||
|
b "(ioNb-1 DOWNTO 0)"
|
||
|
o 4
|
||
|
suid 2185,0
|
||
|
)
|
||
|
)
|
||
|
)
|
||
|
*78 (CptPort
|
||
|
uid 2197,0
|
||
|
ps "OnEdgeStrategy"
|
||
|
shape (Triangle
|
||
|
uid 2198,0
|
||
|
ro 180
|
||
|
va (VaSet
|
||
|
vasetType 1
|
||
|
fg "0,65535,0"
|
||
|
)
|
||
|
xt "88625,5250,89375,6000"
|
||
|
)
|
||
|
tg (CPTG
|
||
|
uid 2199,0
|
||
|
ps "CptPortTextPlaceStrategy"
|
||
|
stg "RightVerticalLayoutStrategy"
|
||
|
f (Text
|
||
|
uid 2200,0
|
||
|
ro 270
|
||
|
va (VaSet
|
||
|
font "Verdana,12,0"
|
||
|
)
|
||
|
xt "88300,7000,89700,16800"
|
||
|
st "lowpassOutY"
|
||
|
ju 2
|
||
|
blo "89500,7000"
|
||
|
tm "CptPortNameMgr"
|
||
|
)
|
||
|
)
|
||
|
dt (MLText
|
||
|
uid 2201,0
|
||
|
va (VaSet
|
||
|
font "Courier New,8,0"
|
||
|
)
|
||
|
xt "44000,2800,74000,3600"
|
||
|
st "lowpassOutY : IN unsigned (signalBitNb-1 DOWNTO 0) ;
|
||
|
"
|
||
|
)
|
||
|
thePort (LogicalPort
|
||
|
decl (Decl
|
||
|
n "lowpassOutY"
|
||
|
t "unsigned"
|
||
|
b "(signalBitNb-1 DOWNTO 0)"
|
||
|
o 9
|
||
|
suid 2186,0
|
||
|
)
|
||
|
)
|
||
|
)
|
||
|
*79 (CptPort
|
||
|
uid 2202,0
|
||
|
ps "OnEdgeStrategy"
|
||
|
shape (Triangle
|
||
|
uid 2203,0
|
||
|
ro 180
|
||
|
va (VaSet
|
||
|
vasetType 1
|
||
|
fg "0,65535,0"
|
||
|
)
|
||
|
xt "56625,5250,57375,6000"
|
||
|
)
|
||
|
tg (CPTG
|
||
|
uid 2204,0
|
||
|
ps "CptPortTextPlaceStrategy"
|
||
|
stg "RightVerticalLayoutStrategy"
|
||
|
f (Text
|
||
|
uid 2205,0
|
||
|
ro 270
|
||
|
va (VaSet
|
||
|
font "Verdana,12,0"
|
||
|
)
|
||
|
xt "56300,7000,57700,10700"
|
||
|
st "outX"
|
||
|
ju 2
|
||
|
blo "57500,7000"
|
||
|
tm "CptPortNameMgr"
|
||
|
)
|
||
|
)
|
||
|
dt (MLText
|
||
|
uid 2206,0
|
||
|
va (VaSet
|
||
|
font "Courier New,8,0"
|
||
|
)
|
||
|
xt "44000,3600,62500,4400"
|
||
|
st "outX : IN std_ulogic ;
|
||
|
"
|
||
|
)
|
||
|
thePort (LogicalPort
|
||
|
decl (Decl
|
||
|
n "outX"
|
||
|
t "std_ulogic"
|
||
|
o 10
|
||
|
suid 2187,0
|
||
|
)
|
||
|
)
|
||
|
)
|
||
|
*80 (CptPort
|
||
|
uid 2207,0
|
||
|
ps "OnEdgeStrategy"
|
||
|
shape (Triangle
|
||
|
uid 2208,0
|
||
|
ro 180
|
||
|
va (VaSet
|
||
|
vasetType 1
|
||
|
fg "0,65535,0"
|
||
|
)
|
||
|
xt "54625,5250,55375,6000"
|
||
|
)
|
||
|
tg (CPTG
|
||
|
uid 2209,0
|
||
|
ps "CptPortTextPlaceStrategy"
|
||
|
stg "RightVerticalLayoutStrategy"
|
||
|
f (Text
|
||
|
uid 2210,0
|
||
|
ro 270
|
||
|
va (VaSet
|
||
|
font "Verdana,12,0"
|
||
|
)
|
||
|
xt "54300,7000,55700,10600"
|
||
|
st "outY"
|
||
|
ju 2
|
||
|
blo "55500,7000"
|
||
|
tm "CptPortNameMgr"
|
||
|
)
|
||
|
)
|
||
|
dt (MLText
|
||
|
uid 2211,0
|
||
|
va (VaSet
|
||
|
font "Courier New,8,0"
|
||
|
)
|
||
|
xt "44000,4400,62500,5200"
|
||
|
st "outY : IN std_ulogic ;
|
||
|
"
|
||
|
)
|
||
|
thePort (LogicalPort
|
||
|
decl (Decl
|
||
|
n "outY"
|
||
|
t "std_ulogic"
|
||
|
o 11
|
||
|
suid 2188,0
|
||
|
)
|
||
|
)
|
||
|
)
|
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ju 2
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blo "23500,7000"
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tm "CptPortNameMgr"
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dt (MLText
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thePort (LogicalPort
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suid 2192,0
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