1505 lines
18 KiB
Plaintext
1505 lines
18 KiB
Plaintext
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DocumentHdrVersion "1.1"
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Header (DocumentHdr
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version 2
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dialect 11
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(DmPackageRef
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library "ieee"
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unitName "std_logic_1164"
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(DmPackageRef
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library "ieee"
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libraryRefs [
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version "26.1"
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appVersion "2018.1 (Build 12)"
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port (LogicalPort
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decl (Decl
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n "dataIn"
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pdm (PhysicalDM
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litem &18
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litem &20
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dimension 20
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ldm (LogicalDM
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*47 (RefLabelColHdr
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tm "RefLabelColHdrMgr"
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*48 (RowExpandColHdr
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tm "RowExpandColHdrMgr"
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*49 (GroupColHdr
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tm "GroupColHdrMgr"
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tm "GenericTypeColHdrMgr"
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*52 (InitColHdr
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tm "GenericValueColHdrMgr"
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VExpander (VariableExpander
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vvMap [
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(vvPair
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variable " "
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value " "
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)
|
||
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(vvPair
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variable "HDLDir"
|
||
|
value "/home/francois/Documents/HEVs/Kart/eln_kart/04-Controller/../Libs/Memory_test/hdl"
|
||
|
)
|
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(vvPair
|
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variable "HDSDir"
|
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value "/home/francois/Documents/HEVs/Kart/eln_kart/04-Controller/../Libs/Memory_test/hds"
|
||
|
)
|
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(vvPair
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|
variable "SideDataDesignDir"
|
||
|
value "/home/francois/Documents/HEVs/Kart/eln_kart/04-Controller/../Libs/Memory_test/hds/fifo_tester/interface.info"
|
||
|
)
|
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|
(vvPair
|
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variable "SideDataUserDir"
|
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|
value "/home/francois/Documents/HEVs/Kart/eln_kart/04-Controller/../Libs/Memory_test/hds/fifo_tester/interface.user"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "SourceDir"
|
||
|
value "/home/francois/Documents/HEVs/Kart/eln_kart/04-Controller/../Libs/Memory_test/hds"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "appl"
|
||
|
value "HDL Designer"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "arch_name"
|
||
|
value "interface"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "concat_file"
|
||
|
value "concatenated"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "config"
|
||
|
value "%(unit)_%(view)_config"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "d"
|
||
|
value "/home/francois/Documents/HEVs/Kart/eln_kart/04-Controller/../Libs/Memory_test/hds/fifo_tester"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "d_logical"
|
||
|
value "/home/francois/Documents/HEVs/Kart/eln_kart/04-Controller/../Libs/Memory_test/hds/fifo_tester"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "date"
|
||
|
value "08/28/19"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "day"
|
||
|
value "Wed"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "day_long"
|
||
|
value "Wednesday"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "dd"
|
||
|
value "28"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "designName"
|
||
|
value "$DESIGN_NAME"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "entity_name"
|
||
|
value "fifo_tester"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "ext"
|
||
|
value "<TBD>"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "f"
|
||
|
value "interface"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "f_logical"
|
||
|
value "interface"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "f_noext"
|
||
|
value "interface"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "graphical_source_author"
|
||
|
value "francois"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "graphical_source_date"
|
||
|
value "08/28/19"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "graphical_source_group"
|
||
|
value "francois"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "graphical_source_host"
|
||
|
value "Aphelia"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "graphical_source_time"
|
||
|
value "13:45:28"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "group"
|
||
|
value "francois"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "host"
|
||
|
value "Aphelia"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "language"
|
||
|
value "VHDL"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "library"
|
||
|
value "Memory_test"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "library_downstream_ModelSimCompiler"
|
||
|
value "$SCRATCH_DIR/Libs/Memory_test/work"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "mm"
|
||
|
value "08"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "module_name"
|
||
|
value "fifo_tester"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "month"
|
||
|
value "Aug"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "month_long"
|
||
|
value "August"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "p"
|
||
|
value "/home/francois/Documents/HEVs/Kart/eln_kart/04-Controller/../Libs/Memory_test/hds/fifo_tester/interface"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "p_logical"
|
||
|
value "/home/francois/Documents/HEVs/Kart/eln_kart/04-Controller/../Libs/Memory_test/hds/fifo_tester/interface"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "package_name"
|
||
|
value "<Undefined Variable>"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "project_name"
|
||
|
value "hds"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "series"
|
||
|
value "HDL Designer Series"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "task_ActelPath"
|
||
|
value "$ACTEL_HOME"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "task_ActelProjectPath"
|
||
|
value "$SCRATCH_DIR\\$DESIGN_NAME\\$ACTEL_WORK_DIR"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "task_HDSPath"
|
||
|
value "$HDS_HOME"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "task_ModelSimPath"
|
||
|
value "$MODELSIM_HOME\\win32"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "this_ext"
|
||
|
value "<TBD>"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "this_file"
|
||
|
value "interface"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "this_file_logical"
|
||
|
value "interface"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "time"
|
||
|
value "13:45:28"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "unit"
|
||
|
value "fifo_tester"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "user"
|
||
|
value "francois"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "version"
|
||
|
value "2018.1 (Build 12)"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "view"
|
||
|
value "interface"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "year"
|
||
|
value "2019"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "yy"
|
||
|
value "19"
|
||
|
)
|
||
|
]
|
||
|
)
|
||
|
LanguageMgr "Vhdl2008LangMgr"
|
||
|
uid 75,0
|
||
|
optionalChildren [
|
||
|
*71 (SymbolBody
|
||
|
uid 8,0
|
||
|
optionalChildren [
|
||
|
*72 (CptPort
|
||
|
uid 363,0
|
||
|
ps "OnEdgeStrategy"
|
||
|
shape (Triangle
|
||
|
uid 364,0
|
||
|
va (VaSet
|
||
|
vasetType 1
|
||
|
fg "0,65535,0"
|
||
|
)
|
||
|
xt "30625,5250,31375,6000"
|
||
|
)
|
||
|
tg (CPTG
|
||
|
uid 365,0
|
||
|
ps "CptPortTextPlaceStrategy"
|
||
|
stg "RightVerticalLayoutStrategy"
|
||
|
f (Text
|
||
|
uid 366,0
|
||
|
ro 270
|
||
|
va (VaSet
|
||
|
font "courier,8,0"
|
||
|
)
|
||
|
xt "30550,7000,31450,9500"
|
||
|
st "clock"
|
||
|
ju 2
|
||
|
blo "31250,7000"
|
||
|
tm "CptPortNameMgr"
|
||
|
)
|
||
|
)
|
||
|
dt (MLText
|
||
|
uid 367,0
|
||
|
va (VaSet
|
||
|
font "courier,8,0"
|
||
|
)
|
||
|
xt "44000,4700,59500,5600"
|
||
|
st "clock : OUT std_ulogic ;
|
||
|
"
|
||
|
)
|
||
|
thePort (LogicalPort
|
||
|
m 1
|
||
|
decl (Decl
|
||
|
n "clock"
|
||
|
t "std_ulogic"
|
||
|
o 1
|
||
|
suid 25,0
|
||
|
)
|
||
|
)
|
||
|
)
|
||
|
*73 (CptPort
|
||
|
uid 368,0
|
||
|
ps "OnEdgeStrategy"
|
||
|
shape (Triangle
|
||
|
uid 369,0
|
||
|
va (VaSet
|
||
|
vasetType 1
|
||
|
fg "0,65535,0"
|
||
|
)
|
||
|
xt "22625,5250,23375,6000"
|
||
|
)
|
||
|
tg (CPTG
|
||
|
uid 370,0
|
||
|
ps "CptPortTextPlaceStrategy"
|
||
|
stg "RightVerticalLayoutStrategy"
|
||
|
f (Text
|
||
|
uid 371,0
|
||
|
ro 270
|
||
|
va (VaSet
|
||
|
font "courier,8,0"
|
||
|
)
|
||
|
xt "22550,7000,23450,10000"
|
||
|
st "dataIn"
|
||
|
ju 2
|
||
|
blo "23250,7000"
|
||
|
tm "CptPortNameMgr"
|
||
|
)
|
||
|
)
|
||
|
dt (MLText
|
||
|
uid 372,0
|
||
|
va (VaSet
|
||
|
font "courier,8,0"
|
||
|
)
|
||
|
xt "44000,5600,74000,6500"
|
||
|
st "dataIn : OUT std_ulogic_vector (dataBitNb-1 DOWNTO 0) ;
|
||
|
"
|
||
|
)
|
||
|
thePort (LogicalPort
|
||
|
m 1
|
||
|
decl (Decl
|
||
|
n "dataIn"
|
||
|
t "std_ulogic_vector"
|
||
|
b "(dataBitNb-1 DOWNTO 0)"
|
||
|
o 2
|
||
|
suid 26,0
|
||
|
)
|
||
|
)
|
||
|
)
|
||
|
*74 (CptPort
|
||
|
uid 373,0
|
||
|
ps "OnEdgeStrategy"
|
||
|
shape (Triangle
|
||
|
uid 374,0
|
||
|
ro 180
|
||
|
va (VaSet
|
||
|
vasetType 1
|
||
|
fg "0,65535,0"
|
||
|
)
|
||
|
xt "58625,5250,59375,6000"
|
||
|
)
|
||
|
tg (CPTG
|
||
|
uid 375,0
|
||
|
ps "CptPortTextPlaceStrategy"
|
||
|
stg "RightVerticalLayoutStrategy"
|
||
|
f (Text
|
||
|
uid 376,0
|
||
|
ro 270
|
||
|
va (VaSet
|
||
|
font "courier,8,0"
|
||
|
)
|
||
|
xt "58550,7000,59450,10500"
|
||
|
st "dataOut"
|
||
|
ju 2
|
||
|
blo "59250,7000"
|
||
|
tm "CptPortNameMgr"
|
||
|
)
|
||
|
)
|
||
|
dt (MLText
|
||
|
uid 377,0
|
||
|
va (VaSet
|
||
|
font "courier,8,0"
|
||
|
)
|
||
|
xt "44000,2000,74000,2900"
|
||
|
st "dataOut : IN std_ulogic_vector (dataBitNb-1 DOWNTO 0) ;
|
||
|
"
|
||
|
)
|
||
|
thePort (LogicalPort
|
||
|
decl (Decl
|
||
|
n "dataOut"
|
||
|
t "std_ulogic_vector"
|
||
|
b "(dataBitNb-1 DOWNTO 0)"
|
||
|
o 3
|
||
|
suid 27,0
|
||
|
)
|
||
|
)
|
||
|
)
|
||
|
*75 (CptPort
|
||
|
uid 378,0
|
||
|
ps "OnEdgeStrategy"
|
||
|
shape (Triangle
|
||
|
uid 379,0
|
||
|
ro 180
|
||
|
va (VaSet
|
||
|
vasetType 1
|
||
|
fg "0,65535,0"
|
||
|
)
|
||
|
xt "56625,5250,57375,6000"
|
||
|
)
|
||
|
tg (CPTG
|
||
|
uid 380,0
|
||
|
ps "CptPortTextPlaceStrategy"
|
||
|
stg "RightVerticalLayoutStrategy"
|
||
|
f (Text
|
||
|
uid 381,0
|
||
|
ro 270
|
||
|
va (VaSet
|
||
|
font "courier,8,0"
|
||
|
)
|
||
|
xt "56550,7000,57450,9500"
|
||
|
st "empty"
|
||
|
ju 2
|
||
|
blo "57250,7000"
|
||
|
tm "CptPortNameMgr"
|
||
|
)
|
||
|
)
|
||
|
dt (MLText
|
||
|
uid 382,0
|
||
|
va (VaSet
|
||
|
font "courier,8,0"
|
||
|
)
|
||
|
xt "44000,2900,59500,3800"
|
||
|
st "empty : IN std_ulogic ;
|
||
|
"
|
||
|
)
|
||
|
thePort (LogicalPort
|
||
|
decl (Decl
|
||
|
n "empty"
|
||
|
t "std_ulogic"
|
||
|
o 4
|
||
|
suid 28,0
|
||
|
)
|
||
|
)
|
||
|
)
|
||
|
*76 (CptPort
|
||
|
uid 383,0
|
||
|
ps "OnEdgeStrategy"
|
||
|
shape (Triangle
|
||
|
uid 384,0
|
||
|
ro 180
|
||
|
va (VaSet
|
||
|
vasetType 1
|
||
|
fg "0,65535,0"
|
||
|
)
|
||
|
xt "24625,5250,25375,6000"
|
||
|
)
|
||
|
tg (CPTG
|
||
|
uid 385,0
|
||
|
ps "CptPortTextPlaceStrategy"
|
||
|
stg "RightVerticalLayoutStrategy"
|
||
|
f (Text
|
||
|
uid 386,0
|
||
|
ro 270
|
||
|
va (VaSet
|
||
|
font "courier,8,0"
|
||
|
)
|
||
|
xt "24550,7000,25450,9000"
|
||
|
st "full"
|
||
|
ju 2
|
||
|
blo "25250,7000"
|
||
|
tm "CptPortNameMgr"
|
||
|
)
|
||
|
)
|
||
|
dt (MLText
|
||
|
uid 387,0
|
||
|
va (VaSet
|
||
|
font "courier,8,0"
|
||
|
)
|
||
|
xt "44000,3800,59500,4700"
|
||
|
st "full : IN std_ulogic ;
|
||
|
"
|
||
|
)
|
||
|
thePort (LogicalPort
|
||
|
decl (Decl
|
||
|
n "full"
|
||
|
t "std_ulogic"
|
||
|
o 5
|
||
|
suid 29,0
|
||
|
)
|
||
|
)
|
||
|
)
|
||
|
*77 (CptPort
|
||
|
uid 388,0
|
||
|
ps "OnEdgeStrategy"
|
||
|
shape (Triangle
|
||
|
uid 389,0
|
||
|
va (VaSet
|
||
|
vasetType 1
|
||
|
fg "0,65535,0"
|
||
|
)
|
||
|
xt "54625,5250,55375,6000"
|
||
|
)
|
||
|
tg (CPTG
|
||
|
uid 390,0
|
||
|
ps "CptPortTextPlaceStrategy"
|
||
|
stg "RightVerticalLayoutStrategy"
|
||
|
f (Text
|
||
|
uid 391,0
|
||
|
ro 270
|
||
|
va (VaSet
|
||
|
font "courier,8,0"
|
||
|
)
|
||
|
xt "54550,7000,55450,9000"
|
||
|
st "read"
|
||
|
ju 2
|
||
|
blo "55250,7000"
|
||
|
tm "CptPortNameMgr"
|
||
|
)
|
||
|
)
|
||
|
dt (MLText
|
||
|
uid 392,0
|
||
|
va (VaSet
|
||
|
font "courier,8,0"
|
||
|
)
|
||
|
xt "44000,6500,59500,7400"
|
||
|
st "read : OUT std_ulogic ;
|
||
|
"
|
||
|
)
|
||
|
thePort (LogicalPort
|
||
|
m 1
|
||
|
decl (Decl
|
||
|
n "read"
|
||
|
t "std_ulogic"
|
||
|
o 6
|
||
|
suid 30,0
|
||
|
)
|
||
|
)
|
||
|
)
|
||
|
*78 (CptPort
|
||
|
uid 393,0
|
||
|
ps "OnEdgeStrategy"
|
||
|
shape (Triangle
|
||
|
uid 394,0
|
||
|
va (VaSet
|
||
|
vasetType 1
|
||
|
fg "0,65535,0"
|
||
|
)
|
||
|
xt "32625,5250,33375,6000"
|
||
|
)
|
||
|
tg (CPTG
|
||
|
uid 395,0
|
||
|
ps "CptPortTextPlaceStrategy"
|
||
|
stg "RightVerticalLayoutStrategy"
|
||
|
f (Text
|
||
|
uid 396,0
|
||
|
ro 270
|
||
|
va (VaSet
|
||
|
font "courier,8,0"
|
||
|
)
|
||
|
xt "32550,7000,33450,9500"
|
||
|
st "reset"
|
||
|
ju 2
|
||
|
blo "33250,7000"
|
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|
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decl (Decl
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thePort (LogicalPort
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decl (Decl
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uid 1,0
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uid 6,0
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externalText (MLText
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tm "SyDeclarativeTextMgr"
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internalText (MLText
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uid 7,0
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tm "SyDeclarativeTextMgr"
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