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implement uvwxy way

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This commit is contained in:
Rémi Heredero 2024-03-13 14:21:54 +01:00
parent f086447f28
commit 1867661418
4 changed files with 23 additions and 35 deletions
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2
02-SplineInterpolator/Prefs/hds_user/v2019.2/hds_user_prefs.bak
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@ -1280,8 +1280,8 @@ projectPaths [
"C:\\work\\repo\\edu\\sem\\labo\\solution\\sem_labs\\02-SplineInterpolator\\Prefs\\hds.hdp" "C:\\work\\repo\\edu\\sem\\labo\\solution\\sem_labs\\02-SplineInterpolator\\Prefs\\hds.hdp"
"C:\\work\\edu\\sem\\labo\\sem_labs\\02-SplineInterpolator\\Prefs\\hds.hdp" "C:\\work\\edu\\sem\\labo\\sem_labs\\02-SplineInterpolator\\Prefs\\hds.hdp"
"C:\\dev\\sem-labs\\02-SplineInterpolator\\Prefs\\hds.hdp" "C:\\dev\\sem-labs\\02-SplineInterpolator\\Prefs\\hds.hdp"
"C:\\Users\\remi.heredero\\GIT\\2024-sem-labs-herederoremi\\02-SplineInterpolator\\Prefs\\hds.hdp"
"C:\\Users\\uadmin\\GIT\\2024-sem-labs-herederoremi\\02-SplineInterpolator\\Prefs\\hds.hdp" "C:\\Users\\uadmin\\GIT\\2024-sem-labs-herederoremi\\02-SplineInterpolator\\Prefs\\hds.hdp"
"C:\\Users\\remi.heredero\\GIT\\2024-sem-labs-herederoremi\\02-SplineInterpolator\\Prefs\\hds.hdp"
] ]
libMappingsRootDir "" libMappingsRootDir ""
teamLibMappingsRootDir "" teamLibMappingsRootDir ""

56
02-SplineInterpolator/SplineInterpolator/hdl/interpolatorCalculatePolynom_studentVersion.vhd
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@ -1,54 +1,42 @@
ARCHITECTURE studentVersion OF interpolatorCalculatePolynom IS ARCHITECTURE studentVersion OF interpolatorCalculatePolynom IS
subtype sample_type is signed(coeffBitNb-1+oversamplingBitNb DOWNTO 0); subtype st is signed(coeffBitNb-1+oversamplingBitNb+8 DOWNTO 0);
type order0 is array (0 to 0) of sample_type; signal x: st;
type order1 is array (0 to 1) of sample_type; signal u: st;
type order2 is array (0 to 2) of sample_type; signal v: st;
type order3 is array (0 to 3) of sample_type; signal w: st;
signal cA: order3; signal y: st;
signal cB: order2;
signal cC: order1;
signal cD: order0;
BEGIN BEGIN
process(clock, reset) begin process(clock, reset) begin
if reset = '1' then if reset = '1' then
cA <= (others => (others => '0')); x <= (others => '0');
cB <= (others => (others => '0')); u <= (others => '0');
cC <= (others => (others => '0')); v <= (others => '0');
cD <= (others => (others => '0')); w <= (others => '0');
y <= (others => '0');
elsif rising_edge(clock) then elsif rising_edge(clock) then
if restartPolynom = '1' then if restartPolynom = '1' then
cA(3) <= (others => '0');
cA(2) <= (others => '0');
cA(1) <= (others => '0');
cA(0) <= resize(a,sample_type'high+1);
cB(2) <= (others => '0');
cB(1) <= (others => '0');
cB(0) <= resize(b,sample_type'high+1);
cC(1) <= (others => '0');
cC(0) <= resize(c,sample_type'high+1);
cD(0) <= resize(d,sample_type'high+1); x <= resize(d, st'high+1) sll (oversamplingBitNb * 3 + 1);
u <= resize(a, st'high+1) + (resize(b, st'high+1) sll oversamplingBitNb) + (resize(c, st'high+1) sll (oversamplingBitNb*2));
v <= resize(6*a, v'length) + (resize(b, st'high+1) sll (oversamplingBitNb + 1));
w <= resize(6*a, w'length);
y <= resize(d, st'high+1);
else else
cC(1) <= resize(c,sample_type'high+1) + cC(1); x <= x + u;
u <= u + v;
cB(2) <= cB(2) + resize(2*cB(1),sample_type'high+1) + b; v <= v + w;
cB(1) <= resize(b,sample_type'high+1) + cB(1); y <= x srl (oversamplingBitNb * 3 + 1);
cA(3) <= cA(3) + resize(3*cA(2),sample_type'high+1) + resize(3*cA(1),sample_type'high+1) + a;
cA(2) <= cA(2) + resize(2*cA(1),sample_type'high+1) + a;
cA(1) <= resize(A,sample_type'high+1) + cA(1);
end if; end if;
end if; end if;
end process; end process;
sampleOut <= resize(cA(3)+cB(2)+cC(1)+cD(0),signalBitNb); sampleOut <= resize(y,signalBitNb);
END ARCHITECTURE studentVersion; END ARCHITECTURE studentVersion;

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02-SplineInterpolator/SplineInterpolator/hds/.cache.dat
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02-SplineInterpolator/SplineInterpolator_test/hds/.cache.dat
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