Klagarge/SEm-Labos
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add shift + buffer

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This commit is contained in:
Rémi Heredero 2024-03-13 13:26:53 +01:00
parent f086447f28
commit 29cc4f7620
1 changed files with 16 additions and 6 deletions
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22
02-SplineInterpolator/SplineInterpolator/hdl/interpolatorCalculatePolynom_studentVersion.vhd
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@ -1,6 +1,6 @@
ARCHITECTURE studentVersion OF interpolatorCalculatePolynom IS ARCHITECTURE studentVersion OF interpolatorCalculatePolynom IS
subtype sample_type is signed(coeffBitNb-1+oversamplingBitNb DOWNTO 0); subtype sample_type is signed(coeffBitNb-1+oversamplingBitNb+10 DOWNTO 0);
type order0 is array (0 to 0) of sample_type; type order0 is array (0 to 0) of sample_type;
type order1 is array (0 to 1) of sample_type; type order1 is array (0 to 1) of sample_type;
type order2 is array (0 to 2) of sample_type; type order2 is array (0 to 2) of sample_type;
@ -9,6 +9,7 @@ signal cA: order3;
signal cB: order2; signal cB: order2;
signal cC: order1; signal cC: order1;
signal cD: order0; signal cD: order0;
signal bufferSine: sample_type;
BEGIN BEGIN
@ -18,6 +19,7 @@ BEGIN
cB <= (others => (others => '0')); cB <= (others => (others => '0'));
cC <= (others => (others => '0')); cC <= (others => (others => '0'));
cD <= (others => (others => '0')); cD <= (others => (others => '0'));
bufferSine <= (others => '0');
elsif rising_edge(clock) then elsif rising_edge(clock) then
if restartPolynom = '1' then if restartPolynom = '1' then
@ -37,18 +39,26 @@ BEGIN
else else
cC(1) <= resize(c,sample_type'high+1) + cC(1); cC(1) <= cC(0) + cC(1);
cB(2) <= cB(2) + resize(2*cB(1),sample_type'high+1) + b; cB(2) <= cB(2) + resize(2*cB(1),sample_type'high+1) + cB(0);
cB(1) <= resize(b,sample_type'high+1) + cB(1); cB(1) <= resize(b,sample_type'high+1) + cB(1);
cA(3) <= cA(3) + resize(3*cA(2),sample_type'high+1) + resize(3*cA(1),sample_type'high+1) + a; cA(3) <= cA(3) + resize(3*cA(2),sample_type'high+1) + resize(3*cA(1),sample_type'high+1) + cA(0);
cA(2) <= cA(2) + resize(2*cA(1),sample_type'high+1) + a; cA(2) <= cA(2) + resize(2*cA(1),sample_type'high+1) + cA(0);
cA(1) <= resize(A,sample_type'high+1) + cA(1); cA(1) <= resize(A,sample_type'high+1) + cA(1);
end if; end if;
bufferSine <= bufferSine + shift_right(cA(3)+cB(2)+cC(1)+cD(0),0);
end if; end if;
end process; end process;
sampleOut <= resize(cA(3)+cB(2)+cC(1)+cD(0),signalBitNb); process(cA, cB, cC, cD) begin
--bufferSine <= bufferSine + cA(3)+cB(2)+cC(1)+cD(0);
end process;
--sampleOut <= resize(shift_right(cA(3)+cB(2)+cC(1)+cD(0),oversamplingBitNb),signalBitNb);
sampleOut <= resize(bufferSine,signalBitNb);
END ARCHITECTURE studentVersion; END ARCHITECTURE studentVersion;