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finish lab2

This commit is contained in:
Rémi Heredero 2024-03-15 14:03:21 +01:00
parent 1867661418
commit 6780852b7f
2 changed files with 18 additions and 9 deletions

View File

@ -5,7 +5,6 @@ signal x: st;
signal u: st;
signal v: st;
signal w: st;
signal y: st;
BEGIN
@ -15,28 +14,25 @@ BEGIN
u <= (others => '0');
v <= (others => '0');
w <= (others => '0');
y <= (others => '0');
elsif rising_edge(clock) then
if restartPolynom = '1' then
x <= resize(d, st'high+1) sll (oversamplingBitNb * 3 + 1);
u <= resize(a, st'high+1) + (resize(b, st'high+1) sll oversamplingBitNb) + (resize(c, st'high+1) sll (oversamplingBitNb*2));
v <= resize(6*a, v'length) + (resize(b, st'high+1) sll (oversamplingBitNb + 1));
x <= resize(d, st'high+1) sla (oversamplingBitNb * 3 + 1);
u <= resize(a, st'high+1) + (resize(b, st'high+1) sla oversamplingBitNb) + (resize(c, st'high+1) sla (oversamplingBitNb*2));
v <= resize(6*a, v'length) + (resize(b, st'high+1) sla (oversamplingBitNb + 1));
w <= resize(6*a, w'length);
y <= resize(d, st'high+1);
else
x <= x + u;
u <= u + v;
v <= v + w;
y <= x srl (oversamplingBitNb * 3 + 1);
end if;
end if;
end process;
sampleOut <= resize(y,signalBitNb);
sampleOut <= resize(x sra (oversamplingBitNb * 3 + 1),signalBitNb);
END ARCHITECTURE studentVersion;

View File

@ -1,4 +1,17 @@
ARCHITECTURE studentVersion OF offsetToUnsigned IS
signal mySignal : unsigned(BitNb-1 downto 0);
signal const : unsigned(BitNb-1 downto 0) := (others => '1');
BEGIN
unsignedOut <= (others => '0');
process(signedIn) begin
if signedIn(signedIn'high) then
mySignal <= unsigned(signedIn) - (const srl 1);
else
mySignal <= unsigned(signedIn) + (const srl 1);
end if;
end process;
unsignedOut <= mySignal;
END ARCHITECTURE studentVersion;