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add resize + tabel

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This commit is contained in:
Rémi Heredero
2024-03-05 11:48:52 +01:00
parent 73dd7da0db
commit 681c567da7
46 changed files with 14970 additions and 524 deletions
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6
01-WaveformGenerator/WaveformGenerator_test/hdl/waveformgen_tb_struct.vhg
View File

@ -3,7 +3,7 @@
--
-- Created:
-- by - remi.heredero.UNKNOWN (WE2330808)
-- at - 14:26:40 01.03.2024
-- at - 15:12:57 01.03.2024
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5)
--
@ -20,8 +20,8 @@ ARCHITECTURE struct OF waveformGen_tb IS
constant bitNb: positive := 16;
constant signalBitNb: positive := 16;
constant phaseBitNb: positive := 16;
constant clockFrequency: real := 60.0E6;
--constant clockFrequency: real := 66.0E6;
--constant clockFrequency: real := 60.0E6;
constant clockFrequency: real := 66.0E6;
-- Internal signal declarations
SIGNAL clock : std_ulogic;

BIN
01-WaveformGenerator/WaveformGenerator_test/hds/.cache.dat Normal file
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Binary file not shown.

9
01-WaveformGenerator/WaveformGenerator_test/hds/waveform@gen_tb/struct.bd
View File

@ -173,7 +173,7 @@ value "WE2330808"
)
(vvPair
variable "graphical_source_time"
value "14:26:40"
value "15:12:57"
)
(vvPair
variable "group"
@ -301,7 +301,7 @@ value "struct"
)
(vvPair
variable "time"
value "14:26:40"
value "15:12:57"
)
(vvPair
variable "unit"
@ -2743,8 +2743,9 @@ xt "2000,7700,26900,13700"
st "constant bitNb: positive := 16;
constant signalBitNb: positive := 16;
constant phaseBitNb: positive := 16;
constant clockFrequency: real := 60.0E6;
--constant clockFrequency: real := 66.0E6;"
--constant clockFrequency: real := 60.0E6;
constant clockFrequency: real := 66.0E6;
"
tm "BdDeclarativeTextMgr"
)
diagSignalLabel (Text

371
01-WaveformGenerator/WaveformGenerator_test/hds/waveform@gen_tb/struct.bd.bak
View File

@ -173,7 +173,7 @@ value "WE2330808"
)
(vvPair
variable "graphical_source_time"
value "13:13:41"
value "14:26:40"
)
(vvPair
variable "group"
@ -301,7 +301,7 @@ value "struct"
)
(vvPair
variable "time"
value "13:13:41"
value "14:26:40"
)
(vvPair
variable "unit"
@ -771,7 +771,7 @@ declText (MLText
uid 595,0
va (VaSet
)
xt "2000,21800,29200,23000"
xt "2000,23000,29200,24200"
st "SIGNAL step : unsigned(bitNb-1 DOWNTO 0)
"
)
@ -1241,7 +1241,7 @@ declText (MLText
uid 1264,0
va (VaSet
)
xt "2000,20600,32900,21800"
xt "2000,21800,32900,23000"
st "SIGNAL square : unsigned(signalBitNb-1 DOWNTO 0)
"
)
@ -1259,7 +1259,7 @@ declText (MLText
uid 1309,0
va (VaSet
)
xt "2000,23000,32700,24200"
xt "2000,24200,32700,25400"
st "SIGNAL triangle : unsigned(signalBitNb-1 DOWNTO 0)
"
)
@ -1282,7 +1282,25 @@ st "SIGNAL polygon : unsigned(signalBitNb-1 DOWNTO 0)
"
)
)
*37 (Wire
*37 (Net
uid 1404,0
decl (Decl
n "sine"
t "unsigned"
b "(signalBitNb-1 DOWNTO 0)"
o 9
suid 13,0
)
declText (MLText
uid 1405,0
va (VaSet
)
xt "2000,20600,32200,21800"
st "SIGNAL sine : unsigned(signalBitNb-1 DOWNTO 0)
"
)
)
*38 (Wire
uid 47,0
shape (OrthoPolyLine
uid 48,0
@ -1321,7 +1339,7 @@ tm "WireNameMgr"
)
on &1
)
*38 (Wire
*39 (Wire
uid 55,0
shape (OrthoPolyLine
uid 56,0
@ -1360,7 +1378,7 @@ tm "WireNameMgr"
)
on &2
)
*39 (Wire
*40 (Wire
uid 596,0
shape (OrthoPolyLine
uid 597,0
@ -1401,7 +1419,7 @@ tm "WireNameMgr"
)
on &18
)
*40 (Wire
*41 (Wire
uid 702,0
shape (OrthoPolyLine
uid 703,0
@ -1440,7 +1458,7 @@ tm "WireNameMgr"
)
on &19
)
*41 (Wire
*42 (Wire
uid 1182,0
shape (OrthoPolyLine
uid 1183,0
@ -1481,7 +1499,7 @@ tm "WireNameMgr"
)
on &33
)
*42 (Wire
*43 (Wire
uid 1265,0
shape (OrthoPolyLine
uid 1266,0
@ -1522,7 +1540,7 @@ tm "WireNameMgr"
)
on &34
)
*43 (Wire
*44 (Wire
uid 1310,0
shape (OrthoPolyLine
uid 1311,0
@ -1563,7 +1581,7 @@ tm "WireNameMgr"
)
on &35
)
*44 (Wire
*45 (Wire
uid 1357,0
shape (OrthoPolyLine
uid 1358,0
@ -1604,6 +1622,47 @@ tm "WireNameMgr"
)
on &36
)
*46 (Wire
uid 1406,0
shape (OrthoPolyLine
uid 1407,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "55750,26000,58000,38000"
pts [
"55750,26000"
"58000,26000"
"58000,38000"
]
)
start &25
end &14
sat 32
eat 1
sty 1
stc 0
st 0
sf 1
si 0
tg (WTG
uid 1410,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 1411,0
va (VaSet
font "Arial,12,0"
)
xt "57750,24500,60850,26000"
st "sine"
blo "57750,25700"
tm "WireNameMgr"
)
)
on &37
)
]
bg "65535,65535,65535"
grid (Grid
@ -1616,11 +1675,11 @@ xShown 1
yShown 1
color "26368,26368,26368"
)
packageList *45 (PackageList
packageList *47 (PackageList
uid 142,0
stg "VerticalLayoutStrategy"
textVec [
*46 (Text
*48 (Text
uid 143,0
va (VaSet
font "Arial,8,1"
@ -1629,7 +1688,7 @@ xt "0,0,6500,900"
st "Package List"
blo "0,700"
)
*47 (MLText
*49 (MLText
uid 144,0
va (VaSet
)
@ -1645,7 +1704,7 @@ compDirBlock (MlTextGroup
uid 145,0
stg "VerticalLayoutStrategy"
textVec [
*48 (Text
*50 (Text
uid 146,0
va (VaSet
isHidden 1
@ -1655,7 +1714,7 @@ xt "20000,0,30000,900"
st "Compiler Directives"
blo "20000,700"
)
*49 (Text
*51 (Text
uid 147,0
va (VaSet
isHidden 1
@ -1665,7 +1724,7 @@ xt "20000,1000,31500,1900"
st "Pre-module directives:"
blo "20000,1700"
)
*50 (MLText
*52 (MLText
uid 148,0
va (VaSet
isHidden 1
@ -1675,7 +1734,7 @@ st "`resetall
`timescale 1ns/10ps"
tm "BdCompilerDirectivesTextMgr"
)
*51 (Text
*53 (Text
uid 149,0
va (VaSet
isHidden 1
@ -1685,7 +1744,7 @@ xt "20000,4000,32000,4900"
st "Post-module directives:"
blo "20000,4700"
)
*52 (MLText
*54 (MLText
uid 150,0
va (VaSet
isHidden 1
@ -1693,7 +1752,7 @@ isHidden 1
xt "20000,0,20000,0"
tm "BdCompilerDirectivesTextMgr"
)
*53 (Text
*55 (Text
uid 151,0
va (VaSet
isHidden 1
@ -1703,7 +1762,7 @@ xt "20000,5000,31500,5900"
st "End-module directives:"
blo "20000,5700"
)
*54 (MLText
*56 (MLText
uid 152,0
va (VaSet
isHidden 1
@ -1714,7 +1773,7 @@ tm "BdCompilerDirectivesTextMgr"
]
associable 1
)
windowSize "0,0,1921,1056"
windowSize "0,24,1921,1080"
viewArea "-1200,4500,107152,62100"
cachedDiagramExtent "0,0,81000,55000"
pageSetupInfo (PageSetupInfo
@ -1740,7 +1799,7 @@ boundaryWidth 0
)
hasePageBreakOrigin 1
pageBreakOrigin "0,0"
lastUid 1364,0
lastUid 1413,0
defaultCommentText (CommentText
shape (Rectangle
layer 0
@ -1827,7 +1886,7 @@ ttg (MlTextGroup
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*55 (Text
*57 (Text
va (VaSet
font "Arial,9,0"
)
@ -1836,7 +1895,7 @@ st "<library>"
blo "1700,4200"
tm "BdLibraryNameMgr"
)
*56 (Text
*58 (Text
va (VaSet
font "Arial,9,0"
)
@ -1845,7 +1904,7 @@ st "<block>"
blo "1700,5400"
tm "BlkNameMgr"
)
*57 (Text
*59 (Text
va (VaSet
font "Arial,9,0"
)
@ -1883,21 +1942,21 @@ ttg (MlTextGroup
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*58 (Text
*60 (Text
va (VaSet
)
xt "1000,3500,3300,4500"
st "Library"
blo "1000,4300"
)
*59 (Text
*61 (Text
va (VaSet
)
xt "1000,4500,7000,5500"
st "MWComponent"
blo "1000,5300"
)
*60 (Text
*62 (Text
va (VaSet
)
xt "1000,5500,1600,6500"
@ -1941,7 +2000,7 @@ ttg (MlTextGroup
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*61 (Text
*63 (Text
va (VaSet
)
xt "1250,3500,3550,4500"
@ -1949,7 +2008,7 @@ st "Library"
blo "1250,4300"
tm "BdLibraryNameMgr"
)
*62 (Text
*64 (Text
va (VaSet
)
xt "1250,4500,6750,5500"
@ -1957,7 +2016,7 @@ st "SaComponent"
blo "1250,5300"
tm "CptNameMgr"
)
*63 (Text
*65 (Text
va (VaSet
)
xt "1250,5500,1850,6500"
@ -1995,21 +2054,21 @@ ttg (MlTextGroup
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*64 (Text
*66 (Text
va (VaSet
)
xt "950,3500,3250,4500"
st "Library"
blo "950,4300"
)
*65 (Text
*67 (Text
va (VaSet
)
xt "950,4500,7050,5500"
st "VhdlComponent"
blo "950,5300"
)
*66 (Text
*68 (Text
va (VaSet
)
xt "950,5500,1550,6500"
@ -2049,21 +2108,21 @@ ttg (MlTextGroup
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*67 (Text
*69 (Text
va (VaSet
)
xt "450,3500,2750,4500"
st "Library"
blo "450,4300"
)
*68 (Text
*70 (Text
va (VaSet
)
xt "450,4500,7550,5500"
st "VerilogComponent"
blo "450,5300"
)
*69 (Text
*71 (Text
va (VaSet
)
xt "450,5500,1050,6500"
@ -2101,7 +2160,7 @@ ttg (MlTextGroup
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*70 (Text
*72 (Text
va (VaSet
)
xt "3400,4000,4600,5000"
@ -2109,7 +2168,7 @@ st "eb1"
blo "3400,4800"
tm "HdlTextNameMgr"
)
*71 (Text
*73 (Text
va (VaSet
)
xt "3400,5000,3800,6000"
@ -2506,7 +2565,7 @@ decls (MlTextGroup
ps "BottomRightOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*72 (Text
*74 (Text
va (VaSet
font "Arial,8,1"
)
@ -2514,7 +2573,7 @@ xt "14100,20000,22000,21000"
st "Frame Declarations"
blo "14100,20800"
)
*73 (MLText
*75 (MLText
va (VaSet
)
xt "14100,21000,14100,21000"
@ -2566,7 +2625,7 @@ decls (MlTextGroup
ps "BottomRightOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*74 (Text
*76 (Text
va (VaSet
font "Arial,8,1"
)
@ -2574,7 +2633,7 @@ xt "14100,20000,22000,21000"
st "Frame Declarations"
blo "14100,20800"
)
*75 (MLText
*77 (MLText
va (VaSet
)
xt "14100,21000,14100,21000"
@ -2685,8 +2744,7 @@ st "constant bitNb: positive := 16;
constant signalBitNb: positive := 16;
constant phaseBitNb: positive := 16;
constant clockFrequency: real := 60.0E6;
--constant clockFrequency: real := 66.0E6;
"
--constant clockFrequency: real := 66.0E6;"
tm "BdDeclarativeTextMgr"
)
diagSignalLabel (Text
@ -2719,46 +2777,46 @@ tm "BdDeclarativeTextMgr"
)
commonDM (CommonDM
ldm (LogicalDM
suid 12,0
suid 13,0
usingSuid 1
emptyRow *76 (LEmptyRow
emptyRow *78 (LEmptyRow
)
uid 717,0
optionalChildren [
*77 (RefLabelRowHdr
*79 (RefLabelRowHdr
)
*78 (TitleRowHdr
*80 (TitleRowHdr
)
*79 (FilterRowHdr
*81 (FilterRowHdr
)
*80 (RefLabelColHdr
*82 (RefLabelColHdr
tm "RefLabelColHdrMgr"
)
*81 (RowExpandColHdr
*83 (RowExpandColHdr
tm "RowExpandColHdrMgr"
)
*82 (GroupColHdr
*84 (GroupColHdr
tm "GroupColHdrMgr"
)
*83 (NameColHdr
*85 (NameColHdr
tm "BlockDiagramNameColHdrMgr"
)
*84 (ModeColHdr
*86 (ModeColHdr
tm "BlockDiagramModeColHdrMgr"
)
*85 (TypeColHdr
*87 (TypeColHdr
tm "BlockDiagramTypeColHdrMgr"
)
*86 (BoundsColHdr
*88 (BoundsColHdr
tm "BlockDiagramBoundsColHdrMgr"
)
*87 (InitColHdr
*89 (InitColHdr
tm "BlockDiagramInitColHdrMgr"
)
*88 (EolColHdr
*90 (EolColHdr
tm "BlockDiagramEolColHdrMgr"
)
*89 (LeafLogPort
*91 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
@ -2770,7 +2828,7 @@ suid 1,0
)
uid 708,0
)
*90 (LeafLogPort
*92 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
@ -2782,7 +2840,7 @@ suid 2,0
)
uid 710,0
)
*91 (LeafLogPort
*93 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
@ -2795,7 +2853,7 @@ suid 3,0
)
uid 712,0
)
*92 (LeafLogPort
*94 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
@ -2807,7 +2865,7 @@ suid 4,0
)
uid 714,0
)
*93 (LeafLogPort
*95 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
@ -2820,7 +2878,7 @@ suid 5,0
)
uid 1188,0
)
*94 (LeafLogPort
*96 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
@ -2833,7 +2891,7 @@ suid 10,0
)
uid 1271,0
)
*95 (LeafLogPort
*97 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
@ -2846,7 +2904,7 @@ suid 11,0
)
uid 1316,0
)
*96 (LeafLogPort
*98 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
@ -2859,6 +2917,19 @@ suid 12,0
)
uid 1363,0
)
*99 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "sine"
t "unsigned"
b "(signalBitNb-1 DOWNTO 0)"
o 9
suid 13,0
)
)
uid 1412,0
)
]
)
pdm (PhysicalDM
@ -2866,7 +2937,7 @@ displayShortBounds 1
editShortBounds 1
uid 730,0
optionalChildren [
*97 (Sheet
*100 (Sheet
sheetRow (SheetRow
headerVa (MVa
cellColor "49152,49152,49152"
@ -2883,80 +2954,86 @@ cellColor "39936,56832,65280"
fontColor "0,0,0"
font "Tahoma,10,0"
)
emptyMRCItem *98 (MRCItem
litem &76
pos 8
emptyMRCItem *101 (MRCItem
litem &78
pos 9
dimension 20
)
uid 732,0
optionalChildren [
*99 (MRCItem
litem &77
*102 (MRCItem
litem &79
pos 0
dimension 20
uid 733,0
)
*100 (MRCItem
litem &78
*103 (MRCItem
litem &80
pos 1
dimension 23
uid 734,0
)
*101 (MRCItem
litem &79
*104 (MRCItem
litem &81
pos 2
hidden 1
dimension 20
uid 735,0
)
*102 (MRCItem
litem &89
*105 (MRCItem
litem &91
pos 0
dimension 20
uid 709,0
)
*103 (MRCItem
litem &90
*106 (MRCItem
litem &92
pos 1
dimension 20
uid 711,0
)
*104 (MRCItem
litem &91
*107 (MRCItem
litem &93
pos 2
dimension 20
uid 713,0
)
*105 (MRCItem
litem &92
*108 (MRCItem
litem &94
pos 3
dimension 20
uid 715,0
)
*106 (MRCItem
litem &93
*109 (MRCItem
litem &95
pos 4
dimension 20
uid 1189,0
)
*107 (MRCItem
litem &94
*110 (MRCItem
litem &96
pos 5
dimension 20
uid 1272,0
)
*108 (MRCItem
litem &95
*111 (MRCItem
litem &97
pos 6
dimension 20
uid 1317,0
)
*109 (MRCItem
litem &96
*112 (MRCItem
litem &98
pos 7
dimension 20
uid 1364,0
)
*113 (MRCItem
litem &99
pos 8
dimension 20
uid 1413,0
)
]
)
sheetCol (SheetCol
@ -2968,50 +3045,50 @@ textAngle 90
)
uid 736,0
optionalChildren [
*110 (MRCItem
litem &80
*114 (MRCItem
litem &82
pos 0
dimension 20
uid 737,0
)
*111 (MRCItem
litem &82
*115 (MRCItem
litem &84
pos 1
dimension 50
uid 738,0
)
*112 (MRCItem
litem &83
*116 (MRCItem
litem &85
pos 2
dimension 100
uid 739,0
)
*113 (MRCItem
litem &84
*117 (MRCItem
litem &86
pos 3
dimension 50
uid 740,0
)
*114 (MRCItem
litem &85
*118 (MRCItem
litem &87
pos 4
dimension 100
uid 741,0
)
*115 (MRCItem
litem &86
*119 (MRCItem
litem &88
pos 5
dimension 100
uid 742,0
)
*116 (MRCItem
litem &87
*120 (MRCItem
litem &89
pos 6
dimension 50
uid 743,0
)
*117 (MRCItem
litem &88
*121 (MRCItem
litem &90
pos 7
dimension 80
uid 744,0
@ -3031,38 +3108,38 @@ uid 716,0
)
genericsCommonDM (CommonDM
ldm (LogicalDM
emptyRow *118 (LEmptyRow
emptyRow *122 (LEmptyRow
)
uid 746,0
optionalChildren [
*119 (RefLabelRowHdr
*123 (RefLabelRowHdr
)
*120 (TitleRowHdr
*124 (TitleRowHdr
)
*121 (FilterRowHdr
*125 (FilterRowHdr
)
*122 (RefLabelColHdr
*126 (RefLabelColHdr
tm "RefLabelColHdrMgr"
)
*123 (RowExpandColHdr
*127 (RowExpandColHdr
tm "RowExpandColHdrMgr"
)
*124 (GroupColHdr
*128 (GroupColHdr
tm "GroupColHdrMgr"
)
*125 (NameColHdr
*129 (NameColHdr
tm "GenericNameColHdrMgr"
)
*126 (TypeColHdr
*130 (TypeColHdr
tm "GenericTypeColHdrMgr"
)
*127 (InitColHdr
*131 (InitColHdr
tm "GenericValueColHdrMgr"
)
*128 (PragmaColHdr
*132 (PragmaColHdr
tm "GenericPragmaColHdrMgr"
)
*129 (EolColHdr
*133 (EolColHdr
tm "GenericEolColHdrMgr"
)
]
@ -3070,7 +3147,7 @@ tm "GenericEolColHdrMgr"
pdm (PhysicalDM
uid 758,0
optionalChildren [
*130 (Sheet
*134 (Sheet
sheetRow (SheetRow
headerVa (MVa
cellColor "49152,49152,49152"
@ -3087,27 +3164,27 @@ cellColor "39936,56832,65280"
fontColor "0,0,0"
font "Tahoma,10,0"
)
emptyMRCItem *131 (MRCItem
litem &118
emptyMRCItem *135 (MRCItem
litem &122
pos 0
dimension 20
)
uid 760,0
optionalChildren [
*132 (MRCItem
litem &119
*136 (MRCItem
litem &123
pos 0
dimension 20
uid 761,0
)
*133 (MRCItem
litem &120
*137 (MRCItem
litem &124
pos 1
dimension 23
uid 762,0
)
*134 (MRCItem
litem &121
*138 (MRCItem
litem &125
pos 2
hidden 1
dimension 20
@ -3124,44 +3201,44 @@ textAngle 90
)
uid 764,0
optionalChildren [
*135 (MRCItem
litem &122
*139 (MRCItem
litem &126
pos 0
dimension 20
uid 765,0
)
*136 (MRCItem
litem &124
*140 (MRCItem
litem &128
pos 1
dimension 50
uid 766,0
)
*137 (MRCItem
litem &125
*141 (MRCItem
litem &129
pos 2
dimension 100
uid 767,0
)
*138 (MRCItem
litem &126
*142 (MRCItem
litem &130
pos 3
dimension 100
uid 768,0
)
*139 (MRCItem
litem &127
*143 (MRCItem
litem &131
pos 4
dimension 50
uid 769,0
)
*140 (MRCItem
litem &128
*144 (MRCItem
litem &132
pos 5
dimension 50
uid 770,0
)
*141 (MRCItem
litem &129
*145 (MRCItem
litem &133
pos 6
dimension 80
uid 771,0

6
01-WaveformGenerator/WaveformGenerator_test/hds/waveform@gen_tb/struct.bd.lck
View File

@ -1,6 +0,0 @@
EDIT_LOCK
remi.heredero
UNKNOWN
WE2330808
15212
01.03.2024-14:26:32.427000