Klagarge/SEm-Labos
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add resize + tabel

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This commit is contained in:
Rémi Heredero
2024-03-05 11:48:52 +01:00
parent 73dd7da0db
commit 681c567da7
46 changed files with 14970 additions and 524 deletions
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6
01-WaveformGenerator/WaveformGenerator_test/hdl/waveformgen_tb_struct.vhg
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@ -3,7 +3,7 @@
--
-- Created:
-- by - remi.heredero.UNKNOWN (WE2330808)
-- at - 14:26:40 01.03.2024
-- at - 15:12:57 01.03.2024
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5)
--
@ -20,8 +20,8 @@ ARCHITECTURE struct OF waveformGen_tb IS
constant bitNb: positive := 16;
constant signalBitNb: positive := 16;
constant phaseBitNb: positive := 16;
constant clockFrequency: real := 60.0E6;
--constant clockFrequency: real := 66.0E6;
--constant clockFrequency: real := 60.0E6;
constant clockFrequency: real := 66.0E6;
-- Internal signal declarations
SIGNAL clock : std_ulogic;