add resize + tabel

02-SplineInterpolator/SplineInterpolator_test/hdl/sinegen_tb_entity.vhg

@@ -0,0 +1,15 @@
+-- VHDL Entity SplineInterpolator_test.sineGen_tb.symbol
+--
+-- Created:
+--          by - francois.francois (Aphelia)
+--          at - 13:00:04 02/19/19
+--
+-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5)
+--
+
+
+ENTITY sineGen_tb IS
+-- Declarations
+
+END sineGen_tb ;
+

02-SplineInterpolator/SplineInterpolator_test/hdl/sinegen_tb_struct.vhg

@@ -0,0 +1,108 @@
+--
+-- VHDL Architecture SplineInterpolator_test.sineGen_tb.struct
+--
+-- Created:
+--          by - axel.amand.UNKNOWN (WE7860)
+--          at - 14:41:39 28.04.2023
+--
+-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5)
+--
+LIBRARY ieee;
+  USE ieee.std_logic_1164.all;
+  USE ieee.numeric_std.ALL;
+
+LIBRARY SplineInterpolator;
+LIBRARY SplineInterpolator_test;
+
+ARCHITECTURE struct OF sineGen_tb IS
+
+    -- Architecture declarations
+    constant signalBitNb: positive := 16;
+    constant phaseBitNb: positive := 10;
+    constant clockFrequency: real := 60.0E6;
+    --constant clockFrequency: real := 66.0E6;
+
+    -- Internal signal declarations
+    SIGNAL clock    : std_ulogic;
+    SIGNAL reset    : std_ulogic;
+    SIGNAL sawtooth : unsigned(signalBitNb-1 DOWNTO 0);
+    SIGNAL sine     : unsigned(signalBitNb-1 DOWNTO 0);
+    SIGNAL square   : unsigned(signalBitNb-1 DOWNTO 0);
+    SIGNAL step     : unsigned(phaseBitNb-1 DOWNTO 0);
+    SIGNAL triangle : unsigned(signalBitNb-1 DOWNTO 0);
+
+
+    -- Component Declarations
+    COMPONENT sineGen
+    GENERIC (
+        signalBitNb : positive := 16;
+        phaseBitNb  : positive := 10
+    );
+    PORT (
+        clock    : IN     std_ulogic ;
+        reset    : IN     std_ulogic ;
+        step     : IN     unsigned (phaseBitNb-1 DOWNTO 0);
+        sawtooth : OUT    unsigned (signalBitNb-1 DOWNTO 0);
+        sine     : OUT    unsigned (signalBitNb-1 DOWNTO 0);
+        square   : OUT    unsigned (signalBitNb-1 DOWNTO 0);
+        triangle : OUT    unsigned (signalBitNb-1 DOWNTO 0)
+    );
+    END COMPONENT;
+    COMPONENT sineGen_tester
+    GENERIC (
+        signalBitNb    : positive := 16;
+        phaseBitNb     : positive := 10;
+        clockFrequency : real     := 60.0E6
+    );
+    PORT (
+        sawtooth : IN     unsigned (signalBitNb-1 DOWNTO 0);
+        sine     : IN     unsigned (signalBitNb-1 DOWNTO 0);
+        square   : IN     unsigned (signalBitNb-1 DOWNTO 0);
+        triangle : IN     unsigned (signalBitNb-1 DOWNTO 0);
+        clock    : OUT    std_ulogic ;
+        reset    : OUT    std_ulogic ;
+        step     : OUT    unsigned (phaseBitNb-1 DOWNTO 0)
+    );
+    END COMPONENT;
+
+    -- Optional embedded configurations
+    -- pragma synthesis_off
+    FOR ALL : sineGen USE ENTITY SplineInterpolator.sineGen;
+    FOR ALL : sineGen_tester USE ENTITY SplineInterpolator_test.sineGen_tester;
+    -- pragma synthesis_on
+
+
+BEGIN
+
+    -- Instance port mappings.
+    I_DUT : sineGen
+        GENERIC MAP (
+            signalBitNb => signalBitNb,
+            phaseBitNb  => phaseBitNb
+        )
+        PORT MAP (
+            clock    => clock,
+            reset    => reset,
+            step     => step,
+            sawtooth => sawtooth,
+            sine     => sine,
+            square   => square,
+            triangle => triangle
+        );
+    I_tb : sineGen_tester
+        GENERIC MAP (
+            signalBitNb    => signalBitNb,
+            phaseBitNb     => phaseBitNb,
+            clockFrequency => clockFrequency
+        )
+        PORT MAP (
+            sawtooth => sawtooth,
+            sine     => sine,
+            square   => square,
+            triangle => triangle,
+            clock    => clock,
+            reset    => reset,
+            step     => step
+        );
+
+END struct;

02-SplineInterpolator/SplineInterpolator_test/hdl/sinegen_tester_entity.vhg

@@ -0,0 +1,32 @@
+-- VHDL Entity SplineInterpolator_test.sineGen_tester.interface
+--
+-- Created:
+--          by - axel.amand.UNKNOWN (WE7860)
+--          at - 14:41:39 28.04.2023
+--
+-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5)
+--
+LIBRARY ieee;
+  USE ieee.std_logic_1164.all;
+  USE ieee.numeric_std.ALL;
+
+ENTITY sineGen_tester IS
+    GENERIC( 
+        signalBitNb    : positive := 16;
+        phaseBitNb     : positive := 10;
+        clockFrequency : real     := 60.0E6
+    );
+    PORT( 
+        sawtooth : IN     unsigned (signalBitNb-1 DOWNTO 0);
+        sine     : IN     unsigned (signalBitNb-1 DOWNTO 0);
+        square   : IN     unsigned (signalBitNb-1 DOWNTO 0);
+        triangle : IN     unsigned (signalBitNb-1 DOWNTO 0);
+        clock    : OUT    std_ulogic;
+        reset    : OUT    std_ulogic;
+        step     : OUT    unsigned (phaseBitNb-1 DOWNTO 0)
+    );
+
+-- Declarations
+
+END sineGen_tester ;
+

02-SplineInterpolator/SplineInterpolator_test/hds/.xrf/sinegen_tb_entity.xrf

@@ -0,0 +1,12 @@
+DESIGN sine@gen_tb
+VIEW symbol.sb
+NO_GRAPHIC 0
+DESIGN sine@gen_tb
+VIEW symbol.sb
+GRAPHIC 50,0 8 0 
+DESIGN sine@gen_tb
+VIEW symbol.sb
+GRAPHIC 1,0 11 0 
+DESIGN sine@gen_tb
+VIEW symbol.sb
+GRAPHIC 1,0 12 0 

02-SplineInterpolator/SplineInterpolator_test/hds/.xrf/sinegen_tb_struct.xrf

@@ -0,0 +1,153 @@
+DESIGN sine@gen_tb
+VIEW struct.bd
+NO_GRAPHIC 0
+DESIGN sine@gen_tb
+VIEW struct.bd
+GRAPHIC 142,0 9 0 
+DESIGN sine@gen_tb
+VIEW struct.bd
+NO_GRAPHIC 12
+DESIGN sine@gen_tb
+VIEW struct.bd
+GRAPHIC 0,0 16 2 
+DESIGN sine@gen_tb
+VIEW struct.bd
+GRAPHIC 1,0 19 0 
+DESIGN sine@gen_tb
+VIEW struct.bd
+NO_GRAPHIC 19
+DESIGN sine@gen_tb
+VIEW struct.bd
+GRAPHIC 53,0 25 0 
+DESIGN sine@gen_tb
+VIEW struct.bd
+GRAPHIC 45,0 26 0 
+DESIGN sine@gen_tb
+VIEW struct.bd
+GRAPHIC 933,0 27 0 
+DESIGN sine@gen_tb
+VIEW struct.bd
+GRAPHIC 909,0 28 0 
+DESIGN sine@gen_tb
+VIEW struct.bd
+GRAPHIC 925,0 29 0 
+DESIGN sine@gen_tb
+VIEW struct.bd
+GRAPHIC 996,0 30 0 
+DESIGN sine@gen_tb
+VIEW struct.bd
+GRAPHIC 917,0 31 0 
+DESIGN sine@gen_tb
+VIEW struct.bd
+NO_GRAPHIC 32
+DESIGN sine@gen_tb
+VIEW struct.bd
+NO_GRAPHIC 33
+LIBRARY SplineInterpolator
+DESIGN sine@gen
+VIEW struct
+GRAPHIC 1519,0 35 0 
+DESIGN sine@gen
+VIEW symbol.sb
+GRAPHIC 14,0 36 1 
+DESIGN sine@gen
+VIEW symbol.sb
+GRAPHIC 52,0 41 0 
+DESIGN sine@gen
+VIEW symbol.sb
+GRAPHIC 88,0 42 0 
+DESIGN sine@gen
+VIEW symbol.sb
+GRAPHIC 128,0 43 0 
+DESIGN sine@gen
+VIEW symbol.sb
+GRAPHIC 98,0 44 0 
+DESIGN sine@gen
+VIEW symbol.sb
+GRAPHIC 103,0 45 0 
+DESIGN sine@gen
+VIEW symbol.sb
+GRAPHIC 108,0 46 0 
+DESIGN sine@gen
+VIEW symbol.sb
+GRAPHIC 118,0 47 0 
+LIBRARY SplineInterpolator_test
+DESIGN sine@gen_tester
+VIEW test
+GRAPHIC 421,0 50 0 
+DESIGN sine@gen_tester
+VIEW interface
+GRAPHIC 14,0 51 1 
+DESIGN sine@gen_tb
+VIEW struct.bd
+GRAPHIC 935,0 57 0 
+DESIGN sine@gen_tb
+VIEW struct.bd
+GRAPHIC 911,0 58 0 
+DESIGN sine@gen_tb
+VIEW struct.bd
+GRAPHIC 927,0 59 0 
+DESIGN sine@gen_tb
+VIEW struct.bd
+GRAPHIC 919,0 60 0 
+DESIGN sine@gen_tb
+VIEW struct.bd
+GRAPHIC 55,0 61 0 
+DESIGN sine@gen_tb
+VIEW struct.bd
+GRAPHIC 47,0 62 0 
+DESIGN sine@gen_tb
+VIEW struct.bd
+GRAPHIC 998,0 63 0 
+LIBRARY SplineInterpolator_test
+DESIGN sine@gen_tb
+VIEW struct.bd
+NO_GRAPHIC 66
+DESIGN sine@gen_tb
+VIEW struct.bd
+GRAPHIC 1519,0 69 0 
+DESIGN sine@gen_tb
+VIEW struct.bd
+GRAPHIC 421,0 70 0 
+DESIGN sine@gen_tb
+VIEW struct.bd
+NO_GRAPHIC 73
+DESIGN sine@gen_tb
+VIEW struct.bd
+NO_GRAPHIC 75
+DESIGN sine@gen_tb
+VIEW struct.bd
+GRAPHIC 1519,0 77 0 
+DESIGN sine@gen_tb
+VIEW struct.bd
+GRAPHIC 1526,0 78 1 
+DESIGN sine@gen_tb
+VIEW struct.bd
+GRAPHIC 55,0 83 0 
+DESIGN sine@gen_tb
+VIEW struct.bd
+GRAPHIC 47,0 84 0 
+DESIGN sine@gen_tb
+VIEW struct.bd
+GRAPHIC 998,0 85 0 
+DESIGN sine@gen_tb
+VIEW struct.bd
+GRAPHIC 935,0 86 0 
+DESIGN sine@gen_tb
+VIEW struct.bd
+GRAPHIC 911,0 87 0 
+DESIGN sine@gen_tb
+VIEW struct.bd
+GRAPHIC 927,0 88 0 
+DESIGN sine@gen_tb
+VIEW struct.bd
+GRAPHIC 919,0 89 0 
+DESIGN sine@gen_tb
+VIEW struct.bd
+GRAPHIC 421,0 91 0 
+DESIGN sine@gen_tb
+VIEW struct.bd
+GRAPHIC 428,0 92 1 
+DESIGN sine@gen_tb
+VIEW struct.bd
+NO_GRAPHIC 107

02-SplineInterpolator/SplineInterpolator_test/hds/.xrf/sinegen_tester_entity.xrf

@@ -0,0 +1,36 @@
+DESIGN sine@gen_tester
+VIEW interface
+NO_GRAPHIC 0
+DESIGN sine@gen_tester
+VIEW interface
+GRAPHIC 50,0 8 0 
+DESIGN sine@gen_tester
+VIEW interface
+GRAPHIC 13,0 13 1 
+DESIGN sine@gen_tester
+VIEW interface
+GRAPHIC 409,0 19 0 
+DESIGN sine@gen_tester
+VIEW interface
+GRAPHIC 414,0 20 0 
+DESIGN sine@gen_tester
+VIEW interface
+GRAPHIC 419,0 21 0 
+DESIGN sine@gen_tester
+VIEW interface
+GRAPHIC 429,0 22 0 
+DESIGN sine@gen_tester
+VIEW interface
+GRAPHIC 399,0 23 0 
+DESIGN sine@gen_tester
+VIEW interface
+GRAPHIC 404,0 24 0 
+DESIGN sine@gen_tester
+VIEW interface
+GRAPHIC 424,0 25 0 
+DESIGN sine@gen_tester
+VIEW interface
+GRAPHIC 1,0 28 0 
+DESIGN sine@gen_tester
+VIEW interface
+GRAPHIC 1,0 29 0