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This commit is contained in:
Rémi Heredero
2024-04-09 11:46:35 +02:00
parent 95d5c14ee7
commit 7f4a0c615f
36 changed files with 10015 additions and 254 deletions
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15
05-Morse/Morse_test/hdl/chartomorsecontroller_tb_entity.vhg Normal file
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-- VHDL Entity Morse_test.charToMorseController_tb.symbol
--
-- Created:
-- by - francois.francois (Aphelia)
-- at - 09:12:49 03/29/19
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5)
--
ENTITY charToMorseController_tb IS
-- Declarations
END charToMorseController_tb ;

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05-Morse/Morse_test/hdl/chartomorsecontroller_tb_struct.vhg Normal file
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--
-- VHDL Architecture Morse_test.charToMorseController_tb.struct
--
-- Created:
-- by - axel.amand.UNKNOWN (WE7860)
-- at - 14:50:43 28.04.2023
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.ALL;
LIBRARY Morse;
LIBRARY Morse_test;
ARCHITECTURE struct OF charToMorseController_tb IS
-- Architecture declarations
constant characterBitNb: positive := 7;
constant unitCountBitNb: positive := 3;
constant unitDuration: real := 50.0E-6;
constant clockFrequency: real := 60.0E6;
--constant clockFrequency: real := 66.0E6;
-- Internal signal declarations
SIGNAL char : std_ulogic_vector(characterBitNb-1 DOWNTO 0);
SIGNAL charNotReady : std_ulogic;
SIGNAL clock : std_ulogic;
SIGNAL done : std_ulogic;
SIGNAL morseOut : std_ulogic;
SIGNAL readChar : std_ulogic;
SIGNAL reset : std_ulogic;
SIGNAL startCounter : std_ulogic;
SIGNAL unitNb : unsigned(unitCountBitNb-1 DOWNTO 0);
-- Component Declarations
COMPONENT charToMorseController
GENERIC (
characterBitNb : positive := 8;
unitCountBitNb : positive := 3
);
PORT (
morseOut : OUT std_ulogic ;
clock : IN std_ulogic ;
reset : IN std_ulogic ;
charNotReady : IN std_ulogic ;
char : IN std_ulogic_vector (characterBitNb-1 DOWNTO 0);
startCounter : OUT std_ulogic ;
unitNb : OUT unsigned (unitCountBitNb-1 DOWNTO 0);
counterDone : IN std_ulogic ;
readChar : OUT std_ulogic
);
END COMPONENT;
COMPONENT unitCounter
GENERIC (
unitCountDivide : positive := 10E3;
unitCountBitNb : positive := 3
);
PORT (
clock : IN std_ulogic ;
reset : IN std_ulogic ;
startCounter : IN std_ulogic ;
unitNb : IN unsigned (unitCountBitNb-1 DOWNTO 0);
done : OUT std_ulogic
);
END COMPONENT;
COMPONENT charToMorseController_tester
GENERIC (
clockFrequency : real;
characterBitNb : positive
);
PORT (
morseOut : IN std_ulogic ;
readChar : IN std_ulogic ;
char : OUT std_ulogic_vector (characterBitNb-1 DOWNTO 0);
charNotReady : OUT std_ulogic ;
clock : OUT std_ulogic ;
reset : OUT std_ulogic
);
END COMPONENT;
-- Optional embedded configurations
-- pragma synthesis_off
FOR ALL : charToMorseController USE ENTITY Morse.charToMorseController;
FOR ALL : charToMorseController_tester USE ENTITY Morse_test.charToMorseController_tester;
FOR ALL : unitCounter USE ENTITY Morse.unitCounter;
-- pragma synthesis_on
BEGIN
-- Instance port mappings.
I_DUT : charToMorseController
GENERIC MAP (
characterBitNb => characterBitNb,
unitCountBitNb => unitCountBitNb
)
PORT MAP (
morseOut => morseOut,
clock => clock,
reset => reset,
charNotReady => charNotReady,
char => char,
startCounter => startCounter,
unitNb => unitNb,
counterDone => done,
readChar => readChar
);
I_cnt : unitCounter
GENERIC MAP (
unitCountDivide => integer(clockFrequency*unitDuration + 0.5),
unitCountBitNb => unitCountBitNb
)
PORT MAP (
clock => clock,
reset => reset,
startCounter => startCounter,
unitNb => unitNb,
done => done
);
I_tester : charToMorseController_tester
GENERIC MAP (
clockFrequency => clockFrequency,
characterBitNb => characterBitNb
)
PORT MAP (
morseOut => morseOut,
readChar => readChar,
char => char,
charNotReady => charNotReady,
clock => clock,
reset => reset
);
END struct;

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05-Morse/Morse_test/hdl/chartomorsecontroller_tester_entity.vhg Normal file
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-- VHDL Entity Morse_test.charToMorseController_tester.interface
--
-- Created:
-- by - axel.amand.UNKNOWN (WE7860)
-- at - 14:50:43 28.04.2023
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.ALL;
ENTITY charToMorseController_tester IS
GENERIC(
clockFrequency : real;
characterBitNb : positive
);
PORT(
morseOut : IN std_ulogic;
readChar : IN std_ulogic;
char : OUT std_ulogic_vector (characterBitNb-1 DOWNTO 0);
charNotReady : OUT std_ulogic;
clock : OUT std_ulogic;
reset : OUT std_ulogic
);
-- Declarations
END charToMorseController_tester ;

15
05-Morse/Morse_test/hdl/morseencoder_tb_entity.vhg Normal file
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-- VHDL Entity Morse_test.morseEncoder_tb.symbol
--
-- Created:
-- by - francois.francois (Aphelia)
-- at - 09:12:49 03/29/19
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5)
--
ENTITY morseEncoder_tb IS
-- Declarations
END morseEncoder_tb ;

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05-Morse/Morse_test/hdl/morseencoder_tb_struct.vhg Normal file
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--
-- VHDL Architecture Morse_test.morseEncoder_tb.struct
--
-- Created:
-- by - axel.amand.UNKNOWN (WE7860)
-- at - 14:51:13 28.04.2023
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.ALL;
LIBRARY Morse;
LIBRARY Morse_test;
ARCHITECTURE struct OF morseEncoder_tb IS
-- Architecture declarations
constant clockFrequency: real := 60.0E6;
--constant clockFrequency: real := 66.0E6;
constant uartBaudRate: real := 115.2E3;
constant uartDataBitNb: positive := 7;
constant morseUnitDuration: real := 50.0E-6;
constant morseToneFrequency: real := 10.0/morseUnitDuration;
-- Internal signal declarations
SIGNAL RxD : std_ulogic;
SIGNAL clock : std_ulogic;
SIGNAL morseCode : std_ulogic;
SIGNAL reset : std_ulogic;
-- Component Declarations
COMPONENT morseEncoder
GENERIC (
clockFrequency : real := 100.0E6;
uartBaudRate : real := 115.2E3;
uartDataBitNb : positive := 8;
unitDuration : real := 100.0E-3;
toneFrequency : real := 300.0
);
PORT (
morseCode : OUT std_ulogic ;
clock : IN std_ulogic ;
reset : IN std_ulogic ;
RxD : IN std_ulogic
);
END COMPONENT;
COMPONENT morseEncoder_tester
GENERIC (
clockFrequency : real;
uartBaudRate : real;
uartDataBitNb : positive
);
PORT (
morseCode : IN std_ulogic ;
RxD : OUT std_ulogic ;
clock : OUT std_ulogic ;
reset : OUT std_ulogic
);
END COMPONENT;
-- Optional embedded configurations
-- pragma synthesis_off
FOR ALL : morseEncoder USE ENTITY Morse.morseEncoder;
FOR ALL : morseEncoder_tester USE ENTITY Morse_test.morseEncoder_tester;
-- pragma synthesis_on
BEGIN
-- Instance port mappings.
I_DUT : morseEncoder
GENERIC MAP (
clockFrequency => clockFrequency,
uartBaudRate => uartBaudRate,
uartDataBitNb => uartDataBitNb,
unitDuration => morseUnitDuration,
toneFrequency => morseToneFrequency
)
PORT MAP (
morseCode => morseCode,
clock => clock,
reset => reset,
RxD => RxD
);
I_tester : morseEncoder_tester
GENERIC MAP (
clockFrequency => clockFrequency,
uartBaudRate => uartBaudRate,
uartDataBitNb => uartDataBitNb
)
PORT MAP (
morseCode => morseCode,
RxD => RxD,
clock => clock,
reset => reset
);
END struct;

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05-Morse/Morse_test/hdl/morseencoder_tester_entity.vhg Normal file
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-- VHDL Entity Morse_test.morseEncoder_tester.interface
--
-- Created:
-- by - axel.amand.UNKNOWN (WE7860)
-- at - 14:51:13 28.04.2023
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.ALL;
ENTITY morseEncoder_tester IS
GENERIC(
clockFrequency : real;
uartBaudRate : real;
uartDataBitNb : positive
);
PORT(
morseCode : IN std_ulogic;
RxD : OUT std_ulogic;
clock : OUT std_ulogic;
reset : OUT std_ulogic
);
-- Declarations
END morseEncoder_tester ;