Klagarge/SEm-Labos
1
0
Fork 0
Code

Merge pull request #1 from hei-synd-sem-stud/lab1-waveformGenerator

Browse Source 
Lab1 + 2 waveform generator
This commit is contained in:
Rémi Heredero 2024-03-15 15:05:06 +01:00 committed by GitHub
commit 95d5c14ee7
No known key found for this signature in database
GPG Key ID: B5690EEEBB952194
690 changed files with 301745 additions and 892 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

110
.gitignore vendored Normal file
View File

@ -0,0 +1,110 @@
ipcache
*.ip_user_files
*.dcp
*.cache
*.data
*.xpr
*.log
*.bld
*.chk
*.cmd_log
*.cxt
*.gise
*.gyd
*.jed
*.lso
*.mfd
*.nga
*.ngc
*.ngd
*.ngr
*.pad
*.pnx
*.prj
*.rpt
*.stx
*.syr
*.tim
*.tspec
*.vm6
*.xst
*.html
*.xrpt
*.err
*_html
*.sld
*.txt
*.qsys
*.csv
xst
netgen
iseconfig
xlnx_auto*
_ngo
_xmsgs
component.xml
*.jou
xgui
*.runs
*.srcs
*.sdk
.Xil
*_INFO.txt
*_dump.txt
db
*.asm.rpt
*.done
*.eda.rpt
*.fit.*
*.map.*
*.sta.*
*.qsf
*.qpf
*.qws
*.sof
*.rbf
system_qsys_script.tcl
hc_output
hps_isw_handoff
hps_sdram_*.csv
incremental_db
system_bd/
reconfig_mif
*.sopcinfo
*.jdi
*.pin
*.os
*webtalk*
*.xml
*.hw
gui
.timestamp_intel
temporary_case_dependencies.mk
*.zip
*.str
*.vcd
*.wlf
transcript
tags
boot_bin
_info
_vmake
*.qdb
*.qpg
*.qtl
*.xpe
*.gen*
*.xsa
*.pdi
library/**/bd/bd.tcl
*.syn.smsg
*.syn.summary
qdb
tmp-clearbox
*.bin
__pycache__
_build
.qsys_edit
.github/CODEOWNERS
.github/PULL_REQUEST_TEMPLATE.md
library/**/.lock

55
01-WaveformGenerator/Prefs/hds_team/v2019.2/hds_team_prefs.bak Normal file
View File

@ -0,0 +1,55 @@
version "8.0"
RenoirTeamPreferences [
(BaseTeamPreferences
version "1.1"
verConcat 0
ttDGProps [
]
fcDGProps [
]
smDGProps [
]
asmDGProps [
]
bdDGProps [
]
syDGProps [
]
)
(VersionControlTeamPreferences
version "1.1"
VMPlugin ""
VMRepository "$HDS_HOME/examples/hds_scratch/hds_repository"
VMRcsHdsRepository "$HDS_HOME/examples/hds_scratch/hds_repository/%(library)/hds_vm"
VMRcsHdlRepository "$HDS_HOME/examples/hds_scratch/hds_repository/%(library)/hdl_vm"
VMCvsHdsRepository "$HDS_HOME/examples/hds_scratch/hds_repository/hds_vm"
VMCvsHdlRepository "$HDS_HOME/examples/hds_scratch/hds_repository/hdl_vm"
VMCVSmkIIHdsRepository "$HDS_HOME/examples/hds_scratch/hds_repository/hds_vm"
VMCVSmkIIHdlRepository "$HDS_HOME/examples/hds_scratch/hds_repository"
VMVssHdsRepository "$/hds_scratch/hds_repository/%(library)/hds_vm"
VMVssHdlRepository "$/hds_scratch/hds_repository/%(library)/hdl_vm"
VMDsHdsRepository "sync://<host_name>:<port>/hds_scratch/hds_repository/hds_vm"
VMDsHdlRepository "sync://<host_name>:<port>/hds_scratch/hds_repository/hdl_vm"
VMPvcsHdsRepository "$HDS_HOME/examples/hds_scratch/hds_repository/hds_vm"
VMPvcsHdlRepository "$HDS_HOME/examples/hds_scratch/hds_repository/hdl_vm"
VMSvnHdlRepository ""
VMDefaultView 1
VMCurrentDesignHierarchyOnly 0
VMUserData 1
VMGeneratedHDL 0
VMVerboseMode 0
VMAlwaysEmpty 0
VMSetTZ 1
VMSymbol 1
VMCurrentDesignHierarchy 0
VMMultipleRepositoryMode 0
VMSnapshotViewMode 0
backupNameClashes 1
clearCaseMaster 0
)
(CustomizeTeamPreferences
version "1.1"
FileTypes [
]
)
]

277
01-WaveformGenerator/Prefs/hds_user/v2019.2/hds_user_prefs
View File

@ -1279,6 +1279,7 @@ projectPaths [
"C:\\work\\repo\\edu\\sem\\labo\\solution\\sem_labs\\01-WaveformGenerator\\Prefs\\hds.hdp"
"C:\\work\\edu\\sem\\labo\\sem_labs\\01-WaveformGenerator\\Prefs\\hds.hdp"
"C:\\dev\\sem-labs\\01-WaveformGenerator\\Prefs\\hds.hdp"
"C:\\Users\\remi.heredero\\GIT\\2024-sem-labs-herederoremi\\01-WaveformGenerator\\Prefs\\hds.hdp"
]
libMappingsRootDir ""
teamLibMappingsRootDir ""
@ -1299,288 +1300,144 @@ exportedDirectories [
exportStdIncludeRefs 1
exportStdPackageRefs 1
)
printerName "\\\\vmenpprint1.hevs.ch\\VS-FOLLOWME-PRN"
printerName "\\\\vmenpprint1\\VS-ENP.23.N308-PRN"
pageSizes [
(PageSizeInfo
name "12\" x 18\""
type 512
width 1106
height 1658
name "Letter"
width 783
height 1013
)
(PageSizeInfo
name "11\" x 17\""
type 17
width 1013
height 1566
)
(PageSizeInfo
name "Legal (8,5\" x 14\")"
name "Legal"
type 5
width 783
height 1290
)
(PageSizeInfo
name "Letter (8,5\" x 11\")"
width 783
height 1013
)
(PageSizeInfo
name "Executive (7,25\"x10,5\")"
type 7
width 667
height 967
)
(PageSizeInfo
name "5,5\" x 8,5\""
name "Statement"
type 6
width 506
height 783
)
(PageSizeInfo
name "A3 (297 x 420 mm)"
name "Executive"
type 7
width 667
height 967
)
(PageSizeInfo
name "A3"
type 8
width 1077
height 1523
)
(PageSizeInfo
name "A4 (210 x 297 mm)"
name "A4"
type 9
width 761
height 1077
)
(PageSizeInfo
name "A5 (148 x 210 mm)"
name "A5"
type 11
width 538
width 536
height 761
)
(PageSizeInfo
name "A6 (105 x 148 mm)"
type 70
width 380
height 538
)
(PageSizeInfo
name "B4 JIS (257 x 364 mm)"
name "B4 (JIS)"
type 12
width 932
height 1320
)
(PageSizeInfo
name "B5 JIS (182 x 257 mm)"
name "B5 (JIS)"
type 13
width 660
height 932
)
(PageSizeInfo
name "B6 JIS (128 x 182 mm)"
type 88
width 464
height 660
name "11×17"
type 17
width 1013
height 1566
)
(PageSizeInfo
name "8\" x 13\""
type 518
width 737
height 1198
)
(PageSizeInfo
name "8,25\" x 13\""
type 519
width 760
height 1198
)
(PageSizeInfo
name "8,5\" x 13\""
type 14
width 783
height 1198
)
(PageSizeInfo
name "8.5\" x 13.4\""
type 551
width 783
height 1235
)
(PageSizeInfo
name "Com10 Env.(4,125\"x9,5\")"
name "Envelope #10"
type 20
width 380
width 379
height 875
)
(PageSizeInfo
name "Env.Monar.(3,875\"x7,5\")"
type 37
width 357
height 691
)
(PageSizeInfo
name "Env. DL (110 x 220 mm)"
name "Envelope DL"
type 27
width 399
height 798
)
(PageSizeInfo
name "Env. C6 (114 x 162 mm)"
type 31
width 413
height 587
)
(PageSizeInfo
name "Env. C5 (162 x 229 mm)"
name "Envelope C5"
type 28
width 587
height 830
)
(PageSizeInfo
name "8K (267 x 390 mm)"
type 520
width 968
height 1415
name "Envelope B5"
type 34
width 638
height 907
)
(PageSizeInfo
name "16K (195 x 267 mm)"
type 521
width 707
height 968
name "Envelope Monarch"
type 37
width 357
height 691
)
(PageSizeInfo
name "8,25\" x 14\""
type 522
width 760
height 1290
name "Japanese Postcard"
type 43
width 362
height 536
)
(PageSizeInfo
name "11\" x 14\""
type 524
width 1013
height 1290
name "A6"
type 70
width 380
height 536
)
(PageSizeInfo
name "13\" x 19,2\""
type 525
width 1198
height 1769
name "Double Japan Postcard Rotated"
type 82
width 536
height 725
)
(PageSizeInfo
name "13\" x 19\""
type 526
width 1198
height 1751
name "Executive (JIS)"
type 119
width 783
height 1196
)
(PageSizeInfo
name "12,6\" x 19,2\""
type 527
width 1161
height 1769
name "Oficio 8.5x13"
type 120
width 783
height 1198
)
(PageSizeInfo
name "12,6\" x 18,5\""
type 528
width 1161
height 1704
)
(PageSizeInfo
name "13\" x 18\""
type 529
width 1198
name "12x18"
type 121
width 1105
height 1658
)
(PageSizeInfo
name "10\" x 14\""
type 16
width 921
height 1290
name "8K 273x394 mm"
type 139
width 990
height 1428
)
(PageSizeInfo
name "10\" x 15\""
type 546
width 921
height 1382
)
(PageSizeInfo
name "11\" x 15\""
type 539
width 1013
height 1382
)
(PageSizeInfo
name "SRA3 (320 x 450 mm)"
type 530
width 1161
height 1632
)
(PageSizeInfo
name "SRA4 (225 x 320 mm)"
type 531
width 816
height 1161
)
(PageSizeInfo
name "Format papier personnalisé"
type 256
width 783
height 1013
)
(PageSizeInfo
name "Custom Paper Size1(215,9 x 279,4 mm)"
type 257
width 783
height 1013
)
(PageSizeInfo
name "Custom Paper Size2(215,9 x 279,4 mm)"
type 258
width 783
height 1013
)
(PageSizeInfo
name "Custom Paper Size3(215,9 x 279,4 mm)"
type 259
width 783
height 1013
)
(PageSizeInfo
name "Custom Paper Size4(215,9 x 279,4 mm)"
type 260
width 783
height 1013
)
(PageSizeInfo
name "Custom Paper Size5(215,9 x 279,4 mm)"
type 261
width 783
height 1013
)
(PageSizeInfo
name "Custom Paper Size6(215,9 x 279,4 mm)"
type 262
width 783
height 1013
)
(PageSizeInfo
name "Custom Paper Size7(215,9 x 279,4 mm)"
type 263
width 783
height 1013
)
(PageSizeInfo
name "Custom Paper Size8(215,9 x 279,4 mm)"
type 264
width 783
height 1013
)
(PageSizeInfo
name "Custom Paper Size9(215,9 x 279,4 mm)"
type 265
width 783
height 1013
)
(PageSizeInfo
name "Custom Paper Size10(215,9 x 279,4 mm)"
type 266
width 783
height 1013
name "16K 197x273 mm"
type 140
width 714
height 990
)
]
exportPageSetupInfo (PageSetupInfo
@ -4291,7 +4148,7 @@ hdsWorkspaceLocation ""
relativeLibraryRootDir ""
vmLabelLatestDontAskAgain 0
vmLabelWorkspaceDontAskAgain 0
logWindowGeometry "600x200+2349+55"
logWindowGeometry "683x501+259+78"
diagramBrowserTabNo 0
showInsertPortHint 0
showContentFirstTime 0

6698
01-WaveformGenerator/Prefs/hds_user/v2019.2/hds_user_prefs.bak Normal file
View File

File diff suppressed because it is too large Load Diff

28
01-WaveformGenerator/WaveformGenerator/hdl/lowpass_entity.vhg Normal file
View File

@ -0,0 +1,28 @@
-- VHDL Entity WaveformGenerator.lowpass.symbol
--
-- Created:
-- by - remi.heredero.UNKNOWN (WE2330808)
-- at - 15:16:08 01.03.2024
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
ENTITY lowpass IS
GENERIC(
signalBitNb : positive := 16;
shiftBitNb : positive := 12
);
PORT(
lowpassOut : OUT unsigned (signalBitNb-1 DOWNTO 0);
clock : IN std_ulogic;
reset : IN std_ulogic;
lowpassIn : IN unsigned (signalBitNb-1 DOWNTO 0)
);
-- Declarations
END lowpass ;

15
01-WaveformGenerator/WaveformGenerator/hdl/lowpass_studentVersion.vhd
View File

@ -1,4 +1,17 @@
ARCHITECTURE studentVersion OF lowpass IS
signal accumulator: unsigned((signalBitNb-1)+shiftBitNb downto 0);
BEGIN
lowpassOut <= (others => '0');
process(clock)
begin
if reset = '1' then
accumulator <= (others => '0');
elsif rising_edge(clock) then
accumulator <= accumulator + resize(lowpassIn,signalBitNb+shiftBitNb) - shift_right(accumulator, shiftBitNb);
end if;
end process;
lowpassOut <= resize(shift_right(accumulator, shiftBitNb), signalBitNb);
END ARCHITECTURE studentVersion;

18
01-WaveformGenerator/WaveformGenerator/hdl/sawtoothGen_studentVersion.vhd
View File

@ -1,5 +1,21 @@
ARCHITECTURE studentVersion OF sawtoothGen IS
signal counter : unsigned(bitNb-1 downto 0);
BEGIN
sawtooth <= (others => '0');
count: process(clock, reset)
begin
if reset = '1' then
counter <= (others => '0');
elsif rising_edge(clock) then
if en = '1' then
counter <= counter + step;
end if;
end if;
end process count;
sawtooth <= counter;
END ARCHITECTURE studentVersion;

14
01-WaveformGenerator/WaveformGenerator/hdl/sawtoothToSquare_studentVersion.vhd
View File

@ -1,4 +1,16 @@
ARCHITECTURE studentVersion OF sawtoothToSquare IS
signal mySignal : unsigned(bitNb-1 downto 0);
constant constOf0 : unsigned(bitNb-2 downto 0) := (others => '0');
constant myConst : unsigned(bitNb-1 downto 0) := ('1' & constOf0);
BEGIN
square <= (others => '0');
convert: process(sawtooth)
begin
mySignal <= sawtooth AND myConst;
end process convert;
square <= (others => sawtooth(bitNb-1));
END ARCHITECTURE studentVersion;

16
01-WaveformGenerator/WaveformGenerator/hdl/sawtoothToTriangle_studentVersion.vhd
View File

@ -1,4 +1,18 @@
ARCHITECTURE studentVersion OF sawtoothToTriangle IS
signal mySignal : unsigned(bitNb-1 downto 0);
BEGIN
triangle <= (others => '0');
convert: process(sawtooth)
begin
if sawtooth(bitNb-1) = '1' then
mySignal <= NOT sawtooth;
else
mySignal <= sawtooth;
end if;
end process convert;
triangle <= shift_left(mySignal, 1);
END ARCHITECTURE studentVersion;

28
01-WaveformGenerator/WaveformGenerator/hdl/sawtoothgen_entity.vhg Normal file
View File

@ -0,0 +1,28 @@
-- VHDL Entity WaveformGenerator.sawtoothGen.symbol
--
-- Created:
-- by - francois.francois (Aphelia)
-- at - 08:02:49 03/11/19
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
ENTITY sawtoothGen IS
GENERIC(
bitNb : positive := 16
);
PORT(
sawtooth : OUT unsigned (bitNb-1 DOWNTO 0);
clock : IN std_ulogic;
reset : IN std_ulogic;
step : IN unsigned (bitNb-1 DOWNTO 0);
en : IN std_ulogic
);
-- Declarations
END sawtoothGen ;

25
01-WaveformGenerator/WaveformGenerator/hdl/sawtoothtosquare_entity.vhg Normal file
View File

@ -0,0 +1,25 @@
-- VHDL Entity WaveformGenerator.sawtoothToSquare.symbol
--
-- Created:
-- by - francois.francois (Aphelia)
-- at - 08:02:49 03/11/19
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
ENTITY sawtoothToSquare IS
GENERIC(
bitNb : positive := 16
);
PORT(
square : OUT unsigned (bitNb-1 DOWNTO 0);
sawtooth : IN unsigned (bitNb-1 DOWNTO 0)
);
-- Declarations
END sawtoothToSquare ;

25
01-WaveformGenerator/WaveformGenerator/hdl/sawtoothtotriangle_entity.vhg Normal file
View File

@ -0,0 +1,25 @@
-- VHDL Entity WaveformGenerator.sawtoothToTriangle.symbol
--
-- Created:
-- by - francois.francois (Aphelia)
-- at - 08:02:49 03/11/19
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
ENTITY sawtoothToTriangle IS
GENERIC(
bitNb : positive := 16
);
PORT(
triangle : OUT unsigned (bitNb-1 DOWNTO 0);
sawtooth : IN unsigned (bitNb-1 DOWNTO 0)
);
-- Declarations
END sawtoothToTriangle ;

35
01-WaveformGenerator/WaveformGenerator/hdl/triangleToPolygon_studentVersion.vhd
View File

@ -1,4 +1,37 @@
ARCHITECTURE studentVersion OF triangleToPolygon IS
signal mySignal : unsigned(bitNb downto 0);
constant aFullTriangle : unsigned(bitNb downto 0) := (others => '1');
signal bigTriangle: unsigned(bitNb downto 0);
signal oneOfHeight: unsigned(bitNb downto 0);
signal fiveOfHeight: unsigned(bitNb downto 0);
BEGIN
polygon <= (others => '0');
resizeTriangle: process(triangle)
begin
bigTriangle <= ('0' & triangle) + ('0' & shift_right(triangle, 1));
oneOfHeight <= shift_right(aFullTriangle, 3);
fiveOfHeight <= shift_right(aFullTriangle, 1) + shift_right(aFullTriangle, 3);
end process resizeTriangle;
convert: process(bigTriangle)
begin
if bigTriangle < oneOfHeight then
mySignal <= oneOfHeight;
elsif bigTriangle > fiveOfHeight then
mySignal <= fiveOfHeight;
else
mySignal <= bigTriangle;
end if ;
end process convert;
polygon <= resize(mySignal-oneOfHeight, bitNb);
END ARCHITECTURE studentVersion;

13
01-WaveformGenerator/WaveformGenerator/hdl/triangleToPolygon_studentVersion.vhd.bak Normal file
View File

@ -0,0 +1,13 @@
ARCHITECTURE studentVersion OF triangleToPolygon IS
signal mySignal : unsigned(bitNb downto 0);
BEGIN
convert: process(triangle)
begin
mySignal <= triangle + shift_left(triangle, 1);
end process convert;
polygon <= mySignal;
END ARCHITECTURE studentVersion;

25
01-WaveformGenerator/WaveformGenerator/hdl/triangletopolygon_entity.vhg Normal file
View File

@ -0,0 +1,25 @@
-- VHDL Entity WaveformGenerator.triangleToPolygon.symbol
--
-- Created:
-- by - francois.francois (Aphelia)
-- at - 08:02:49 03/11/19
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
ENTITY triangleToPolygon IS
GENERIC(
bitNb : positive := 16
);
PORT(
polygon : OUT unsigned (bitNb-1 DOWNTO 0);
triangle : IN unsigned (bitNb-1 DOWNTO 0)
);
-- Declarations
END triangleToPolygon ;

33
01-WaveformGenerator/WaveformGenerator/hdl/waveformgen_entity.vhg Normal file
View File

@ -0,0 +1,33 @@
-- VHDL Entity WaveformGenerator.waveformGen.symbol
--
-- Created:
-- by - francois.corthay.UNKNOWN (WEA20303)
-- at - 17:19:13 06.03.2019
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
ENTITY waveformGen IS
GENERIC(
phaseBitNb : positive := 16;
signalBitNb : positive := 16
);
PORT(
clock : IN std_ulogic;
en : IN std_ulogic;
reset : IN std_ulogic;
step : IN unsigned (phaseBitNb-1 DOWNTO 0);
polygon : OUT unsigned (signalBitNb-1 DOWNTO 0);
sawtooth : OUT unsigned (phaseBitNb-1 DOWNTO 0);
sine : OUT unsigned (signalBitNb-1 DOWNTO 0);
square : OUT unsigned (signalBitNb-1 DOWNTO 0);
triangle : OUT unsigned (signalBitNb-1 DOWNTO 0)
);
-- Declarations
END waveformGen ;

146
01-WaveformGenerator/WaveformGenerator/hdl/waveformgen_struct.vhg Normal file
View File

@ -0,0 +1,146 @@
--
-- VHDL Architecture WaveformGenerator.waveformGen.struct
--
-- Created:
-- by - remi.heredero.UNKNOWN (WE2330808)
-- at - 15:15:34 01.03.2024
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
LIBRARY WaveformGenerator;
ARCHITECTURE struct OF waveformGen IS
-- Architecture declarations
-- Internal signal declarations
-- Implicit buffer signal declarations
SIGNAL polygon_internal : unsigned (signalBitNb-1 DOWNTO 0);
SIGNAL sawtooth_internal : unsigned (phaseBitNb-1 DOWNTO 0);
SIGNAL triangle_internal : unsigned (signalBitNb-1 DOWNTO 0);
-- Component Declarations
COMPONENT lowpass
GENERIC (
signalBitNb : positive := 16;
shiftBitNb : positive := 6
);
PORT (
lowpassOut : OUT unsigned (signalBitNb-1 DOWNTO 0);
clock : IN std_ulogic ;
reset : IN std_ulogic ;
lowpassIn : IN unsigned (signalBitNb-1 DOWNTO 0)
);
END COMPONENT;
COMPONENT sawtoothGen
GENERIC (
bitNb : positive := 16
);
PORT (
sawtooth : OUT unsigned (bitNb-1 DOWNTO 0);
clock : IN std_ulogic ;
reset : IN std_ulogic ;
step : IN unsigned (bitNb-1 DOWNTO 0);
en : IN std_ulogic
);
END COMPONENT;
COMPONENT sawtoothToSquare
GENERIC (
bitNb : positive := 16
);
PORT (
square : OUT unsigned (bitNb-1 DOWNTO 0);
sawtooth : IN unsigned (bitNb-1 DOWNTO 0)
);
END COMPONENT;
COMPONENT sawtoothToTriangle
GENERIC (
bitNb : positive := 16
);
PORT (
triangle : OUT unsigned (bitNb-1 DOWNTO 0);
sawtooth : IN unsigned (bitNb-1 DOWNTO 0)
);
END COMPONENT;
COMPONENT triangleToPolygon
GENERIC (
bitNb : positive := 16
);
PORT (
polygon : OUT unsigned (bitNb-1 DOWNTO 0);
triangle : IN unsigned (bitNb-1 DOWNTO 0)
);
END COMPONENT;
-- Optional embedded configurations
-- pragma synthesis_off
FOR ALL : lowpass USE ENTITY WaveformGenerator.lowpass;
FOR ALL : sawtoothGen USE ENTITY WaveformGenerator.sawtoothGen;
FOR ALL : sawtoothToSquare USE ENTITY WaveformGenerator.sawtoothToSquare;
FOR ALL : sawtoothToTriangle USE ENTITY WaveformGenerator.sawtoothToTriangle;
FOR ALL : triangleToPolygon USE ENTITY WaveformGenerator.triangleToPolygon;
-- pragma synthesis_on
BEGIN
-- Instance port mappings.
I_lp : lowpass
GENERIC MAP (
signalBitNb => signalBitNb,
shiftBitNb => 10
)
PORT MAP (
lowpassOut => sine,
clock => clock,
reset => reset,
lowpassIn => polygon_internal
);
I_saw : sawtoothGen
GENERIC MAP (
bitNb => phaseBitNb
)
PORT MAP (
sawtooth => sawtooth_internal,
clock => clock,
reset => reset,
step => step,
en => en
);
I_square : sawtoothToSquare
GENERIC MAP (
bitNb => signalBitNb
)
PORT MAP (
square => square,
sawtooth => sawtooth_internal
);
I_tri : sawtoothToTriangle
GENERIC MAP (
bitNb => signalBitNb
)
PORT MAP (
triangle => triangle_internal,
sawtooth => sawtooth_internal
);
I_poly : triangleToPolygon
GENERIC MAP (
bitNb => signalBitNb
)
PORT MAP (
polygon => polygon_internal,
triangle => triangle_internal
);
-- Implicit buffered output assignments
polygon <= polygon_internal;
sawtooth <= sawtooth_internal;
triangle <= triangle_internal;
END struct;

BIN
01-WaveformGenerator/WaveformGenerator/hds/.cache.dat Normal file
View File

Binary file not shown.

27
01-WaveformGenerator/WaveformGenerator/hds/.xrf/lowpass_entity.xrf Normal file
View File

@ -0,0 +1,27 @@
DESIGN lowpass
VIEW symbol.sb
NO_GRAPHIC 0
DESIGN lowpass
VIEW symbol.sb
GRAPHIC 50,0 8 0
DESIGN lowpass
VIEW symbol.sb
GRAPHIC 13,0 13 1
DESIGN lowpass
VIEW symbol.sb
GRAPHIC 57,0 18 0
DESIGN lowpass
VIEW symbol.sb
GRAPHIC 52,0 19 0
DESIGN lowpass
VIEW symbol.sb
GRAPHIC 76,0 20 0
DESIGN lowpass
VIEW symbol.sb
GRAPHIC 83,0 21 0
DESIGN lowpass
VIEW symbol.sb
GRAPHIC 1,0 24 0
DESIGN lowpass
VIEW symbol.sb
GRAPHIC 1,0 25 0

30
01-WaveformGenerator/WaveformGenerator/hds/.xrf/sawtoothgen_entity.xrf Normal file
View File

@ -0,0 +1,30 @@
DESIGN sawtooth@gen
VIEW symbol.sb
NO_GRAPHIC 0
DESIGN sawtooth@gen
VIEW symbol.sb
GRAPHIC 50,0 8 0
DESIGN sawtooth@gen
VIEW symbol.sb
GRAPHIC 13,0 13 1
DESIGN sawtooth@gen
VIEW symbol.sb
GRAPHIC 57,0 17 0
DESIGN sawtooth@gen
VIEW symbol.sb
GRAPHIC 52,0 18 0
DESIGN sawtooth@gen
VIEW symbol.sb
GRAPHIC 76,0 19 0
DESIGN sawtooth@gen
VIEW symbol.sb
GRAPHIC 83,0 20 0
DESIGN sawtooth@gen
VIEW symbol.sb
GRAPHIC 89,0 21 0
DESIGN sawtooth@gen
VIEW symbol.sb
GRAPHIC 1,0 24 0
DESIGN sawtooth@gen
VIEW symbol.sb
GRAPHIC 1,0 25 0

21
01-WaveformGenerator/WaveformGenerator/hds/.xrf/sawtoothtosquare_entity.xrf Normal file
View File

@ -0,0 +1,21 @@
DESIGN sawtooth@to@square
VIEW symbol.sb
NO_GRAPHIC 0
DESIGN sawtooth@to@square
VIEW symbol.sb
GRAPHIC 50,0 8 0
DESIGN sawtooth@to@square
VIEW symbol.sb
GRAPHIC 13,0 13 1
DESIGN sawtooth@to@square
VIEW symbol.sb
GRAPHIC 57,0 17 0
DESIGN sawtooth@to@square
VIEW symbol.sb
GRAPHIC 83,0 18 0
DESIGN sawtooth@to@square
VIEW symbol.sb
GRAPHIC 1,0 21 0
DESIGN sawtooth@to@square
VIEW symbol.sb
GRAPHIC 1,0 22 0

21
01-WaveformGenerator/WaveformGenerator/hds/.xrf/sawtoothtotriangle_entity.xrf Normal file
View File

@ -0,0 +1,21 @@
DESIGN sawtooth@to@triangle
VIEW symbol.sb
NO_GRAPHIC 0
DESIGN sawtooth@to@triangle
VIEW symbol.sb
GRAPHIC 50,0 8 0
DESIGN sawtooth@to@triangle
VIEW symbol.sb
GRAPHIC 13,0 13 1
DESIGN sawtooth@to@triangle
VIEW symbol.sb
GRAPHIC 57,0 17 0
DESIGN sawtooth@to@triangle
VIEW symbol.sb
GRAPHIC 83,0 18 0
DESIGN sawtooth@to@triangle
VIEW symbol.sb
GRAPHIC 1,0 21 0
DESIGN sawtooth@to@triangle
VIEW symbol.sb
GRAPHIC 1,0 22 0

21
01-WaveformGenerator/WaveformGenerator/hds/.xrf/triangletopolygon_entity.xrf Normal file
View File

@ -0,0 +1,21 @@
DESIGN triangle@to@polygon
VIEW symbol.sb
NO_GRAPHIC 0
DESIGN triangle@to@polygon
VIEW symbol.sb
GRAPHIC 50,0 8 0
DESIGN triangle@to@polygon
VIEW symbol.sb
GRAPHIC 13,0 13 1
DESIGN triangle@to@polygon
VIEW symbol.sb
GRAPHIC 57,0 17 0
DESIGN triangle@to@polygon
VIEW symbol.sb
GRAPHIC 83,0 18 0
DESIGN triangle@to@polygon
VIEW symbol.sb
GRAPHIC 1,0 21 0
DESIGN triangle@to@polygon
VIEW symbol.sb
GRAPHIC 1,0 22 0

42
01-WaveformGenerator/WaveformGenerator/hds/.xrf/waveformgen_entity.xrf Normal file
View File

@ -0,0 +1,42 @@
DESIGN waveform@gen
VIEW symbol.sb
NO_GRAPHIC 0
DESIGN waveform@gen
VIEW symbol.sb
GRAPHIC 50,0 8 0
DESIGN waveform@gen
VIEW symbol.sb
GRAPHIC 13,0 13 1
DESIGN waveform@gen
VIEW symbol.sb
GRAPHIC 52,0 18 0
DESIGN waveform@gen
VIEW symbol.sb
GRAPHIC 123,0 19 0
DESIGN waveform@gen
VIEW symbol.sb
GRAPHIC 88,0 20 0
DESIGN waveform@gen
VIEW symbol.sb
GRAPHIC 113,0 21 0
DESIGN waveform@gen
VIEW symbol.sb
GRAPHIC 93,0 22 0
DESIGN waveform@gen
VIEW symbol.sb
GRAPHIC 98,0 23 0
DESIGN waveform@gen
VIEW symbol.sb
GRAPHIC 103,0 24 0
DESIGN waveform@gen
VIEW symbol.sb
GRAPHIC 108,0 25 0
DESIGN waveform@gen
VIEW symbol.sb
GRAPHIC 118,0 26 0
DESIGN waveform@gen
VIEW symbol.sb
GRAPHIC 1,0 29 0
DESIGN waveform@gen
VIEW symbol.sb
GRAPHIC 1,0 30 0

215
01-WaveformGenerator/WaveformGenerator/hds/.xrf/waveformgen_struct.xrf Normal file
View File

@ -0,0 +1,215 @@
DESIGN waveform@gen
VIEW struct.bd
NO_GRAPHIC 0
DESIGN waveform@gen
VIEW struct.bd
GRAPHIC 84,0 9 0
DESIGN waveform@gen
VIEW struct.bd
NO_GRAPHIC 12
DESIGN waveform@gen
VIEW struct.bd
GRAPHIC 0,0 15 2
DESIGN waveform@gen
VIEW struct.bd
NO_GRAPHIC 20
DESIGN waveform@gen
VIEW struct.bd
GRAPHIC 513,0 22 0
DESIGN waveform@gen
VIEW struct.bd
GRAPHIC 414,0 23 0
DESIGN waveform@gen
VIEW struct.bd
GRAPHIC 424,0 24 0
DESIGN waveform@gen
VIEW struct.bd
NO_GRAPHIC 26
LIBRARY WaveformGenerator
DESIGN lowpass
VIEW student@version
GRAPHIC 1036,0 28 0
DESIGN lowpass
VIEW symbol.sb
GRAPHIC 14,0 29 1
DESIGN lowpass
VIEW symbol.sb
GRAPHIC 57,0 34 0
DESIGN lowpass
VIEW symbol.sb
GRAPHIC 52,0 35 0
DESIGN lowpass
VIEW symbol.sb
GRAPHIC 76,0 36 0
DESIGN lowpass
VIEW symbol.sb
GRAPHIC 83,0 37 0
DESIGN waveform@gen
VIEW struct.bd
GRAPHIC 1227,0 40 0
DESIGN sawtooth@gen
VIEW symbol.sb
GRAPHIC 14,0 41 1
DESIGN sawtooth@gen
VIEW symbol.sb
GRAPHIC 57,0 45 0
DESIGN sawtooth@gen
VIEW symbol.sb
GRAPHIC 52,0 46 0
DESIGN sawtooth@gen
VIEW symbol.sb
GRAPHIC 76,0 47 0
DESIGN sawtooth@gen
VIEW symbol.sb
GRAPHIC 83,0 48 0
DESIGN sawtooth@gen
VIEW symbol.sb
GRAPHIC 89,0 49 0
DESIGN waveform@gen
VIEW struct.bd
GRAPHIC 916,0 52 0
DESIGN sawtooth@to@square
VIEW symbol.sb
GRAPHIC 14,0 53 1
DESIGN sawtooth@to@square
VIEW symbol.sb
GRAPHIC 57,0 57 0
DESIGN sawtooth@to@square
VIEW symbol.sb
GRAPHIC 83,0 58 0
DESIGN waveform@gen
VIEW struct.bd
GRAPHIC 977,0 61 0
DESIGN sawtooth@to@triangle
VIEW symbol.sb
GRAPHIC 14,0 62 1
DESIGN sawtooth@to@triangle
VIEW symbol.sb
GRAPHIC 57,0 66 0
DESIGN sawtooth@to@triangle
VIEW symbol.sb
GRAPHIC 83,0 67 0
DESIGN waveform@gen
VIEW struct.bd
GRAPHIC 1011,0 70 0
DESIGN triangle@to@polygon
VIEW symbol.sb
GRAPHIC 14,0 71 1
DESIGN triangle@to@polygon
VIEW symbol.sb
GRAPHIC 57,0 75 0
DESIGN triangle@to@polygon
VIEW symbol.sb
GRAPHIC 83,0 76 0
LIBRARY WaveformGenerator
DESIGN waveform@gen
VIEW struct.bd
NO_GRAPHIC 79
DESIGN waveform@gen
VIEW struct.bd
GRAPHIC 1036,0 82 0
DESIGN waveform@gen
VIEW struct.bd
GRAPHIC 1227,0 83 0
DESIGN waveform@gen
VIEW struct.bd
GRAPHIC 916,0 84 0
DESIGN waveform@gen
VIEW struct.bd
GRAPHIC 977,0 85 0
DESIGN waveform@gen
VIEW struct.bd
GRAPHIC 1011,0 86 0
DESIGN waveform@gen
VIEW struct.bd
NO_GRAPHIC 89
DESIGN waveform@gen
VIEW struct.bd
NO_GRAPHIC 91
DESIGN waveform@gen
VIEW struct.bd
GRAPHIC 1036,0 93 0
DESIGN waveform@gen
VIEW struct.bd
GRAPHIC 1043,0 94 1
DESIGN waveform@gen
VIEW struct.bd
GRAPHIC 562,0 99 0
DESIGN waveform@gen
VIEW struct.bd
GRAPHIC 184,0 100 0
DESIGN waveform@gen
VIEW struct.bd
GRAPHIC 192,0 101 0
DESIGN waveform@gen
VIEW struct.bd
GRAPHIC 513,0 102 0
DESIGN waveform@gen
VIEW struct.bd
GRAPHIC 1227,0 104 0
DESIGN waveform@gen
VIEW struct.bd
GRAPHIC 1234,0 105 1
DESIGN waveform@gen
VIEW struct.bd
GRAPHIC 414,0 109 0
DESIGN waveform@gen
VIEW struct.bd
GRAPHIC 15,0 110 0
DESIGN waveform@gen
VIEW struct.bd
GRAPHIC 237,0 111 0
DESIGN waveform@gen
VIEW struct.bd
GRAPHIC 319,0 112 0
DESIGN waveform@gen
VIEW struct.bd
GRAPHIC 719,0 113 0
DESIGN waveform@gen
VIEW struct.bd
GRAPHIC 916,0 115 0
DESIGN waveform@gen
VIEW struct.bd
GRAPHIC 923,0 116 1
DESIGN waveform@gen
VIEW struct.bd
GRAPHIC 480,0 120 0
DESIGN waveform@gen
VIEW struct.bd
GRAPHIC 414,0 121 0
DESIGN waveform@gen
VIEW struct.bd
GRAPHIC 977,0 123 0
DESIGN waveform@gen
VIEW struct.bd
GRAPHIC 984,0 124 1
DESIGN waveform@gen
VIEW struct.bd
GRAPHIC 424,0 128 0
DESIGN waveform@gen
VIEW struct.bd
GRAPHIC 472,0 129 0
DESIGN waveform@gen
VIEW struct.bd
GRAPHIC 1011,0 131 0
DESIGN waveform@gen
VIEW struct.bd
GRAPHIC 1018,0 132 1
DESIGN waveform@gen
VIEW struct.bd
GRAPHIC 513,0 136 0
DESIGN waveform@gen
VIEW struct.bd
GRAPHIC 424,0 137 0
DESIGN waveform@gen
VIEW struct.bd
GRAPHIC 513,0 141 0
DESIGN waveform@gen
VIEW struct.bd
GRAPHIC 414,0 142 0
DESIGN waveform@gen
VIEW struct.bd
GRAPHIC 424,0 143 0
DESIGN waveform@gen
VIEW struct.bd
NO_GRAPHIC 145

198
01-WaveformGenerator/WaveformGenerator/hds/lowpass/symbol.sb
View File

@ -16,8 +16,8 @@ libraryRefs [
"ieee"
]
)
version "26.1"
appVersion "2018.1 (Build 12)"
version "27.1"
appVersion "2019.2 (Build 5)"
model (Symbol
commonDM (CommonDM
ldm (LogicalDM
@ -118,17 +118,17 @@ sheetRow (SheetRow
headerVa (MVa
cellColor "49152,49152,49152"
fontColor "0,0,0"
font "courier,10,0"
font "Tahoma,10,0"
)
cellVa (MVa
cellColor "65535,65535,65535"
fontColor "0,0,0"
font "courier,10,0"
font "Tahoma,10,0"
)
groupVa (MVa
cellColor "39936,56832,65280"
fontColor "0,0,0"
font "courier,10,0"
font "Tahoma,10,0"
)
emptyMRCItem *19 (MRCItem
litem &1
@ -186,7 +186,7 @@ sheetCol (SheetCol
propVa (MVa
cellColor "0,49152,49152"
fontColor "0,0,0"
font "courier,10,0"
font "Tahoma,10,0"
textAngle 90
)
uid 91,0
@ -314,17 +314,17 @@ sheetRow (SheetRow
headerVa (MVa
cellColor "49152,49152,49152"
fontColor "0,0,0"
font "courier,10,0"
font "Tahoma,10,0"
)
cellVa (MVa
cellColor "65535,65535,65535"
fontColor "0,0,0"
font "courier,10,0"
font "Tahoma,10,0"
)
groupVa (MVa
cellColor "39936,56832,65280"
fontColor "0,0,0"
font "courier,10,0"
font "Tahoma,10,0"
)
emptyMRCItem *50 (MRCItem
litem &35
@ -370,7 +370,7 @@ sheetCol (SheetCol
propVa (MVa
cellColor "0,49152,49152"
fontColor "0,0,0"
font "courier,10,0"
font "Tahoma,10,0"
textAngle 90
)
uid 122,0
@ -439,23 +439,23 @@ value " "
)
(vvPair
variable "HDLDir"
value "/home/francois/Documents/HEVs/SEm/SEm_labs/VHDL/WaveformGenerator/Prefs/../WaveformGenerator/hdl"
value "C:\\Users\\remi.heredero\\GIT\\2024-sem-labs-herederoremi\\01-WaveformGenerator\\Prefs\\..\\WaveformGenerator\\hdl"
)
(vvPair
variable "HDSDir"
value "/home/francois/Documents/HEVs/SEm/SEm_labs/VHDL/WaveformGenerator/Prefs/../WaveformGenerator/hds"
value "C:\\Users\\remi.heredero\\GIT\\2024-sem-labs-herederoremi\\01-WaveformGenerator\\Prefs\\..\\WaveformGenerator\\hds"
)
(vvPair
variable "SideDataDesignDir"
value "/home/francois/Documents/HEVs/SEm/SEm_labs/VHDL/WaveformGenerator/Prefs/../WaveformGenerator/hds/lowpass/symbol.sb.info"
value "C:\\Users\\remi.heredero\\GIT\\2024-sem-labs-herederoremi\\01-WaveformGenerator\\Prefs\\..\\WaveformGenerator\\hds\\lowpass\\symbol.sb.info"
)
(vvPair
variable "SideDataUserDir"
value "/home/francois/Documents/HEVs/SEm/SEm_labs/VHDL/WaveformGenerator/Prefs/../WaveformGenerator/hds/lowpass/symbol.sb.user"
value "C:\\Users\\remi.heredero\\GIT\\2024-sem-labs-herederoremi\\01-WaveformGenerator\\Prefs\\..\\WaveformGenerator\\hds\\lowpass\\symbol.sb.user"
)
(vvPair
variable "SourceDir"
value "/home/francois/Documents/HEVs/SEm/SEm_labs/VHDL/WaveformGenerator/Prefs/../WaveformGenerator/hds"
value "C:\\Users\\remi.heredero\\GIT\\2024-sem-labs-herederoremi\\01-WaveformGenerator\\Prefs\\..\\WaveformGenerator\\hds"
)
(vvPair
variable "appl"
@ -479,27 +479,27 @@ value "%(unit)_%(view)_config"
)
(vvPair
variable "d"
value "/home/francois/Documents/HEVs/SEm/SEm_labs/VHDL/WaveformGenerator/Prefs/../WaveformGenerator/hds/lowpass"
value "C:\\Users\\remi.heredero\\GIT\\2024-sem-labs-herederoremi\\01-WaveformGenerator\\Prefs\\..\\WaveformGenerator\\hds\\lowpass"
)
(vvPair
variable "d_logical"
value "/home/francois/Documents/HEVs/SEm/SEm_labs/VHDL/WaveformGenerator/Prefs/../WaveformGenerator/hds/lowpass"
value "C:\\Users\\remi.heredero\\GIT\\2024-sem-labs-herederoremi\\01-WaveformGenerator\\Prefs\\..\\WaveformGenerator\\hds\\lowpass"
)
(vvPair
variable "date"
value "03/11/19"
value "01.03.2024"
)
(vvPair
variable "day"
value "Mon"
value "ven."
)
(vvPair
variable "day_long"
value "Monday"
value "vendredi"
)
(vvPair
variable "dd"
value "11"
value "01"
)
(vvPair
variable "designName"
@ -527,31 +527,31 @@ value "symbol"
)
(vvPair
variable "graphical_source_author"
value "francois"
value "remi.heredero"
)
(vvPair
variable "graphical_source_date"
value "03/11/19"
value "01.03.2024"
)
(vvPair
variable "graphical_source_group"
value "francois"
value "UNKNOWN"
)
(vvPair
variable "graphical_source_host"
value "Aphelia"
value "WE2330808"
)
(vvPair
variable "graphical_source_time"
value "08:02:49"
value "15:16:08"
)
(vvPair
variable "group"
value "francois"
value "UNKNOWN"
)
(vvPair
variable "host"
value "Aphelia"
value "WE2330808"
)
(vvPair
variable "language"
@ -587,19 +587,19 @@ value "lowpass"
)
(vvPair
variable "month"
value "Mar"
value "mars"
)
(vvPair
variable "month_long"
value "March"
value "mars"
)
(vvPair
variable "p"
value "/home/francois/Documents/HEVs/SEm/SEm_labs/VHDL/WaveformGenerator/Prefs/../WaveformGenerator/hds/lowpass/symbol.sb"
value "C:\\Users\\remi.heredero\\GIT\\2024-sem-labs-herederoremi\\01-WaveformGenerator\\Prefs\\..\\WaveformGenerator\\hds\\lowpass\\symbol.sb"
)
(vvPair
variable "p_logical"
value "/home/francois/Documents/HEVs/SEm/SEm_labs/VHDL/WaveformGenerator/Prefs/../WaveformGenerator/hds/lowpass/symbol.sb"
value "C:\\Users\\remi.heredero\\GIT\\2024-sem-labs-herederoremi\\01-WaveformGenerator\\Prefs\\..\\WaveformGenerator\\hds\\lowpass\\symbol.sb"
)
(vvPair
variable "package_name"
@ -607,7 +607,7 @@ value "<Undefined Variable>"
)
(vvPair
variable "project_name"
value "waveformGenerator"
value "hds"
)
(vvPair
variable "series"
@ -675,7 +675,7 @@ value "symbol"
)
(vvPair
variable "time"
value "08:02:49"
value "15:16:08"
)
(vvPair
variable "unit"
@ -683,11 +683,11 @@ value "lowpass"
)
(vvPair
variable "user"
value "francois"
value "remi.heredero"
)
(vvPair
variable "version"
value "2018.1 (Build 12)"
value "2019.2 (Build 5)"
)
(vvPair
variable "view"
@ -695,11 +695,11 @@ value "symbol"
)
(vvPair
variable "year"
value "2019"
value "2024"
)
(vvPair
variable "yy"
value "19"
value "24"
)
]
)
@ -728,7 +728,6 @@ stg "VerticalLayoutStrategy"
f (Text
uid 55,0
va (VaSet
font "courier,9,0"
)
xt "33000,17400,36400,18600"
st "clock"
@ -739,9 +738,9 @@ tm "CptPortNameMgr"
dt (MLText
uid 56,0
va (VaSet
font "courier,8,0"
font "Verdana,8,0"
)
xt "2000,11900,19000,12800"
xt "2000,11900,15400,12900"
st "clock : IN std_ulogic ;"
)
thePort (LogicalPort
@ -772,7 +771,6 @@ stg "RightVerticalLayoutStrategy"
f (Text
uid 60,0
va (VaSet
font "courier,9,0"
)
xt "39700,13400,47000,14600"
st "lowpassOut"
@ -784,9 +782,9 @@ tm "CptPortNameMgr"
dt (MLText
uid 61,0
va (VaSet
font "courier,8,0"
font "Verdana,8,0"
)
xt "2000,11000,30000,11900"
xt "2000,11000,28000,12000"
st "lowpassOut : OUT unsigned (signalBitNb-1 DOWNTO 0) ;"
)
thePort (LogicalPort
@ -819,7 +817,6 @@ stg "VerticalLayoutStrategy"
f (Text
uid 79,0
va (VaSet
font "courier,9,0"
)
xt "33000,19400,36300,20600"
st "reset"
@ -830,9 +827,9 @@ tm "CptPortNameMgr"
dt (MLText
uid 80,0
va (VaSet
font "courier,8,0"
font "Verdana,8,0"
)
xt "2000,12800,19000,13700"
xt "2000,12800,15400,13800"
st "reset : IN std_ulogic ;"
)
thePort (LogicalPort
@ -863,7 +860,6 @@ stg "VerticalLayoutStrategy"
f (Text
uid 86,0
va (VaSet
font "courier,9,0"
)
xt "33000,13400,38800,14600"
st "lowpassIn"
@ -874,9 +870,9 @@ tm "CptPortNameMgr"
dt (MLText
uid 87,0
va (VaSet
font "courier,8,0"
font "Verdana,8,0"
)
xt "2000,13700,29000,14600"
xt "2000,13700,26500,14700"
st "lowpassIn : IN unsigned (signalBitNb-1 DOWNTO 0)"
)
thePort (LogicalPort
@ -909,20 +905,20 @@ stg "VerticalLayoutStrategy"
first (Text
uid 11,0
va (VaSet
font "courier,9,1"
font "Verdana,9,1"
)
xt "32600,21800,41600,22700"
xt "32600,21800,44100,23000"
st "WaveformGenerator"
blo "32600,22500"
blo "32600,22800"
)
second (Text
uid 12,0
va (VaSet
font "courier,9,1"
font "Verdana,9,1"
)
xt "32600,22700,36100,23600"
xt "32600,23000,37200,24200"
st "lowpass"
blo "32600,23400"
blo "32600,24000"
)
)
gi *68 (GenericInterface
@ -933,13 +929,14 @@ uid 14,0
text (MLText
uid 15,0
va (VaSet
font "courier,8,0"
font "Verdana,8,0"
)
xt "32000,25600,45000,29200"
xt "32000,25600,43200,29600"
st "Generic Declarations
signalBitNb positive 16
shiftBitNb positive 12 "
shiftBitNb positive 12
"
)
header "Generic Declarations"
showHdrWhenContentsEmpty 1
@ -987,7 +984,7 @@ va (VaSet
fg "0,0,32768"
bg "0,0,32768"
)
xt "36200,48000,50600,49000"
xt "36200,48500,36200,48500"
st "
by %user on %dd %month %year
"
@ -1017,7 +1014,7 @@ va (VaSet
fg "0,0,32768"
bg "0,0,32768"
)
xt "53200,44000,56800,45000"
xt "53200,44500,53200,44500"
st "
Project:
"
@ -1047,7 +1044,7 @@ va (VaSet
fg "0,0,32768"
bg "0,0,32768"
)
xt "36200,46000,52400,47000"
xt "36200,46500,36200,46500"
st "
<enter diagram title here>
"
@ -1077,7 +1074,7 @@ va (VaSet
fg "0,0,32768"
bg "0,0,32768"
)
xt "32200,46000,35800,47000"
xt "32200,46500,32200,46500"
st "
Title:
"
@ -1107,7 +1104,7 @@ va (VaSet
fg "0,0,32768"
bg "0,0,32768"
)
xt "53200,45200,66400,46200"
xt "53200,45200,67300,46400"
st "
<enter comments here>
"
@ -1136,7 +1133,7 @@ va (VaSet
fg "0,0,32768"
bg "0,0,32768"
)
xt "57200,44000,72800,45000"
xt "57200,44500,57200,44500"
st "
<enter project name here>
"
@ -1165,7 +1162,7 @@ uid 38,0
va (VaSet
fg "32768,0,0"
)
xt "38000,44500,47000,45500"
xt "37350,44400,47650,45600"
st "
<company name>
"
@ -1196,7 +1193,7 @@ va (VaSet
fg "0,0,32768"
bg "0,0,32768"
)
xt "32200,47000,35200,48000"
xt "32200,47500,32200,47500"
st "
Path:
"
@ -1226,7 +1223,7 @@ va (VaSet
fg "0,0,32768"
bg "0,0,32768"
)
xt "32200,48000,35800,49000"
xt "32200,48500,32200,48500"
st "
Edited:
"
@ -1256,7 +1253,7 @@ va (VaSet
fg "0,0,32768"
bg "0,0,32768"
)
xt "36200,47000,52400,48000"
xt "36200,47500,36200,47500"
st "
%library/%unit/%view
"
@ -1300,9 +1297,9 @@ textVec [
*81 (Text
uid 49,0
va (VaSet
font "courier,8,1"
font "Verdana,8,1"
)
xt "0,0,5400,1000"
xt "0,0,6900,1000"
st "Package List"
blo "0,800"
)
@ -1310,7 +1307,7 @@ blo "0,800"
uid 50,0
va (VaSet
)
xt "0,1000,18600,4000"
xt "0,1000,17500,4600"
st "LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;"
@ -1318,17 +1315,19 @@ tm "PackageList"
)
]
)
windowSize "2,35,1387,985"
viewArea "-1070,-1070,74579,51352"
windowSize "2,35,1389,985"
viewArea "-1100,-1100,74235,50510"
cachedDiagramExtent "0,0,73000,49000"
pageSetupInfo (PageSetupInfo
ptrCmd ""
toPrinter 1
xMargin 49
yMargin 49
paperWidth 761
paperHeight 1077
windowsPaperWidth 761
windowsPaperHeight 1077
paperType "Letter (8.5\" x 11\")"
paperType "A4"
windowsPaperName "A4"
exportedDirectories [
"$HDS_PROJECT_DIR/HTMLExport"
@ -1350,9 +1349,8 @@ xt "0,0,15000,5000"
text (MLText
va (VaSet
fg "0,0,32768"
font "courier,9,0"
)
xt "200,200,2200,1100"
xt "200,200,3200,1400"
st "
Text
"
@ -1378,9 +1376,9 @@ autoResize 1
text (MLText
va (VaSet
fg "0,0,32768"
font "courier,8,0"
font "Verdana,8,0"
)
xt "450,2150,1450,3050"
xt "450,2150,1450,3150"
st "
Text
"
@ -1404,7 +1402,7 @@ title (TextAssociate
ps "TopLeftStrategy"
text (Text
va (VaSet
font "courier,9,1"
font "Verdana,9,1"
)
xt "1000,1000,4400,2200"
st "Panel0"
@ -1433,7 +1431,7 @@ ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
first (Text
va (VaSet
font "courier,9,1"
font "Verdana,9,1"
)
xt "22600,14800,27400,16000"
st "<library>"
@ -1441,7 +1439,7 @@ blo "22600,15800"
)
second (Text
va (VaSet
font "courier,9,1"
font "Verdana,9,1"
)
xt "22600,16000,25900,17200"
st "<cell>"
@ -1454,7 +1452,7 @@ matrix (Matrix
text (MLText
va (VaSet
isHidden 1
font "courier,8,0"
font "Verdana,8,0"
)
xt "0,12000,0,12000"
)
@ -1482,7 +1480,7 @@ ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
va (VaSet
font "courier,8,0"
font "Verdana,8,0"
)
xt "0,750,1500,1650"
st "In0"
@ -1492,7 +1490,7 @@ tm "CptPortNameMgr"
)
dt (MLText
va (VaSet
font "courier,8,0"
font "Verdana,8,0"
)
)
thePort (LogicalPort
@ -1520,7 +1518,7 @@ ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
va (VaSet
font "courier,8,0"
font "Verdana,8,0"
)
xt "0,750,3500,1650"
st "Buffer0"
@ -1530,7 +1528,7 @@ tm "CptPortNameMgr"
)
dt (MLText
va (VaSet
font "courier,8,0"
font "Verdana,8,0"
)
)
thePort (LogicalPort
@ -1550,44 +1548,44 @@ stg "SymDeclLayoutStrategy"
declLabel (Text
uid 2,0
va (VaSet
font "courier,8,1"
font "Verdana,8,1"
)
xt "0,9000,5400,10000"
xt "0,9000,7000,10000"
st "Declarations"
blo "0,9800"
)
portLabel (Text
uid 3,0
va (VaSet
font "courier,8,1"
font "Verdana,8,1"
)
xt "0,10000,2700,11000"
xt "0,10000,3400,11000"
st "Ports:"
blo "0,10800"
)
externalLabel (Text
uid 4,0
va (VaSet
font "courier,8,1"
font "Verdana,8,1"
)
xt "0,14600,2500,15500"
xt "0,14600,3000,15600"
st "User:"
blo "0,15300"
blo "0,15400"
)
internalLabel (Text
uid 6,0
va (VaSet
isHidden 1
font "courier,8,1"
font "Verdana,8,1"
)
xt "0,9000,5800,10000"
xt "0,9000,7600,10000"
st "Internal User:"
blo "0,9800"
)
externalText (MLText
uid 5,0
va (VaSet
font "courier,8,0"
font "Verdana,8,0"
)
xt "2000,15500,2000,15500"
tm "SyDeclarativeTextMgr"
@ -1596,12 +1594,12 @@ internalText (MLText
uid 7,0
va (VaSet
isHidden 1
font "courier,8,0"
font "Verdana,8,0"
)
xt "0,9000,0,9000"
tm "SyDeclarativeTextMgr"
)
)
lastUid 181,0
activeModelName "Symbol"
lastUid 227,0
activeModelName "Symbol:GEN"
)

1604
01-WaveformGenerator/WaveformGenerator/hds/lowpass/symbol.sb.bak Normal file
View File

File diff suppressed because it is too large Load Diff

75
01-WaveformGenerator/WaveformGenerator/hds/waveform@gen/struct.bd
View File

@ -68,7 +68,7 @@ value "signalBitNb"
(GiElement
name "shiftBitNb"
type "positive"
value "10"
value "5"
)
]
mwi 0
@ -105,23 +105,23 @@ value " "
)
(vvPair
variable "HDLDir"
value "C:\\dev\\sem-labs\\01-WaveformGenerator\\Prefs\\..\\WaveformGenerator\\hdl"
value "C:\\Users\\remi.heredero\\GIT\\2024-sem-labs-herederoremi\\01-WaveformGenerator\\Prefs\\..\\WaveformGenerator\\hdl"
)
(vvPair
variable "HDSDir"
value "C:\\dev\\sem-labs\\01-WaveformGenerator\\Prefs\\..\\WaveformGenerator\\hds"
value "C:\\Users\\remi.heredero\\GIT\\2024-sem-labs-herederoremi\\01-WaveformGenerator\\Prefs\\..\\WaveformGenerator\\hds"
)
(vvPair
variable "SideDataDesignDir"
value "C:\\dev\\sem-labs\\01-WaveformGenerator\\Prefs\\..\\WaveformGenerator\\hds\\waveform@gen\\struct.bd.info"
value "C:\\Users\\remi.heredero\\GIT\\2024-sem-labs-herederoremi\\01-WaveformGenerator\\Prefs\\..\\WaveformGenerator\\hds\\waveform@gen\\struct.bd.info"
)
(vvPair
variable "SideDataUserDir"
value "C:\\dev\\sem-labs\\01-WaveformGenerator\\Prefs\\..\\WaveformGenerator\\hds\\waveform@gen\\struct.bd.user"
value "C:\\Users\\remi.heredero\\GIT\\2024-sem-labs-herederoremi\\01-WaveformGenerator\\Prefs\\..\\WaveformGenerator\\hds\\waveform@gen\\struct.bd.user"
)
(vvPair
variable "SourceDir"
value "C:\\dev\\sem-labs\\01-WaveformGenerator\\Prefs\\..\\WaveformGenerator\\hds"
value "C:\\Users\\remi.heredero\\GIT\\2024-sem-labs-herederoremi\\01-WaveformGenerator\\Prefs\\..\\WaveformGenerator\\hds"
)
(vvPair
variable "appl"
@ -145,15 +145,15 @@ value "%(unit)_%(view)_config"
)
(vvPair
variable "d"
value "C:\\dev\\sem-labs\\01-WaveformGenerator\\Prefs\\..\\WaveformGenerator\\hds\\waveform@gen"
value "C:\\Users\\remi.heredero\\GIT\\2024-sem-labs-herederoremi\\01-WaveformGenerator\\Prefs\\..\\WaveformGenerator\\hds\\waveform@gen"
)
(vvPair
variable "d_logical"
value "C:\\dev\\sem-labs\\01-WaveformGenerator\\Prefs\\..\\WaveformGenerator\\hds\\waveformGen"
value "C:\\Users\\remi.heredero\\GIT\\2024-sem-labs-herederoremi\\01-WaveformGenerator\\Prefs\\..\\WaveformGenerator\\hds\\waveformGen"
)
(vvPair
variable "date"
value "28.04.2023"
value "01.03.2024"
)
(vvPair
variable "day"
@ -165,7 +165,7 @@ value "vendredi"
)
(vvPair
variable "dd"
value "28"
value "01"
)
(vvPair
variable "designName"
@ -193,11 +193,11 @@ value "struct"
)
(vvPair
variable "graphical_source_author"
value "axel.amand"
value "remi.heredero"
)
(vvPair
variable "graphical_source_date"
value "28.04.2023"
value "01.03.2024"
)
(vvPair
variable "graphical_source_group"
@ -205,11 +205,11 @@ value "UNKNOWN"
)
(vvPair
variable "graphical_source_host"
value "WE7860"
value "WE2330808"
)
(vvPair
variable "graphical_source_time"
value "14:40:08"
value "15:15:34"
)
(vvPair
variable "group"
@ -217,7 +217,7 @@ value "UNKNOWN"
)
(vvPair
variable "host"
value "WE7860"
value "WE2330808"
)
(vvPair
variable "language"
@ -245,7 +245,7 @@ value "U:\\SEm_curves\\Synthesis"
)
(vvPair
variable "mm"
value "04"
value "03"
)
(vvPair
variable "module_name"
@ -253,19 +253,19 @@ value "waveformGen"
)
(vvPair
variable "month"
value "avr."
value "mars"
)
(vvPair
variable "month_long"
value "avril"
value "mars"
)
(vvPair
variable "p"
value "C:\\dev\\sem-labs\\01-WaveformGenerator\\Prefs\\..\\WaveformGenerator\\hds\\waveform@gen\\struct.bd"
value "C:\\Users\\remi.heredero\\GIT\\2024-sem-labs-herederoremi\\01-WaveformGenerator\\Prefs\\..\\WaveformGenerator\\hds\\waveform@gen\\struct.bd"
)
(vvPair
variable "p_logical"
value "C:\\dev\\sem-labs\\01-WaveformGenerator\\Prefs\\..\\WaveformGenerator\\hds\\waveformGen\\struct.bd"
value "C:\\Users\\remi.heredero\\GIT\\2024-sem-labs-herederoremi\\01-WaveformGenerator\\Prefs\\..\\WaveformGenerator\\hds\\waveformGen\\struct.bd"
)
(vvPair
variable "package_name"
@ -341,7 +341,7 @@ value "struct"
)
(vvPair
variable "time"
value "14:40:08"
value "15:15:34"
)
(vvPair
variable "unit"
@ -349,7 +349,7 @@ value "waveformGen"
)
(vvPair
variable "user"
value "axel.amand"
value "remi.heredero"
)
(vvPair
variable "version"
@ -361,11 +361,11 @@ value "struct"
)
(vvPair
variable "year"
value "2023"
value "2024"
)
(vvPair
variable "yy"
value "23"
value "24"
)
]
)
@ -1726,9 +1726,9 @@ uid 1023,0
va (VaSet
font "Arial,9,0"
)
xt "81000,46400,83500,47300"
xt "81000,46400,83700,47600"
st "clock"
blo "81000,47100"
blo "81000,47300"
)
)
thePort (LogicalPort
@ -1761,10 +1761,10 @@ uid 1027,0
va (VaSet
font "Arial,9,0"
)
xt "89500,42400,95000,43300"
xt "89200,42400,95000,43600"
st "lowpassOut"
ju 2
blo "95000,43100"
blo "95000,43300"
)
)
thePort (LogicalPort
@ -1799,9 +1799,9 @@ uid 1031,0
va (VaSet
font "Arial,9,0"
)
xt "81000,48400,83500,49300"
xt "81000,48400,83600,49600"
st "reset"
blo "81000,49100"
blo "81000,49300"
)
)
thePort (LogicalPort
@ -1834,9 +1834,9 @@ uid 1035,0
va (VaSet
font "Arial,9,0"
)
xt "81000,42400,85500,43300"
xt "81000,42400,85600,43600"
st "lowpassIn"
blo "81000,43100"
blo "81000,43300"
)
)
thePort (LogicalPort
@ -1910,7 +1910,8 @@ va (VaSet
)
xt "80000,54600,102900,57000"
st "signalBitNb = signalBitNb ( positive )
shiftBitNb = 10 ( positive ) "
shiftBitNb = 5 ( positive )
"
)
header ""
)
@ -1923,7 +1924,7 @@ value "signalBitNb"
(GiElement
name "shiftBitNb"
type "positive"
value "10"
value "5"
)
]
)
@ -2954,8 +2955,8 @@ tm "BdCompilerDirectivesTextMgr"
]
associable 1
)
windowSize "-8,-8,1928,1048"
viewArea "-4571,-1604,138105,75916"
windowSize "0,0,1921,1056"
viewArea "-4600,-1600,137612,74000"
cachedDiagramExtent "-24700,0,129400,74000"
pageSetupInfo (PageSetupInfo
ptrCmd ""
@ -2979,7 +2980,7 @@ boundaryWidth 0
)
hasePageBreakOrigin 1
pageBreakOrigin "-3000,0"
lastUid 1289,0
lastUid 1316,0
defaultCommentText (CommentText
shape (Rectangle
layer 0

4462
01-WaveformGenerator/WaveformGenerator/hds/waveform@gen/struct.bd.bak Normal file
View File

File diff suppressed because it is too large Load Diff

15
01-WaveformGenerator/WaveformGenerator_test/hdl/waveformgen_tb_entity.vhg Normal file
View File

@ -0,0 +1,15 @@
-- VHDL Entity WaveformGenerator_test.waveformGen_tb.symbol
--
-- Created:
-- by - francois.corthay.UNKNOWN (WEA30906)
-- at - 14:48:16 25.02.2019
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5)
--
ENTITY waveformGen_tb IS
-- Declarations
END waveformGen_tb ;

119
01-WaveformGenerator/WaveformGenerator_test/hdl/waveformgen_tb_struct.vhg Normal file
View File

@ -0,0 +1,119 @@
--
-- VHDL Architecture WaveformGenerator_test.waveformGen_tb.struct
--
-- Created:
-- by - remi.heredero.UNKNOWN (WE2330808)
-- at - 15:12:57 01.03.2024
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.ALL;
LIBRARY WaveformGenerator;
LIBRARY WaveformGenerator_test;
ARCHITECTURE struct OF waveformGen_tb IS
-- Architecture declarations
constant bitNb: positive := 16;
constant signalBitNb: positive := 16;
constant phaseBitNb: positive := 16;
--constant clockFrequency: real := 60.0E6;
constant clockFrequency: real := 66.0E6;
-- Internal signal declarations
SIGNAL clock : std_ulogic;
SIGNAL en : std_ulogic;
SIGNAL polygon : unsigned(signalBitNb-1 DOWNTO 0);
SIGNAL reset : std_ulogic;
SIGNAL sawtooth : unsigned(phaseBitNb-1 DOWNTO 0);
SIGNAL sine : unsigned(signalBitNb-1 DOWNTO 0);
SIGNAL square : unsigned(signalBitNb-1 DOWNTO 0);
SIGNAL step : unsigned(bitNb-1 DOWNTO 0);
SIGNAL triangle : unsigned(signalBitNb-1 DOWNTO 0);
-- Component Declarations
COMPONENT waveformGen
GENERIC (
phaseBitNb : positive := 16;
signalBitNb : positive := 16
);
PORT (
clock : IN std_ulogic ;
en : IN std_ulogic ;
reset : IN std_ulogic ;
step : IN unsigned (phaseBitNb-1 DOWNTO 0);
polygon : OUT unsigned (signalBitNb-1 DOWNTO 0);
sawtooth : OUT unsigned (phaseBitNb-1 DOWNTO 0);
sine : OUT unsigned (signalBitNb-1 DOWNTO 0);
square : OUT unsigned (signalBitNb-1 DOWNTO 0);
triangle : OUT unsigned (signalBitNb-1 DOWNTO 0)
);
END COMPONENT;
COMPONENT waveformGen_tester
GENERIC (
bitNb : positive := 16;
clockFrequency : real := 60.0E6;
phaseBitNb : positive := 16;
signalBitNb : positive := 16
);
PORT (
polygon : IN unsigned (signalBitNb-1 DOWNTO 0);
sawtooth : IN unsigned (phaseBitNb-1 DOWNTO 0);
sine : IN unsigned (signalBitNb-1 DOWNTO 0);
square : IN unsigned (signalBitNb-1 DOWNTO 0);
triangle : IN unsigned (signalBitNb-1 DOWNTO 0);
clock : OUT std_ulogic ;
en : OUT std_ulogic ;
reset : OUT std_ulogic ;
step : OUT unsigned (bitNb-1 DOWNTO 0)
);
END COMPONENT;
-- Optional embedded configurations
-- pragma synthesis_off
FOR ALL : waveformGen USE ENTITY WaveformGenerator.waveformGen;
FOR ALL : waveformGen_tester USE ENTITY WaveformGenerator_test.waveformGen_tester;
-- pragma synthesis_on
BEGIN
-- Instance port mappings.
I_DUT : waveformGen
GENERIC MAP (
phaseBitNb => bitNb,
signalBitNb => bitNb
)
PORT MAP (
clock => clock,
en => en,
reset => reset,
step => step,
polygon => polygon,
sawtooth => sawtooth,
sine => sine,
square => square,
triangle => triangle
);
I_tb : waveformGen_tester
GENERIC MAP (
bitNb => bitNb,
clockFrequency => clockFrequency
)
PORT MAP (
polygon => polygon,
sawtooth => sawtooth,
sine => sine,
square => square,
triangle => triangle,
clock => clock,
en => en,
reset => reset,
step => step
);
END struct;

35
01-WaveformGenerator/WaveformGenerator_test/hdl/waveformgen_tester_entity.vhg Normal file
View File

@ -0,0 +1,35 @@
-- VHDL Entity WaveformGenerator_test.waveformGen_tester.interface
--
-- Created:
-- by - remi.heredero.UNKNOWN (WE2330808)
-- at - 14:26:40 01.03.2024
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.ALL;
ENTITY waveformGen_tester IS
GENERIC(
bitNb : positive := 16;
clockFrequency : real := 60.0E6;
phaseBitNb : positive := 16;
signalBitNb : positive := 16
);
PORT(
polygon : IN unsigned (signalBitNb-1 DOWNTO 0);
sawtooth : IN unsigned (phaseBitNb-1 DOWNTO 0);
sine : IN unsigned (signalBitNb-1 DOWNTO 0);
square : IN unsigned (signalBitNb-1 DOWNTO 0);
triangle : IN unsigned (signalBitNb-1 DOWNTO 0);
clock : OUT std_ulogic;
en : OUT std_ulogic;
reset : OUT std_ulogic;
step : OUT unsigned (bitNb-1 DOWNTO 0)
);
-- Declarations
END waveformGen_tester ;

BIN
01-WaveformGenerator/WaveformGenerator_test/hds/.cache.dat Normal file
View File

Binary file not shown.

12
01-WaveformGenerator/WaveformGenerator_test/hds/.xrf/waveformgen_tb_entity.xrf Normal file
View File

@ -0,0 +1,12 @@
DESIGN waveform@gen_tb
VIEW symbol.sb
NO_GRAPHIC 0
DESIGN waveform@gen_tb
VIEW symbol.sb
GRAPHIC 50,0 8 0
DESIGN waveform@gen_tb
VIEW symbol.sb
GRAPHIC 1,0 11 0
DESIGN waveform@gen_tb
VIEW symbol.sb
GRAPHIC 1,0 12 0

177
01-WaveformGenerator/WaveformGenerator_test/hds/.xrf/waveformgen_tb_struct.xrf Normal file
View File

@ -0,0 +1,177 @@
DESIGN waveform@gen_tb
VIEW struct.bd
NO_GRAPHIC 0
DESIGN waveform@gen_tb
VIEW struct.bd
GRAPHIC 142,0 9 0
DESIGN waveform@gen_tb
VIEW struct.bd
NO_GRAPHIC 12
DESIGN waveform@gen_tb
VIEW struct.bd
GRAPHIC 0,0 16 2
DESIGN waveform@gen_tb
VIEW struct.bd
GRAPHIC 1,0 19 0
DESIGN waveform@gen_tb
VIEW struct.bd
NO_GRAPHIC 19
DESIGN waveform@gen_tb
VIEW struct.bd
GRAPHIC 53,0 26 0
DESIGN waveform@gen_tb
VIEW struct.bd
GRAPHIC 700,0 27 0
DESIGN waveform@gen_tb
VIEW struct.bd
GRAPHIC 1355,0 28 0
DESIGN waveform@gen_tb
VIEW struct.bd
GRAPHIC 45,0 29 0
DESIGN waveform@gen_tb
VIEW struct.bd
GRAPHIC 1180,0 30 0
DESIGN waveform@gen_tb
VIEW struct.bd
GRAPHIC 1404,0 31 0
DESIGN waveform@gen_tb
VIEW struct.bd
GRAPHIC 1263,0 32 0
DESIGN waveform@gen_tb
VIEW struct.bd
GRAPHIC 594,0 33 0
DESIGN waveform@gen_tb
VIEW struct.bd
GRAPHIC 1308,0 34 0
DESIGN waveform@gen_tb
VIEW struct.bd
NO_GRAPHIC 35
DESIGN waveform@gen_tb
VIEW struct.bd
NO_GRAPHIC 36
LIBRARY WaveformGenerator
DESIGN waveform@gen
VIEW struct
GRAPHIC 954,0 38 0
DESIGN waveform@gen
VIEW symbol.sb
GRAPHIC 14,0 39 1
DESIGN waveform@gen
VIEW symbol.sb
GRAPHIC 52,0 44 0
DESIGN waveform@gen
VIEW symbol.sb
GRAPHIC 123,0 45 0
DESIGN waveform@gen
VIEW symbol.sb
GRAPHIC 88,0 46 0
DESIGN waveform@gen
VIEW symbol.sb
GRAPHIC 113,0 47 0
DESIGN waveform@gen
VIEW symbol.sb
GRAPHIC 93,0 48 0
DESIGN waveform@gen
VIEW symbol.sb
GRAPHIC 98,0 49 0
DESIGN waveform@gen
VIEW symbol.sb
GRAPHIC 103,0 50 0
DESIGN waveform@gen
VIEW symbol.sb
GRAPHIC 108,0 51 0
DESIGN waveform@gen
VIEW symbol.sb
GRAPHIC 118,0 52 0
LIBRARY WaveformGenerator_test
DESIGN waveform@gen_tester
VIEW test
GRAPHIC 421,0 55 0
DESIGN waveform@gen_tester
VIEW interface
GRAPHIC 14,0 56 1
DESIGN waveform@gen_tb
VIEW struct.bd
GRAPHIC 1357,0 63 0
DESIGN waveform@gen_tb
VIEW struct.bd
GRAPHIC 1182,0 64 0
DESIGN waveform@gen_tb
VIEW struct.bd
GRAPHIC 1406,0 65 0
DESIGN waveform@gen_tb
VIEW struct.bd
GRAPHIC 1265,0 66 0
DESIGN waveform@gen_tb
VIEW struct.bd
GRAPHIC 1310,0 67 0
DESIGN waveform@gen_tb
VIEW struct.bd
GRAPHIC 55,0 68 0
DESIGN waveform@gen_tb
VIEW struct.bd
GRAPHIC 702,0 69 0
DESIGN waveform@gen_tb
VIEW struct.bd
GRAPHIC 47,0 70 0
DESIGN waveform@gen_tb
VIEW struct.bd
GRAPHIC 596,0 71 0
LIBRARY WaveformGenerator_test
DESIGN waveform@gen_tb
VIEW struct.bd
NO_GRAPHIC 74
DESIGN waveform@gen_tb
VIEW struct.bd
GRAPHIC 954,0 77 0
DESIGN waveform@gen_tb
VIEW struct.bd
GRAPHIC 421,0 78 0
DESIGN waveform@gen_tb
VIEW struct.bd
NO_GRAPHIC 81
DESIGN waveform@gen_tb
VIEW struct.bd
NO_GRAPHIC 83
DESIGN waveform@gen_tb
VIEW struct.bd
GRAPHIC 954,0 85 0
DESIGN waveform@gen_tb
VIEW struct.bd
GRAPHIC 961,0 86 1
DESIGN waveform@gen_tb
VIEW struct.bd
GRAPHIC 55,0 91 0
DESIGN waveform@gen_tb
VIEW struct.bd
GRAPHIC 702,0 92 0
DESIGN waveform@gen_tb
VIEW struct.bd
GRAPHIC 47,0 93 0
DESIGN waveform@gen_tb
VIEW struct.bd
GRAPHIC 596,0 94 0
DESIGN waveform@gen_tb
VIEW struct.bd
GRAPHIC 1357,0 95 0
DESIGN waveform@gen_tb
VIEW struct.bd
GRAPHIC 1182,0 96 0
DESIGN waveform@gen_tb
VIEW struct.bd
GRAPHIC 1406,0 97 0
DESIGN waveform@gen_tb
VIEW struct.bd
GRAPHIC 1265,0 98 0
DESIGN waveform@gen_tb
VIEW struct.bd
GRAPHIC 1310,0 99 0
DESIGN waveform@gen_tb
VIEW struct.bd
GRAPHIC 421,0 101 0
DESIGN waveform@gen_tb
VIEW struct.bd
GRAPHIC 428,0 102 1
DESIGN waveform@gen_tb
VIEW struct.bd
NO_GRAPHIC 118

42
01-WaveformGenerator/WaveformGenerator_test/hds/.xrf/waveformgen_tester_entity.xrf Normal file
View File

@ -0,0 +1,42 @@
DESIGN waveform@gen_tester
VIEW interface
NO_GRAPHIC 0
DESIGN waveform@gen_tester
VIEW interface
GRAPHIC 18,0 8 0
DESIGN waveform@gen_tester
VIEW interface
GRAPHIC 13,0 13 1
DESIGN waveform@gen_tester
VIEW interface
GRAPHIC 1142,0 20 0
DESIGN waveform@gen_tester
VIEW interface
GRAPHIC 1152,0 21 0
DESIGN waveform@gen_tester
VIEW interface
GRAPHIC 1157,0 22 0
DESIGN waveform@gen_tester
VIEW interface
GRAPHIC 1162,0 23 0
DESIGN waveform@gen_tester
VIEW interface
GRAPHIC 1172,0 24 0
DESIGN waveform@gen_tester
VIEW interface
GRAPHIC 1132,0 25 0
DESIGN waveform@gen_tester
VIEW interface
GRAPHIC 1137,0 26 0
DESIGN waveform@gen_tester
VIEW interface
GRAPHIC 1147,0 27 0
DESIGN waveform@gen_tester
VIEW interface
GRAPHIC 1167,0 28 0
DESIGN waveform@gen_tester
VIEW interface
GRAPHIC 1,0 31 0
DESIGN waveform@gen_tester
VIEW interface
GRAPHIC 1,0 32 0

719
01-WaveformGenerator/WaveformGenerator_test/hds/waveform@gen_tb/struct.bd
View File

File diff suppressed because it is too large Load Diff

3261
01-WaveformGenerator/WaveformGenerator_test/hds/waveform@gen_tb/struct.bd.bak Normal file
View File

File diff suppressed because it is too large Load Diff

660
01-WaveformGenerator/WaveformGenerator_test/hds/waveform@gen_tester/interface
View File

File diff suppressed because it is too large Load Diff

1552
01-WaveformGenerator/WaveformGenerator_test/hds/waveform@gen_tester/interface.bak Normal file
View File

File diff suppressed because it is too large Load Diff

3
02-SplineInterpolator/Prefs/hds.hdp
View File

@ -1,11 +1,10 @@
[Concat]
[ModelSim]
SplineInterpolator = $SCRATCH_DIR/SplineInterpolator
SplineInterpolator_test = $SCRATCH_DIR/SplineInterpolator_test
WaveformGenerator = $SCRATCH_DIR/WaveformGenerator
WaveformGenerator_test = $SCRATCH_DIR/WaveformGenerator_test
[hdl]
ieee = $HDS_HOME/hdl_libs/ieee/hdl
ieee = $HDS_HOME\hdl_libs\ieee\hdl
SplineInterpolator = $HDS_PROJECT_DIR/../SplineInterpolator/hdl
SplineInterpolator_test = $HDS_PROJECT_DIR/../SplineInterpolator_test/hdl
std = $HDS_HOME/hdl_libs/std/hdl

55
02-SplineInterpolator/Prefs/hds_team/v2019.2/hds_team_prefs.bak Normal file
View File

@ -0,0 +1,55 @@
version "8.0"
RenoirTeamPreferences [
(BaseTeamPreferences
version "1.1"
verConcat 0
ttDGProps [
]
fcDGProps [
]
smDGProps [
]
asmDGProps [
]
bdDGProps [
]
syDGProps [
]
)
(VersionControlTeamPreferences
version "1.1"
VMPlugin ""
VMRepository "$HDS_HOME/examples/hds_scratch/hds_repository"
VMRcsHdsRepository "$HDS_HOME/examples/hds_scratch/hds_repository/%(library)/hds_vm"
VMRcsHdlRepository "$HDS_HOME/examples/hds_scratch/hds_repository/%(library)/hdl_vm"
VMCvsHdsRepository "$HDS_HOME/examples/hds_scratch/hds_repository/hds_vm"
VMCvsHdlRepository "$HDS_HOME/examples/hds_scratch/hds_repository/hdl_vm"
VMCVSmkIIHdsRepository "$HDS_HOME/examples/hds_scratch/hds_repository/hds_vm"
VMCVSmkIIHdlRepository "$HDS_HOME/examples/hds_scratch/hds_repository"
VMVssHdsRepository "$/hds_scratch/hds_repository/%(library)/hds_vm"
VMVssHdlRepository "$/hds_scratch/hds_repository/%(library)/hdl_vm"
VMDsHdsRepository "sync://<host_name>:<port>/hds_scratch/hds_repository/hds_vm"
VMDsHdlRepository "sync://<host_name>:<port>/hds_scratch/hds_repository/hdl_vm"
VMPvcsHdsRepository "$HDS_HOME/examples/hds_scratch/hds_repository/hds_vm"
VMPvcsHdlRepository "$HDS_HOME/examples/hds_scratch/hds_repository/hdl_vm"
VMSvnHdlRepository ""
VMDefaultView 1
VMCurrentDesignHierarchyOnly 0
VMUserData 1
VMGeneratedHDL 0
VMVerboseMode 0
VMAlwaysEmpty 0
VMSetTZ 1
VMSymbol 1
VMCurrentDesignHierarchy 0
VMMultipleRepositoryMode 0
VMSnapshotViewMode 0
backupNameClashes 1
clearCaseMaster 0
)
(CustomizeTeamPreferences
version "1.1"
FileTypes [
]
)
]

284
02-SplineInterpolator/Prefs/hds_user/v2019.2/hds_user_prefs
View File

@ -1280,6 +1280,8 @@ projectPaths [
"C:\\work\\repo\\edu\\sem\\labo\\solution\\sem_labs\\02-SplineInterpolator\\Prefs\\hds.hdp"
"C:\\work\\edu\\sem\\labo\\sem_labs\\02-SplineInterpolator\\Prefs\\hds.hdp"
"C:\\dev\\sem-labs\\02-SplineInterpolator\\Prefs\\hds.hdp"
"C:\\Users\\uadmin\\GIT\\2024-sem-labs-herederoremi\\02-SplineInterpolator\\Prefs\\hds.hdp"
"C:\\Users\\remi.heredero\\GIT\\2024-sem-labs-herederoremi\\02-SplineInterpolator\\Prefs\\hds.hdp"
]
libMappingsRootDir ""
teamLibMappingsRootDir ""
@ -1300,288 +1302,144 @@ exportedDirectories [
exportStdIncludeRefs 1
exportStdPackageRefs 1
)
printerName "\\\\vmenpprint1.hevs.ch\\VS-FOLLOWME-PRN"
printerName "\\\\vmenpprint1\\VS-ENP.23.N308-PRN"
pageSizes [
(PageSizeInfo
name "12\" x 18\""
type 512
width 1106
height 1658
name "Letter"
width 783
height 1013
)
(PageSizeInfo
name "11\" x 17\""
type 17
width 1013
height 1566
)
(PageSizeInfo
name "Legal (8,5\" x 14\")"
name "Legal"
type 5
width 783
height 1290
)
(PageSizeInfo
name "Letter (8,5\" x 11\")"
width 783
height 1013
)
(PageSizeInfo
name "Executive (7,25\"x10,5\")"
type 7
width 667
height 967
)
(PageSizeInfo
name "5,5\" x 8,5\""
name "Statement"
type 6
width 506
height 783
)
(PageSizeInfo
name "A3 (297 x 420 mm)"
name "Executive"
type 7
width 667
height 967
)
(PageSizeInfo
name "A3"
type 8
width 1077
height 1523
)
(PageSizeInfo
name "A4 (210 x 297 mm)"
name "A4"
type 9
width 761
height 1077
)
(PageSizeInfo
name "A5 (148 x 210 mm)"
name "A5"
type 11
width 538
width 536
height 761
)
(PageSizeInfo
name "A6 (105 x 148 mm)"
type 70
width 380
height 538
)
(PageSizeInfo
name "B4 JIS (257 x 364 mm)"
name "B4 (JIS)"
type 12
width 932
height 1320
)
(PageSizeInfo
name "B5 JIS (182 x 257 mm)"
name "B5 (JIS)"
type 13
width 660
height 932
)
(PageSizeInfo
name "B6 JIS (128 x 182 mm)"
type 88
width 464
height 660
name "11×17"
type 17
width 1013
height 1566
)
(PageSizeInfo
name "8\" x 13\""
type 518
width 737
height 1198
)
(PageSizeInfo
name "8,25\" x 13\""
type 519
width 760
height 1198
)
(PageSizeInfo
name "8,5\" x 13\""
type 14
width 783
height 1198
)
(PageSizeInfo
name "8.5\" x 13.4\""
type 551
width 783
height 1235
)
(PageSizeInfo
name "Com10 Env.(4,125\"x9,5\")"
name "Envelope #10"
type 20
width 380
width 379
height 875
)
(PageSizeInfo
name "Env.Monar.(3,875\"x7,5\")"
type 37
width 357
height 691
)
(PageSizeInfo
name "Env. DL (110 x 220 mm)"
name "Envelope DL"
type 27
width 399
height 798
)
(PageSizeInfo
name "Env. C6 (114 x 162 mm)"
type 31
width 413
height 587
)
(PageSizeInfo
name "Env. C5 (162 x 229 mm)"
name "Envelope C5"
type 28
width 587
height 830
)
(PageSizeInfo
name "8K (267 x 390 mm)"
type 520
width 968
height 1415
name "Envelope B5"
type 34
width 638
height 907
)
(PageSizeInfo
name "16K (195 x 267 mm)"
type 521
width 707
height 968
name "Envelope Monarch"
type 37
width 357
height 691
)
(PageSizeInfo
name "8,25\" x 14\""
type 522
width 760
height 1290
name "Japanese Postcard"
type 43
width 362
height 536
)
(PageSizeInfo
name "11\" x 14\""
type 524
width 1013
height 1290
name "A6"
type 70
width 380
height 536
)
(PageSizeInfo
name "13\" x 19,2\""
type 525
width 1198
height 1769
name "Double Japan Postcard Rotated"
type 82
width 536
height 725
)
(PageSizeInfo
name "13\" x 19\""
type 526
width 1198
height 1751
name "Executive (JIS)"
type 119
width 783
height 1196
)
(PageSizeInfo
name "12,6\" x 19,2\""
type 527
width 1161
height 1769
name "Oficio 8.5x13"
type 120
width 783
height 1198
)
(PageSizeInfo
name "12,6\" x 18,5\""
type 528
width 1161
height 1704
)
(PageSizeInfo
name "13\" x 18\""
type 529
width 1198
name "12x18"
type 121
width 1105
height 1658
)
(PageSizeInfo
name "10\" x 14\""
type 16
width 921
height 1290
name "8K 273x394 mm"
type 139
width 990
height 1428
)
(PageSizeInfo
name "10\" x 15\""
type 546
width 921
height 1382
)
(PageSizeInfo
name "11\" x 15\""
type 539
width 1013
height 1382
)
(PageSizeInfo
name "SRA3 (320 x 450 mm)"
type 530
width 1161
height 1632
)
(PageSizeInfo
name "SRA4 (225 x 320 mm)"
type 531
width 816
height 1161
)
(PageSizeInfo
name "Format papier personnalisé"
type 256
width 783
height 1013
)
(PageSizeInfo
name "Custom Paper Size1(215,9 x 279,4 mm)"
type 257
width 783
height 1013
)
(PageSizeInfo
name "Custom Paper Size2(215,9 x 279,4 mm)"
type 258
width 783
height 1013
)
(PageSizeInfo
name "Custom Paper Size3(215,9 x 279,4 mm)"
type 259
width 783
height 1013
)
(PageSizeInfo
name "Custom Paper Size4(215,9 x 279,4 mm)"
type 260
width 783
height 1013
)
(PageSizeInfo
name "Custom Paper Size5(215,9 x 279,4 mm)"
type 261
width 783
height 1013
)
(PageSizeInfo
name "Custom Paper Size6(215,9 x 279,4 mm)"
type 262
width 783
height 1013
)
(PageSizeInfo
name "Custom Paper Size7(215,9 x 279,4 mm)"
type 263
width 783
height 1013
)
(PageSizeInfo
name "Custom Paper Size8(215,9 x 279,4 mm)"
type 264
width 783
height 1013
)
(PageSizeInfo
name "Custom Paper Size9(215,9 x 279,4 mm)"
type 265
width 783
height 1013
)
(PageSizeInfo
name "Custom Paper Size10(215,9 x 279,4 mm)"
type 266
width 783
height 1013
name "16K 197x273 mm"
type 140
width 714
height 990
)
]
exportPageSetupInfo (PageSetupInfo
@ -4292,7 +4150,7 @@ hdsWorkspaceLocation ""
relativeLibraryRootDir ""
vmLabelLatestDontAskAgain 0
vmLabelWorkspaceDontAskAgain 0
logWindowGeometry "600x200+2349+55"
logWindowGeometry "600x573+406+95"
diagramBrowserTabNo 0
showInsertPortHint 0
showContentFirstTime 0
@ -6360,9 +6218,9 @@ size 180
]
displayHierarchy 0
xPos 0
yPos 14
width 1936
height 1056
yPos 4
width 892
height 982
activeSidePanelTab 2
activeLibraryTab 2
sidePanelSize 278

6700
02-SplineInterpolator/Prefs/hds_user/v2019.2/hds_user_prefs.bak Normal file
View File

File diff suppressed because it is too large Load Diff

36
02-SplineInterpolator/SplineInterpolator/hdl/interpolatorCalculatePolynom_studentVersion.vhd
View File

@ -1,4 +1,38 @@
ARCHITECTURE studentVersion OF interpolatorCalculatePolynom IS
subtype st is signed(coeffBitNb-1+oversamplingBitNb+8 DOWNTO 0);
signal x: st;
signal u: st;
signal v: st;
signal w: st;
BEGIN
sampleOut <= (others => '0');
process(clock, reset) begin
if reset = '1' then
x <= (others => '0');
u <= (others => '0');
v <= (others => '0');
w <= (others => '0');
elsif rising_edge(clock) then
if restartPolynom = '1' then
x <= resize(d, st'high+1) sla (oversamplingBitNb * 3 + 1);
u <= resize(a, st'high+1) + (resize(b, st'high+1) sla oversamplingBitNb) + (resize(c, st'high+1) sla (oversamplingBitNb*2));
v <= resize(6*a, v'length) + (resize(b, st'high+1) sla (oversamplingBitNb + 1));
w <= resize(6*a, w'length);
else
x <= x + u;
u <= u + v;
v <= v + w;
end if;
end if;
end process;
sampleOut <= resize(x sra (oversamplingBitNb * 3 + 1),signalBitNb);
END ARCHITECTURE studentVersion;

28
02-SplineInterpolator/SplineInterpolator/hdl/interpolatorCoefficients_studentVersion.vhd
View File

@ -1,7 +1,27 @@
ARCHITECTURE studentVersion OF interpolatorCoefficients IS
subtype sample is signed(bitNb-1 DOWNTO 0);
subtype coeff is signed(coeffBitNb-1 DOWNTO 0);
type samples_type is array (1 to 4) of coeff;
signal samples: samples_type;
BEGIN
a <= (others => '0');
b <= (others => '0');
c <= (others => '0');
d <= (others => '0');
-- a = - sample1 +3·sample2 -3·sample3 + sample4
-- b = 2·sample1 -5·sample2 +4·sample3 - sample4
-- c = - sample1 + sample3
-- d = sample2
process(sample1, sample2, sample3, sample4) begin
samples(1) <= resize(sample1, coeff'high+1);
samples(2) <= resize(sample2, coeff'high+1);
samples(3) <= resize(sample3, coeff'high+1);
samples(4) <= resize(sample4, coeff'high+1);
end process;
a <= samples(4) - samples(1) + resize( 3*(samples(2) - samples(3)), coeff'high+1);
b <= resize(2*samples(1), coeff'high+1) - resize(5*samples(2), coeff'high+1) + resize(4*samples(3), coeff'high+1) - samples(4);
c <= samples(3) - samples(1);
d <= samples(2);
END ARCHITECTURE studentVersion;

29
02-SplineInterpolator/SplineInterpolator/hdl/interpolatorShiftRegister_studentVersion.vhd
View File

@ -1,7 +1,28 @@
ARCHITECTURE studentVersion OF interpolatorShiftRegister IS
subtype sample_type is signed(sampleIn'range);
type samples_type is array (1 to 4) of sample_type;
signal samples: samples_type;
BEGIN
sample1 <= (others => '0');
sample2 <= (others => '0');
sample3 <= (others => '0');
sample4 <= (others => '0');
process(clock, reset) begin
if reset = '1' then
samples <= (others => (others => '0'));
elsif rising_edge(clock) then
if shiftSamples then
for i in samples_type'low to samples_type'high-1 loop
samples(i+1) <= samples(i);
end loop;
samples(1) <= sampleIn;
end if;
end if;
end process;
sample1 <= samples(4);
sample2 <= samples(3);
sample3 <= samples(2);
sample4 <= samples(1);
END ARCHITECTURE studentVersion;

25
02-SplineInterpolator/SplineInterpolator/hdl/interpolatorTrigger_studentVersion.vhd
View File

@ -1,4 +1,29 @@
ARCHITECTURE studentVersion OF interpolatorTrigger IS
signal counter : unsigned(counterBitNb-1 downto 0);
BEGIN
process(clock, reset)
begin
if reset = '1' then
counter <= (others => '0');
elsif rising_edge(clock) then
if en = '1' then
counter <= counter - 1;
end if;
end if;
end process;
process(counter)
begin
if counter = 0 then
triggerOut <= '1';
else
triggerOut <= '0';
end if;
end process;
END ARCHITECTURE studentVersion;

34
02-SplineInterpolator/SplineInterpolator/hdl/interpolatorcalculatepolynom_entity.vhg Normal file
View File

@ -0,0 +1,34 @@
-- VHDL Entity SplineInterpolator.interpolatorCalculatePolynom.symbol
--
-- Created:
-- by - francois.francois (Aphelia)
-- at - 13:00:14 02/19/19
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
ENTITY interpolatorCalculatePolynom IS
GENERIC(
signalBitNb : positive := 16;
coeffBitNb : positive := 16;
oversamplingBitNb : positive := 8
);
PORT(
clock : IN std_ulogic;
reset : IN std_ulogic;
restartPolynom : IN std_ulogic;
d : IN signed (coeffBitNb-1 DOWNTO 0);
sampleOut : OUT signed (signalBitNb-1 DOWNTO 0);
c : IN signed (coeffBitNb-1 DOWNTO 0);
b : IN signed (coeffBitNb-1 DOWNTO 0);
a : IN signed (coeffBitNb-1 DOWNTO 0);
en : IN std_ulogic
);
-- Declarations
END interpolatorCalculatePolynom ;

33
02-SplineInterpolator/SplineInterpolator/hdl/interpolatorcoefficients_entity.vhg Normal file
View File

@ -0,0 +1,33 @@
-- VHDL Entity SplineInterpolator.interpolatorCoefficients.symbol
--
-- Created:
-- by - francois.francois (Aphelia)
-- at - 13:00:20 02/19/19
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
ENTITY interpolatorCoefficients IS
GENERIC(
bitNb : positive := 16;
coeffBitNb : positive := 16
);
PORT(
sample1 : IN signed (bitNb-1 DOWNTO 0);
sample2 : IN signed (bitNb-1 DOWNTO 0);
sample3 : IN signed (bitNb-1 DOWNTO 0);
sample4 : IN signed (bitNb-1 DOWNTO 0);
a : OUT signed (coeffBitNb-1 DOWNTO 0);
b : OUT signed (coeffBitNb-1 DOWNTO 0);
c : OUT signed (coeffBitNb-1 DOWNTO 0);
d : OUT signed (coeffBitNb-1 DOWNTO 0);
interpolateLinear : IN std_ulogic
);
-- Declarations
END interpolatorCoefficients ;

31
02-SplineInterpolator/SplineInterpolator/hdl/interpolatorshiftregister_entity.vhg Normal file
View File

@ -0,0 +1,31 @@
-- VHDL Entity SplineInterpolator.interpolatorShiftRegister.symbol
--
-- Created:
-- by - francois.francois (Aphelia)
-- at - 13:00:24 02/19/19
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
ENTITY interpolatorShiftRegister IS
GENERIC(
signalBitNb : positive := 16
);
PORT(
clock : IN std_ulogic;
reset : IN std_ulogic;
shiftSamples : IN std_ulogic;
sampleIn : IN signed (signalBitNb-1 DOWNTO 0);
sample1 : OUT signed (signalBitNb-1 DOWNTO 0);
sample2 : OUT signed (signalBitNb-1 DOWNTO 0);
sample3 : OUT signed (signalBitNb-1 DOWNTO 0);
sample4 : OUT signed (signalBitNb-1 DOWNTO 0)
);
-- Declarations
END interpolatorShiftRegister ;

27
02-SplineInterpolator/SplineInterpolator/hdl/interpolatortrigger_entity.vhg Normal file
View File

@ -0,0 +1,27 @@
-- VHDL Entity SplineInterpolator.interpolatorTrigger.symbol
--
-- Created:
-- by - francois.francois (Aphelia)
-- at - 13:00:28 02/19/19
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
ENTITY interpolatorTrigger IS
GENERIC(
counterBitNb : positive := 4
);
PORT(
triggerOut : OUT std_ulogic;
clock : IN std_ulogic;
reset : IN std_ulogic;
en : IN std_ulogic
);
-- Declarations
END interpolatorTrigger ;

15
02-SplineInterpolator/SplineInterpolator/hdl/offsetToUnsigned_studentVersion.vhd
View File

@ -1,4 +1,17 @@
ARCHITECTURE studentVersion OF offsetToUnsigned IS
signal mySignal : unsigned(BitNb-1 downto 0);
signal const : unsigned(BitNb-1 downto 0) := (others => '1');
BEGIN
unsignedOut <= (others => '0');
process(signedIn) begin
if signedIn(signedIn'high) then
mySignal <= unsigned(signedIn) - (const srl 1);
else
mySignal <= unsigned(signedIn) + (const srl 1);
end if;
end process;
unsignedOut <= mySignal;
END ARCHITECTURE studentVersion;

25
02-SplineInterpolator/SplineInterpolator/hdl/offsettounsigned_entity.vhg Normal file
View File

@ -0,0 +1,25 @@
-- VHDL Entity SplineInterpolator.offsetToUnsigned.symbol
--
-- Created:
-- by - francois.francois (Aphelia)
-- at - 13:00:32 02/19/19
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
ENTITY offsetToUnsigned IS
GENERIC(
bitNb : positive := 16
);
PORT(
unsignedOut : OUT unsigned (bitNb-1 DOWNTO 0);
signedIn : IN signed (bitNb-1 DOWNTO 0)
);
-- Declarations
END offsetToUnsigned ;

26
02-SplineInterpolator/SplineInterpolator/hdl/resizer_entity.vhg Normal file
View File

@ -0,0 +1,26 @@
-- VHDL Entity SplineInterpolator.resizer.symbol
--
-- Created:
-- by - francois.francois (Aphelia)
-- at - 13:00:36 02/19/19
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
ENTITY resizer IS
GENERIC(
inputBitNb : positive := 16;
outputBitNb : positive := 16
);
PORT(
resizeOut : OUT unsigned (outputBitNb-1 DOWNTO 0);
resizeIn : IN unsigned (inputBitNb-1 DOWNTO 0)
);
-- Declarations
END resizer ;

22
02-SplineInterpolator/SplineInterpolator/hdl/resizer_studentVersion.vhd
View File

@ -1,4 +1,24 @@
ARCHITECTURE studentVersion OF resizer IS
signal mySignal : unsigned(outputBitNb-1 downto 0);
--------------------------------------------------------------------------------
BEGIN
resizeOut <= (others => '0');
INPUT_BIGGER: if inputBitNb >= outputBitNb generate
process(resizeIn)
begin
mySignal <= resize(shift_right(resizeIn, inputBitNb - outputBitNb), outputBitNb);
end process;
end generate INPUT_BIGGER;
OUTPUT_BIGGER: if inputBitNb <= outputBitNb generate
process(resizeIn)
begin
mySignal <= shift_left(resize(resizeIn, outputBitNb), outputBitNb - inputBitNb);
end process;
end generate OUTPUT_BIGGER;
resizeOut <= mySignal;
END ARCHITECTURE studentVersion;

28
02-SplineInterpolator/SplineInterpolator/hdl/sineTable_studentVersion.vhd
View File

@ -1,15 +1,25 @@
ARCHITECTURE studentVersion OF sineTable IS
signal phaseTableAddress : unsigned(tableAddressBitNb-1 downto 0);
signal phaseTableAddress2 : unsigned(tableAddressBitNb-1 downto 0);
signal quarterSine : signed(sine'range);
BEGIN
phaseTableAddress <= phase(phase'high-2 downto phase'high-2-tableAddressBitNb+1);
quarterTable: process(phaseTableAddress)
sequenceTable: process(phaseTableAddress)
begin
case to_integer(phaseTableAddress) is
if phase(phase'high-1) = '1' then
phaseTableAddress2 <= 8 - phaseTableAddress;
else
phaseTableAddress2 <= phaseTableAddress;
end if;
end process sequenceTable;
quarterTable: process(phaseTableAddress2)
begin
case to_integer(phaseTableAddress2) is
when 0 => quarterSine <= to_signed(16#0000#, quarterSine'length);
when 1 => quarterSine <= to_signed(16#18F9#, quarterSine'length);
when 2 => quarterSine <= to_signed(16#30FB#, quarterSine'length);
@ -20,8 +30,20 @@ BEGIN
when 7 => quarterSine <= to_signed(16#7D89#, quarterSine'length);
when others => quarterSine <= (others => '-');
end case;
if phaseTableAddress2 = 0 then
if phase(phase'high-1) = '1' then
quarterSine <= to_signed(16#7FFF#, quarterSine'length);
end if;
end if;
end process quarterTable;
sine <= (others => '0');
invert: process(quarterSine, phase(phase'high))
begin
if phase(phase'high) = '1' then
sine <= NOT quarterSine;
else
sine <= quarterSine;
end if;
end process invert;
END ARCHITECTURE studentVersion;

31
02-SplineInterpolator/SplineInterpolator/hdl/sinegen_entity.vhg Normal file
View File

@ -0,0 +1,31 @@
-- VHDL Entity SplineInterpolator.sineGen.symbol
--
-- Created:
-- by - francois.francois (Aphelia)
-- at - 13:00:40 02/19/19
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
ENTITY sineGen IS
GENERIC(
signalBitNb : positive := 16;
phaseBitNb : positive := 10
);
PORT(
clock : IN std_ulogic;
reset : IN std_ulogic;
step : IN unsigned (phaseBitNb-1 DOWNTO 0);
sawtooth : OUT unsigned (signalBitNb-1 DOWNTO 0);
sine : OUT unsigned (signalBitNb-1 DOWNTO 0);
square : OUT unsigned (signalBitNb-1 DOWNTO 0);
triangle : OUT unsigned (signalBitNb-1 DOWNTO 0)
);
-- Declarations
END sineGen ;

307
02-SplineInterpolator/SplineInterpolator/hdl/sinegen_struct.vhg Normal file
View File

@ -0,0 +1,307 @@
--
-- VHDL Architecture SplineInterpolator.sineGen.struct
--
-- Created:
-- by - axel.amand.UNKNOWN (WE7860)
-- at - 14:42:04 28.04.2023
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
LIBRARY SplineInterpolator;
LIBRARY WaveformGenerator;
ARCHITECTURE struct OF sineGen IS
-- Architecture declarations
constant tableAddressBitNb : positive := 3;
constant sampleCountBitNb : positive := phaseBitNb-2-tableAddressBitNb;
constant coeffBitNb : positive := signalBitNb+4;
-- Internal signal declarations
SIGNAL a : signed(coeffBitNb-1 DOWNTO 0);
SIGNAL b : signed(coeffBitNb-1 DOWNTO 0);
SIGNAL c : signed(coeffBitNb-1 DOWNTO 0);
SIGNAL d : signed(coeffBitNb-1 DOWNTO 0);
SIGNAL logic0 : std_ulogic;
SIGNAL logic1 : std_ulogic;
SIGNAL newPolynom : std_ulogic;
SIGNAL phase : unsigned(phaseBitNb-1 DOWNTO 0);
SIGNAL sample1 : signed(signalBitNb-1 DOWNTO 0);
SIGNAL sample2 : signed(signalBitNb-1 DOWNTO 0);
SIGNAL sample3 : signed(signalBitNb-1 DOWNTO 0);
SIGNAL sample4 : signed(signalBitNb-1 DOWNTO 0);
SIGNAL sineSamples : signed(signalBitNb-1 DOWNTO 0);
SIGNAL sineSigned : signed(signalBitNb-1 DOWNTO 0);
-- Implicit buffer signal declarations
SIGNAL sawtooth_internal : unsigned (signalBitNb-1 DOWNTO 0);
-- Component Declarations
COMPONENT interpolatorCalculatePolynom
GENERIC (
signalBitNb : positive := 16;
coeffBitNb : positive := 16;
oversamplingBitNb : positive := 8
);
PORT (
clock : IN std_ulogic ;
reset : IN std_ulogic ;
restartPolynom : IN std_ulogic ;
d : IN signed (coeffBitNb-1 DOWNTO 0);
sampleOut : OUT signed (signalBitNb-1 DOWNTO 0);
c : IN signed (coeffBitNb-1 DOWNTO 0);
b : IN signed (coeffBitNb-1 DOWNTO 0);
a : IN signed (coeffBitNb-1 DOWNTO 0);
en : IN std_ulogic
);
END COMPONENT;
COMPONENT interpolatorCoefficients
GENERIC (
bitNb : positive := 16;
coeffBitNb : positive := 16
);
PORT (
sample1 : IN signed (bitNb-1 DOWNTO 0);
sample2 : IN signed (bitNb-1 DOWNTO 0);
sample3 : IN signed (bitNb-1 DOWNTO 0);
sample4 : IN signed (bitNb-1 DOWNTO 0);
a : OUT signed (coeffBitNb-1 DOWNTO 0);
b : OUT signed (coeffBitNb-1 DOWNTO 0);
c : OUT signed (coeffBitNb-1 DOWNTO 0);
d : OUT signed (coeffBitNb-1 DOWNTO 0);
interpolateLinear : IN std_ulogic
);
END COMPONENT;
COMPONENT interpolatorShiftRegister
GENERIC (
signalBitNb : positive := 16
);
PORT (
clock : IN std_ulogic ;
reset : IN std_ulogic ;
shiftSamples : IN std_ulogic ;
sampleIn : IN signed (signalBitNb-1 DOWNTO 0);
sample1 : OUT signed (signalBitNb-1 DOWNTO 0);
sample2 : OUT signed (signalBitNb-1 DOWNTO 0);
sample3 : OUT signed (signalBitNb-1 DOWNTO 0);
sample4 : OUT signed (signalBitNb-1 DOWNTO 0)
);
END COMPONENT;
COMPONENT interpolatorTrigger
GENERIC (
counterBitNb : positive := 4
);
PORT (
triggerOut : OUT std_ulogic ;
clock : IN std_ulogic ;
reset : IN std_ulogic ;
en : IN std_ulogic
);
END COMPONENT;
COMPONENT offsetToUnsigned
GENERIC (
bitNb : positive := 16
);
PORT (
unsignedOut : OUT unsigned (bitNb-1 DOWNTO 0);
signedIn : IN signed (bitNb-1 DOWNTO 0)
);
END COMPONENT;
COMPONENT resizer
GENERIC (
inputBitNb : positive := 16;
outputBitNb : positive := 16
);
PORT (
resizeOut : OUT unsigned (outputBitNb-1 DOWNTO 0);
resizeIn : IN unsigned (inputBitNb-1 DOWNTO 0)
);
END COMPONENT;
COMPONENT sineTable
GENERIC (
inputBitNb : positive := 16;
outputBitNb : positive := 16;
tableAddressBitNb : positive := 3
);
PORT (
sine : OUT signed (outputBitNb-1 DOWNTO 0);
phase : IN unsigned (inputBitNb-1 DOWNTO 0)
);
END COMPONENT;
COMPONENT sawtoothGen
GENERIC (
bitNb : positive := 16
);
PORT (
sawtooth : OUT unsigned (bitNb-1 DOWNTO 0);
clock : IN std_ulogic ;
reset : IN std_ulogic ;
step : IN unsigned (bitNb-1 DOWNTO 0);
en : IN std_ulogic
);
END COMPONENT;
COMPONENT sawtoothToSquare
GENERIC (
bitNb : positive := 16
);
PORT (
square : OUT unsigned (bitNb-1 DOWNTO 0);
sawtooth : IN unsigned (bitNb-1 DOWNTO 0)
);
END COMPONENT;
COMPONENT sawtoothToTriangle
GENERIC (
bitNb : positive := 16
);
PORT (
triangle : OUT unsigned (bitNb-1 DOWNTO 0);
sawtooth : IN unsigned (bitNb-1 DOWNTO 0)
);
END COMPONENT;
-- Optional embedded configurations
-- pragma synthesis_off
FOR ALL : interpolatorCalculatePolynom USE ENTITY SplineInterpolator.interpolatorCalculatePolynom;
FOR ALL : interpolatorCoefficients USE ENTITY SplineInterpolator.interpolatorCoefficients;
FOR ALL : interpolatorShiftRegister USE ENTITY SplineInterpolator.interpolatorShiftRegister;
FOR ALL : interpolatorTrigger USE ENTITY SplineInterpolator.interpolatorTrigger;
FOR ALL : offsetToUnsigned USE ENTITY SplineInterpolator.offsetToUnsigned;
FOR ALL : resizer USE ENTITY SplineInterpolator.resizer;
FOR ALL : sawtoothGen USE ENTITY WaveformGenerator.sawtoothGen;
FOR ALL : sawtoothToSquare USE ENTITY WaveformGenerator.sawtoothToSquare;
FOR ALL : sawtoothToTriangle USE ENTITY WaveformGenerator.sawtoothToTriangle;
FOR ALL : sineTable USE ENTITY SplineInterpolator.sineTable;
-- pragma synthesis_on
BEGIN
-- Architecture concurrent statements
-- HDL Embedded Text Block 2 eb2
logic1 <= '1';
-- HDL Embedded Text Block 3 eb3
logic0 <= '0';
-- Instance port mappings.
I_spline : interpolatorCalculatePolynom
GENERIC MAP (
signalBitNb => signalBitNb,
coeffBitNb => coeffBitNb,
oversamplingBitNb => sampleCountBitNb
)
PORT MAP (
clock => clock,
reset => reset,
restartPolynom => newPolynom,
d => d,
sampleOut => sineSigned,
c => c,
b => b,
a => a,
en => logic1
);
I_coeffs : interpolatorCoefficients
GENERIC MAP (
bitNb => signalBitNb,
coeffBitNb => coeffBitNb
)
PORT MAP (
sample1 => sample1,
sample2 => sample2,
sample3 => sample3,
sample4 => sample4,
a => a,
b => b,
c => c,
d => d,
interpolateLinear => logic0
);
I_shReg : interpolatorShiftRegister
GENERIC MAP (
signalBitNb => signalBitNb
)
PORT MAP (
clock => clock,
reset => reset,
shiftSamples => newPolynom,
sampleIn => sineSamples,
sample1 => sample1,
sample2 => sample2,
sample3 => sample3,
sample4 => sample4
);
I_trig : interpolatorTrigger
GENERIC MAP (
counterBitNb => sampleCountBitNb
)
PORT MAP (
triggerOut => newPolynom,
clock => clock,
reset => reset,
en => logic1
);
I_unsigned : offsetToUnsigned
GENERIC MAP (
bitNb => signalBitNb
)
PORT MAP (
unsignedOut => sine,
signedIn => sineSigned
);
I_size : resizer
GENERIC MAP (
inputBitNb => phaseBitNb,
outputBitNb => signalBitNb
)
PORT MAP (
resizeOut => sawtooth_internal,
resizeIn => phase
);
I_sin : sineTable
GENERIC MAP (
inputBitNb => phaseBitNb,
outputBitNb => signalBitNb,
tableAddressBitNb => tableAddressBitNb
)
PORT MAP (
sine => sineSamples,
phase => phase
);
I_saw : sawtoothGen
GENERIC MAP (
bitNb => phaseBitNb
)
PORT MAP (
sawtooth => phase,
clock => clock,
reset => reset,
step => step,
en => logic1
);
I_square : sawtoothToSquare
GENERIC MAP (
bitNb => signalBitNb
)
PORT MAP (
square => square,
sawtooth => sawtooth_internal
);
I_tri : sawtoothToTriangle
GENERIC MAP (
bitNb => signalBitNb
)
PORT MAP (
triangle => triangle,
sawtooth => sawtooth_internal
);
-- Implicit buffered output assignments
sawtooth <= sawtooth_internal;
END struct;

27
02-SplineInterpolator/SplineInterpolator/hdl/sinetable_entity.vhg Normal file
View File

@ -0,0 +1,27 @@
-- VHDL Entity SplineInterpolator.sineTable.symbol
--
-- Created:
-- by - francois.francois (Aphelia)
-- at - 13:00:46 02/19/19
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
ENTITY sineTable IS
GENERIC(
inputBitNb : positive := 16;
outputBitNb : positive := 16;
tableAddressBitNb : positive := 3
);
PORT(
sine : OUT signed (outputBitNb-1 DOWNTO 0);
phase : IN unsigned (inputBitNb-1 DOWNTO 0)
);
-- Declarations
END sineTable ;

BIN
02-SplineInterpolator/SplineInterpolator/hds/.cache.dat Normal file
View File

Binary file not shown.

42
02-SplineInterpolator/SplineInterpolator/hds/.xrf/interpolatorcalculatepolynom_entity.xrf Normal file
View File

@ -0,0 +1,42 @@
DESIGN interpolator@calculate@polynom
VIEW symbol.sb
NO_GRAPHIC 0
DESIGN interpolator@calculate@polynom
VIEW symbol.sb
GRAPHIC 50,0 8 0
DESIGN interpolator@calculate@polynom
VIEW symbol.sb
GRAPHIC 13,0 13 1
DESIGN interpolator@calculate@polynom
VIEW symbol.sb
GRAPHIC 83,0 19 0
DESIGN interpolator@calculate@polynom
VIEW symbol.sb
GRAPHIC 89,0 20 0
DESIGN interpolator@calculate@polynom
VIEW symbol.sb
GRAPHIC 94,0 21 0
DESIGN interpolator@calculate@polynom
VIEW symbol.sb
GRAPHIC 104,0 22 0
DESIGN interpolator@calculate@polynom
VIEW symbol.sb
GRAPHIC 109,0 23 0
DESIGN interpolator@calculate@polynom
VIEW symbol.sb
GRAPHIC 125,0 24 0
DESIGN interpolator@calculate@polynom
VIEW symbol.sb
GRAPHIC 130,0 25 0
DESIGN interpolator@calculate@polynom
VIEW symbol.sb
GRAPHIC 135,0 26 0
DESIGN interpolator@calculate@polynom
VIEW symbol.sb
GRAPHIC 141,0 27 0
DESIGN interpolator@calculate@polynom
VIEW symbol.sb
GRAPHIC 1,0 30 0
DESIGN interpolator@calculate@polynom
VIEW symbol.sb
GRAPHIC 1,0 31 0

42
02-SplineInterpolator/SplineInterpolator/hds/.xrf/interpolatorcoefficients_entity.xrf Normal file
View File

@ -0,0 +1,42 @@
DESIGN interpolator@coefficients
VIEW symbol.sb
NO_GRAPHIC 0
DESIGN interpolator@coefficients
VIEW symbol.sb
GRAPHIC 50,0 8 0
DESIGN interpolator@coefficients
VIEW symbol.sb
GRAPHIC 13,0 13 1
DESIGN interpolator@coefficients
VIEW symbol.sb
GRAPHIC 104,0 18 0
DESIGN interpolator@coefficients
VIEW symbol.sb
GRAPHIC 109,0 19 0
DESIGN interpolator@coefficients
VIEW symbol.sb
GRAPHIC 114,0 20 0
DESIGN interpolator@coefficients
VIEW symbol.sb
GRAPHIC 119,0 21 0
DESIGN interpolator@coefficients
VIEW symbol.sb
GRAPHIC 125,0 22 0
DESIGN interpolator@coefficients
VIEW symbol.sb
GRAPHIC 130,0 23 0
DESIGN interpolator@coefficients
VIEW symbol.sb
GRAPHIC 140,0 24 0
DESIGN interpolator@coefficients
VIEW symbol.sb
GRAPHIC 135,0 25 0
DESIGN interpolator@coefficients
VIEW symbol.sb
GRAPHIC 149,0 26 0
DESIGN interpolator@coefficients
VIEW symbol.sb
GRAPHIC 1,0 29 0
DESIGN interpolator@coefficients
VIEW symbol.sb
GRAPHIC 1,0 30 0

39
02-SplineInterpolator/SplineInterpolator/hds/.xrf/interpolatorshiftregister_entity.xrf Normal file
View File

@ -0,0 +1,39 @@
DESIGN interpolator@shift@register
VIEW symbol.sb
NO_GRAPHIC 0
DESIGN interpolator@shift@register
VIEW symbol.sb
GRAPHIC 50,0 8 0
DESIGN interpolator@shift@register
VIEW symbol.sb
GRAPHIC 13,0 13 1
DESIGN interpolator@shift@register
VIEW symbol.sb
GRAPHIC 83,0 17 0
DESIGN interpolator@shift@register
VIEW symbol.sb
GRAPHIC 89,0 18 0
DESIGN interpolator@shift@register
VIEW symbol.sb
GRAPHIC 94,0 19 0
DESIGN interpolator@shift@register
VIEW symbol.sb
GRAPHIC 99,0 20 0
DESIGN interpolator@shift@register
VIEW symbol.sb
GRAPHIC 104,0 21 0
DESIGN interpolator@shift@register
VIEW symbol.sb
GRAPHIC 109,0 22 0
DESIGN interpolator@shift@register
VIEW symbol.sb
GRAPHIC 114,0 23 0
DESIGN interpolator@shift@register
VIEW symbol.sb
GRAPHIC 119,0 24 0
DESIGN interpolator@shift@register
VIEW symbol.sb
GRAPHIC 1,0 27 0
DESIGN interpolator@shift@register
VIEW symbol.sb
GRAPHIC 1,0 28 0

27
02-SplineInterpolator/SplineInterpolator/hds/.xrf/interpolatortrigger_entity.xrf Normal file
View File

@ -0,0 +1,27 @@
DESIGN interpolator@trigger
VIEW symbol.sb
NO_GRAPHIC 0
DESIGN interpolator@trigger
VIEW symbol.sb
GRAPHIC 50,0 8 0
DESIGN interpolator@trigger
VIEW symbol.sb
GRAPHIC 13,0 13 1
DESIGN interpolator@trigger
VIEW symbol.sb
GRAPHIC 57,0 17 0
DESIGN interpolator@trigger
VIEW symbol.sb
GRAPHIC 83,0 18 0
DESIGN interpolator@trigger
VIEW symbol.sb
GRAPHIC 89,0 19 0
DESIGN interpolator@trigger
VIEW symbol.sb
GRAPHIC 94,0 20 0
DESIGN interpolator@trigger
VIEW symbol.sb
GRAPHIC 1,0 23 0
DESIGN interpolator@trigger
VIEW symbol.sb
GRAPHIC 1,0 24 0

21
02-SplineInterpolator/SplineInterpolator/hds/.xrf/offsettounsigned_entity.xrf Normal file
View File

@ -0,0 +1,21 @@
DESIGN offset@to@unsigned
VIEW symbol.sb
NO_GRAPHIC 0
DESIGN offset@to@unsigned
VIEW symbol.sb
GRAPHIC 50,0 8 0
DESIGN offset@to@unsigned
VIEW symbol.sb
GRAPHIC 13,0 13 1
DESIGN offset@to@unsigned
VIEW symbol.sb
GRAPHIC 57,0 17 0
DESIGN offset@to@unsigned
VIEW symbol.sb
GRAPHIC 83,0 18 0
DESIGN offset@to@unsigned
VIEW symbol.sb
GRAPHIC 1,0 21 0
DESIGN offset@to@unsigned
VIEW symbol.sb
GRAPHIC 1,0 22 0

21
02-SplineInterpolator/SplineInterpolator/hds/.xrf/resizer_entity.xrf Normal file
View File

@ -0,0 +1,21 @@
DESIGN resizer
VIEW symbol.sb
NO_GRAPHIC 0
DESIGN resizer
VIEW symbol.sb
GRAPHIC 50,0 8 0
DESIGN resizer
VIEW symbol.sb
GRAPHIC 13,0 13 1
DESIGN resizer
VIEW symbol.sb
GRAPHIC 57,0 18 0
DESIGN resizer
VIEW symbol.sb
GRAPHIC 83,0 19 0
DESIGN resizer
VIEW symbol.sb
GRAPHIC 1,0 22 0
DESIGN resizer
VIEW symbol.sb
GRAPHIC 1,0 23 0

36
02-SplineInterpolator/SplineInterpolator/hds/.xrf/sinegen_entity.xrf Normal file
View File

@ -0,0 +1,36 @@
DESIGN sine@gen
VIEW symbol.sb
NO_GRAPHIC 0
DESIGN sine@gen
VIEW symbol.sb
GRAPHIC 50,0 8 0
DESIGN sine@gen
VIEW symbol.sb
GRAPHIC 13,0 13 1
DESIGN sine@gen
VIEW symbol.sb
GRAPHIC 52,0 18 0
DESIGN sine@gen
VIEW symbol.sb
GRAPHIC 88,0 19 0
DESIGN sine@gen
VIEW symbol.sb
GRAPHIC 128,0 20 0
DESIGN sine@gen
VIEW symbol.sb
GRAPHIC 98,0 21 0
DESIGN sine@gen
VIEW symbol.sb
GRAPHIC 103,0 22 0
DESIGN sine@gen
VIEW symbol.sb
GRAPHIC 108,0 23 0
DESIGN sine@gen
VIEW symbol.sb
GRAPHIC 118,0 24 0
DESIGN sine@gen
VIEW symbol.sb
GRAPHIC 1,0 27 0
DESIGN sine@gen
VIEW symbol.sb
GRAPHIC 1,0 28 0

519
02-SplineInterpolator/SplineInterpolator/hds/.xrf/sinegen_struct.xrf Normal file
View File

@ -0,0 +1,519 @@
DESIGN sine@gen
VIEW struct.bd
NO_GRAPHIC 0
DESIGN sine@gen
VIEW struct.bd
GRAPHIC 84,0 9 0
DESIGN sine@gen
VIEW struct.bd
NO_GRAPHIC 12
DESIGN sine@gen
VIEW struct.bd
GRAPHIC 0,0 16 2
DESIGN sine@gen
VIEW struct.bd
GRAPHIC 1,0 19 0
DESIGN sine@gen
VIEW struct.bd
NO_GRAPHIC 19
DESIGN sine@gen
VIEW struct.bd
GRAPHIC 1701,0 24 0
DESIGN sine@gen
VIEW struct.bd
GRAPHIC 1709,0 25 0
DESIGN sine@gen
VIEW struct.bd
GRAPHIC 1717,0 26 0
DESIGN sine@gen
VIEW struct.bd
GRAPHIC 1725,0 27 0
DESIGN sine@gen
VIEW struct.bd
GRAPHIC 2579,0 28 0
DESIGN sine@gen
VIEW struct.bd
GRAPHIC 2447,0 29 0
DESIGN sine@gen
VIEW struct.bd
GRAPHIC 1658,0 30 0
DESIGN sine@gen
VIEW struct.bd
GRAPHIC 726,0 31 0
DESIGN sine@gen
VIEW struct.bd
GRAPHIC 1277,0 32 0
DESIGN sine@gen
VIEW struct.bd
GRAPHIC 1285,0 33 0
DESIGN sine@gen
VIEW struct.bd
GRAPHIC 1293,0 34 0
DESIGN sine@gen
VIEW struct.bd
GRAPHIC 1301,0 35 0
DESIGN sine@gen
VIEW struct.bd
GRAPHIC 1102,0 36 0
DESIGN sine@gen
VIEW struct.bd
GRAPHIC 2227,0 37 0
DESIGN sine@gen
VIEW struct.bd
NO_GRAPHIC 38
DESIGN sine@gen
VIEW struct.bd
GRAPHIC 887,0 40 0
DESIGN sine@gen
VIEW struct.bd
NO_GRAPHIC 42
LIBRARY SplineInterpolator
DESIGN interpolator@calculate@polynom
VIEW student@version
GRAPHIC 3829,0 44 0
DESIGN interpolator@calculate@polynom
VIEW symbol.sb
GRAPHIC 14,0 45 1
DESIGN interpolator@calculate@polynom
VIEW symbol.sb
GRAPHIC 83,0 51 0
DESIGN interpolator@calculate@polynom
VIEW symbol.sb
GRAPHIC 89,0 52 0
DESIGN interpolator@calculate@polynom
VIEW symbol.sb
GRAPHIC 94,0 53 0
DESIGN interpolator@calculate@polynom
VIEW symbol.sb
GRAPHIC 104,0 54 0
DESIGN interpolator@calculate@polynom
VIEW symbol.sb
GRAPHIC 109,0 55 0
DESIGN interpolator@calculate@polynom
VIEW symbol.sb
GRAPHIC 125,0 56 0
DESIGN interpolator@calculate@polynom
VIEW symbol.sb
GRAPHIC 130,0 57 0
DESIGN interpolator@calculate@polynom
VIEW symbol.sb
GRAPHIC 135,0 58 0
DESIGN interpolator@calculate@polynom
VIEW symbol.sb
GRAPHIC 141,0 59 0
DESIGN sine@gen
VIEW struct.bd
GRAPHIC 3784,0 62 0
DESIGN interpolator@coefficients
VIEW symbol.sb
GRAPHIC 14,0 63 1
DESIGN interpolator@coefficients
VIEW symbol.sb
GRAPHIC 104,0 68 0
DESIGN interpolator@coefficients
VIEW symbol.sb
GRAPHIC 109,0 69 0
DESIGN interpolator@coefficients
VIEW symbol.sb
GRAPHIC 114,0 70 0
DESIGN interpolator@coefficients
VIEW symbol.sb
GRAPHIC 119,0 71 0
DESIGN interpolator@coefficients
VIEW symbol.sb
GRAPHIC 125,0 72 0
DESIGN interpolator@coefficients
VIEW symbol.sb
GRAPHIC 130,0 73 0
DESIGN interpolator@coefficients
VIEW symbol.sb
GRAPHIC 140,0 74 0
DESIGN interpolator@coefficients
VIEW symbol.sb
GRAPHIC 135,0 75 0
DESIGN interpolator@coefficients
VIEW symbol.sb
GRAPHIC 149,0 76 0
DESIGN sine@gen
VIEW struct.bd
GRAPHIC 3739,0 79 0
DESIGN interpolator@shift@register
VIEW symbol.sb
GRAPHIC 14,0 80 1
DESIGN interpolator@shift@register
VIEW symbol.sb
GRAPHIC 83,0 84 0
DESIGN interpolator@shift@register
VIEW symbol.sb
GRAPHIC 89,0 85 0
DESIGN interpolator@shift@register
VIEW symbol.sb
GRAPHIC 94,0 86 0
DESIGN interpolator@shift@register
VIEW symbol.sb
GRAPHIC 99,0 87 0
DESIGN interpolator@shift@register
VIEW symbol.sb
GRAPHIC 104,0 88 0
DESIGN interpolator@shift@register
VIEW symbol.sb
GRAPHIC 109,0 89 0
DESIGN interpolator@shift@register
VIEW symbol.sb
GRAPHIC 114,0 90 0
DESIGN interpolator@shift@register
VIEW symbol.sb
GRAPHIC 119,0 91 0
DESIGN sine@gen
VIEW struct.bd
GRAPHIC 3698,0 94 0
DESIGN interpolator@trigger
VIEW symbol.sb
GRAPHIC 14,0 95 1
DESIGN interpolator@trigger
VIEW symbol.sb
GRAPHIC 57,0 99 0
DESIGN interpolator@trigger
VIEW symbol.sb
GRAPHIC 83,0 100 0
DESIGN interpolator@trigger
VIEW symbol.sb
GRAPHIC 89,0 101 0
DESIGN interpolator@trigger
VIEW symbol.sb
GRAPHIC 94,0 102 0
DESIGN sine@gen
VIEW struct.bd
GRAPHIC 3846,0 105 0
DESIGN offset@to@unsigned
VIEW symbol.sb
GRAPHIC 14,0 106 1
DESIGN offset@to@unsigned
VIEW symbol.sb
GRAPHIC 57,0 110 0
DESIGN offset@to@unsigned
VIEW symbol.sb
GRAPHIC 83,0 111 0
DESIGN sine@gen
VIEW struct.bd
GRAPHIC 3584,0 114 0
DESIGN resizer
VIEW symbol.sb
GRAPHIC 14,0 115 1
DESIGN resizer
VIEW symbol.sb
GRAPHIC 57,0 120 0
DESIGN resizer
VIEW symbol.sb
GRAPHIC 83,0 121 0
DESIGN sine@gen
VIEW struct.bd
GRAPHIC 3601,0 124 0
DESIGN sine@table
VIEW symbol.sb
GRAPHIC 14,0 125 1
DESIGN sine@table
VIEW symbol.sb
GRAPHIC 57,0 131 0
DESIGN sine@table
VIEW symbol.sb
GRAPHIC 83,0 132 0
LIBRARY WaveformGenerator
DESIGN sawtooth@gen
VIEW student@version
GRAPHIC 3673,0 135 0
DESIGN sawtooth@gen
VIEW symbol.sb
GRAPHIC 14,0 136 1
DESIGN sawtooth@gen
VIEW symbol.sb
GRAPHIC 57,0 140 0
DESIGN sawtooth@gen
VIEW symbol.sb
GRAPHIC 52,0 141 0
DESIGN sawtooth@gen
VIEW symbol.sb
GRAPHIC 76,0 142 0
DESIGN sawtooth@gen
VIEW symbol.sb
GRAPHIC 83,0 143 0
DESIGN sawtooth@gen
VIEW symbol.sb
GRAPHIC 89,0 144 0
DESIGN sine@gen
VIEW struct.bd
GRAPHIC 2908,0 147 0
DESIGN sawtooth@to@square
VIEW symbol.sb
GRAPHIC 14,0 148 1
DESIGN sawtooth@to@square
VIEW symbol.sb
GRAPHIC 57,0 152 0
DESIGN sawtooth@to@square
VIEW symbol.sb
GRAPHIC 83,0 153 0
DESIGN sine@gen
VIEW struct.bd
GRAPHIC 2925,0 156 0
DESIGN sawtooth@to@triangle
VIEW symbol.sb
GRAPHIC 14,0 157 1
DESIGN sawtooth@to@triangle
VIEW symbol.sb
GRAPHIC 57,0 161 0
DESIGN sawtooth@to@triangle
VIEW symbol.sb
GRAPHIC 83,0 162 0
LIBRARY SplineInterpolator
DESIGN sine@gen
VIEW struct.bd
NO_GRAPHIC 165
DESIGN sine@gen
VIEW struct.bd
GRAPHIC 3829,0 168 0
DESIGN sine@gen
VIEW struct.bd
GRAPHIC 3784,0 169 0
DESIGN sine@gen
VIEW struct.bd
GRAPHIC 3739,0 170 0
DESIGN sine@gen
VIEW struct.bd
GRAPHIC 3698,0 171 0
DESIGN sine@gen
VIEW struct.bd
GRAPHIC 3846,0 172 0
DESIGN sine@gen
VIEW struct.bd
GRAPHIC 3584,0 173 0
DESIGN sine@gen
VIEW struct.bd
GRAPHIC 3673,0 174 0
DESIGN sine@gen
VIEW struct.bd
GRAPHIC 2908,0 175 0
DESIGN sine@gen
VIEW struct.bd
GRAPHIC 2925,0 176 0
DESIGN sine@gen
VIEW struct.bd
GRAPHIC 3601,0 177 0
DESIGN sine@gen
VIEW struct.bd
NO_GRAPHIC 180
DESIGN sine@gen
VIEW struct.bd
GRAPHIC 2375,0 183 0
DESIGN sine@gen
VIEW struct.bd
NO_GRAPHIC 185
DESIGN sine@gen
VIEW struct.bd
GRAPHIC 2562,0 186 0
DESIGN sine@gen
VIEW struct.bd
NO_GRAPHIC 188
DESIGN sine@gen
VIEW struct.bd
NO_GRAPHIC 189
DESIGN sine@gen
VIEW struct.bd
GRAPHIC 3829,0 191 0
DESIGN sine@gen
VIEW struct.bd
GRAPHIC 3836,0 192 1
DESIGN sine@gen
VIEW struct.bd
GRAPHIC 1814,0 198 0
DESIGN sine@gen
VIEW struct.bd
GRAPHIC 1822,0 199 0
DESIGN sine@gen
VIEW struct.bd
GRAPHIC 1830,0 200 0
DESIGN sine@gen
VIEW struct.bd
GRAPHIC 1727,0 201 0
DESIGN sine@gen
VIEW struct.bd
GRAPHIC 2219,0 202 0
DESIGN sine@gen
VIEW struct.bd
GRAPHIC 1719,0 203 0
DESIGN sine@gen
VIEW struct.bd
GRAPHIC 1711,0 204 0
DESIGN sine@gen
VIEW struct.bd
GRAPHIC 1703,0 205 0
DESIGN sine@gen
VIEW struct.bd
GRAPHIC 2394,0 206 0
DESIGN sine@gen
VIEW struct.bd
GRAPHIC 3784,0 208 0
DESIGN sine@gen
VIEW struct.bd
GRAPHIC 3791,0 209 1
DESIGN sine@gen
VIEW struct.bd
GRAPHIC 1279,0 214 0
DESIGN sine@gen
VIEW struct.bd
GRAPHIC 1287,0 215 0
DESIGN sine@gen
VIEW struct.bd
GRAPHIC 1295,0 216 0
DESIGN sine@gen
VIEW struct.bd
GRAPHIC 1303,0 217 0
DESIGN sine@gen
VIEW struct.bd
GRAPHIC 1703,0 218 0
DESIGN sine@gen
VIEW struct.bd
GRAPHIC 1711,0 219 0
DESIGN sine@gen
VIEW struct.bd
GRAPHIC 1719,0 220 0
DESIGN sine@gen
VIEW struct.bd
GRAPHIC 1727,0 221 0
DESIGN sine@gen
VIEW struct.bd
GRAPHIC 2571,0 222 0
DESIGN sine@gen
VIEW struct.bd
GRAPHIC 3739,0 224 0
DESIGN sine@gen
VIEW struct.bd
GRAPHIC 3746,0 225 1
DESIGN sine@gen
VIEW struct.bd
GRAPHIC 1228,0 229 0
DESIGN sine@gen
VIEW struct.bd
GRAPHIC 1220,0 230 0
DESIGN sine@gen
VIEW struct.bd
GRAPHIC 1106,0 231 0
DESIGN sine@gen
VIEW struct.bd
GRAPHIC 1096,0 232 0
DESIGN sine@gen
VIEW struct.bd
GRAPHIC 1279,0 233 0
DESIGN sine@gen
VIEW struct.bd
GRAPHIC 1287,0 234 0
DESIGN sine@gen
VIEW struct.bd
GRAPHIC 1295,0 235 0
DESIGN sine@gen
VIEW struct.bd
GRAPHIC 1303,0 236 0
DESIGN sine@gen
VIEW struct.bd
GRAPHIC 3698,0 238 0
DESIGN sine@gen
VIEW struct.bd
GRAPHIC 3705,0 239 1
DESIGN sine@gen
VIEW struct.bd
GRAPHIC 1106,0 243 0
DESIGN sine@gen
VIEW struct.bd
GRAPHIC 985,0 244 0
DESIGN sine@gen
VIEW struct.bd
GRAPHIC 993,0 245 0
DESIGN sine@gen
VIEW struct.bd
GRAPHIC 2386,0 246 0
DESIGN sine@gen
VIEW struct.bd
GRAPHIC 3846,0 248 0
DESIGN sine@gen
VIEW struct.bd
GRAPHIC 3853,0 249 1
DESIGN sine@gen
VIEW struct.bd
GRAPHIC 562,0 253 0
DESIGN sine@gen
VIEW struct.bd
GRAPHIC 2219,0 254 0
DESIGN sine@gen
VIEW struct.bd
GRAPHIC 3584,0 256 0
DESIGN sine@gen
VIEW struct.bd
GRAPHIC 3591,0 257 1
DESIGN sine@gen
VIEW struct.bd
GRAPHIC 601,0 262 0
DESIGN sine@gen
VIEW struct.bd
GRAPHIC 414,0 263 0
DESIGN sine@gen
VIEW struct.bd
GRAPHIC 3601,0 265 0
DESIGN sine@gen
VIEW struct.bd
GRAPHIC 3608,0 266 1
DESIGN sine@gen
VIEW struct.bd
GRAPHIC 1096,0 272 0
DESIGN sine@gen
VIEW struct.bd
GRAPHIC 472,0 273 0
DESIGN sine@gen
VIEW struct.bd
GRAPHIC 3673,0 275 0
DESIGN sine@gen
VIEW struct.bd
GRAPHIC 3680,0 276 1
DESIGN sine@gen
VIEW struct.bd
GRAPHIC 414,0 280 0
DESIGN sine@gen
VIEW struct.bd
GRAPHIC 15,0 281 0
DESIGN sine@gen
VIEW struct.bd
GRAPHIC 237,0 282 0
DESIGN sine@gen
VIEW struct.bd
GRAPHIC 781,0 283 0
DESIGN sine@gen
VIEW struct.bd
GRAPHIC 2449,0 284 0
DESIGN sine@gen
VIEW struct.bd
GRAPHIC 2908,0 286 0
DESIGN sine@gen
VIEW struct.bd
GRAPHIC 2915,0 287 1
DESIGN sine@gen
VIEW struct.bd
GRAPHIC 480,0 291 0
DESIGN sine@gen
VIEW struct.bd
GRAPHIC 887,0 292 0
DESIGN sine@gen
VIEW struct.bd
GRAPHIC 2925,0 294 0
DESIGN sine@gen
VIEW struct.bd
GRAPHIC 2932,0 295 1
DESIGN sine@gen
VIEW struct.bd
GRAPHIC 424,0 299 0
DESIGN sine@gen
VIEW struct.bd
GRAPHIC 858,0 300 0
DESIGN sine@gen
VIEW struct.bd
GRAPHIC 887,0 304 0
DESIGN sine@gen
VIEW struct.bd
NO_GRAPHIC 306

21
02-SplineInterpolator/SplineInterpolator/hds/.xrf/sinetable_entity.xrf Normal file
View File

@ -0,0 +1,21 @@
DESIGN sine@table
VIEW symbol.sb
NO_GRAPHIC 0
DESIGN sine@table
VIEW symbol.sb
GRAPHIC 50,0 8 0
DESIGN sine@table
VIEW symbol.sb
GRAPHIC 13,0 13 1
DESIGN sine@table
VIEW symbol.sb
GRAPHIC 57,0 19 0
DESIGN sine@table
VIEW symbol.sb
GRAPHIC 83,0 20 0
DESIGN sine@table
VIEW symbol.sb
GRAPHIC 1,0 23 0
DESIGN sine@table
VIEW symbol.sb
GRAPHIC 1,0 24 0

15
02-SplineInterpolator/SplineInterpolator_test/hdl/sinegen_tb_entity.vhg Normal file
View File

@ -0,0 +1,15 @@
-- VHDL Entity SplineInterpolator_test.sineGen_tb.symbol
--
-- Created:
-- by - francois.francois (Aphelia)
-- at - 13:00:04 02/19/19
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5)
--
ENTITY sineGen_tb IS
-- Declarations
END sineGen_tb ;

108
02-SplineInterpolator/SplineInterpolator_test/hdl/sinegen_tb_struct.vhg Normal file
View File

@ -0,0 +1,108 @@
--
-- VHDL Architecture SplineInterpolator_test.sineGen_tb.struct
--
-- Created:
-- by - axel.amand.UNKNOWN (WE7860)
-- at - 14:41:39 28.04.2023
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.ALL;
LIBRARY SplineInterpolator;
LIBRARY SplineInterpolator_test;
ARCHITECTURE struct OF sineGen_tb IS
-- Architecture declarations
constant signalBitNb: positive := 16;
constant phaseBitNb: positive := 10;
constant clockFrequency: real := 60.0E6;
--constant clockFrequency: real := 66.0E6;
-- Internal signal declarations
SIGNAL clock : std_ulogic;
SIGNAL reset : std_ulogic;
SIGNAL sawtooth : unsigned(signalBitNb-1 DOWNTO 0);
SIGNAL sine : unsigned(signalBitNb-1 DOWNTO 0);
SIGNAL square : unsigned(signalBitNb-1 DOWNTO 0);
SIGNAL step : unsigned(phaseBitNb-1 DOWNTO 0);
SIGNAL triangle : unsigned(signalBitNb-1 DOWNTO 0);
-- Component Declarations
COMPONENT sineGen
GENERIC (
signalBitNb : positive := 16;
phaseBitNb : positive := 10
);
PORT (
clock : IN std_ulogic ;
reset : IN std_ulogic ;
step : IN unsigned (phaseBitNb-1 DOWNTO 0);
sawtooth : OUT unsigned (signalBitNb-1 DOWNTO 0);
sine : OUT unsigned (signalBitNb-1 DOWNTO 0);
square : OUT unsigned (signalBitNb-1 DOWNTO 0);
triangle : OUT unsigned (signalBitNb-1 DOWNTO 0)
);
END COMPONENT;
COMPONENT sineGen_tester
GENERIC (
signalBitNb : positive := 16;
phaseBitNb : positive := 10;
clockFrequency : real := 60.0E6
);
PORT (
sawtooth : IN unsigned (signalBitNb-1 DOWNTO 0);
sine : IN unsigned (signalBitNb-1 DOWNTO 0);
square : IN unsigned (signalBitNb-1 DOWNTO 0);
triangle : IN unsigned (signalBitNb-1 DOWNTO 0);
clock : OUT std_ulogic ;
reset : OUT std_ulogic ;
step : OUT unsigned (phaseBitNb-1 DOWNTO 0)
);
END COMPONENT;
-- Optional embedded configurations
-- pragma synthesis_off
FOR ALL : sineGen USE ENTITY SplineInterpolator.sineGen;
FOR ALL : sineGen_tester USE ENTITY SplineInterpolator_test.sineGen_tester;
-- pragma synthesis_on
BEGIN
-- Instance port mappings.
I_DUT : sineGen
GENERIC MAP (
signalBitNb => signalBitNb,
phaseBitNb => phaseBitNb
)
PORT MAP (
clock => clock,
reset => reset,
step => step,
sawtooth => sawtooth,
sine => sine,
square => square,
triangle => triangle
);
I_tb : sineGen_tester
GENERIC MAP (
signalBitNb => signalBitNb,
phaseBitNb => phaseBitNb,
clockFrequency => clockFrequency
)
PORT MAP (
sawtooth => sawtooth,
sine => sine,
square => square,
triangle => triangle,
clock => clock,
reset => reset,
step => step
);
END struct;

32
02-SplineInterpolator/SplineInterpolator_test/hdl/sinegen_tester_entity.vhg Normal file
View File

@ -0,0 +1,32 @@
-- VHDL Entity SplineInterpolator_test.sineGen_tester.interface
--
-- Created:
-- by - axel.amand.UNKNOWN (WE7860)
-- at - 14:41:39 28.04.2023
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.ALL;
ENTITY sineGen_tester IS
GENERIC(
signalBitNb : positive := 16;
phaseBitNb : positive := 10;
clockFrequency : real := 60.0E6
);
PORT(
sawtooth : IN unsigned (signalBitNb-1 DOWNTO 0);
sine : IN unsigned (signalBitNb-1 DOWNTO 0);
square : IN unsigned (signalBitNb-1 DOWNTO 0);
triangle : IN unsigned (signalBitNb-1 DOWNTO 0);
clock : OUT std_ulogic;
reset : OUT std_ulogic;
step : OUT unsigned (phaseBitNb-1 DOWNTO 0)
);
-- Declarations
END sineGen_tester ;

BIN
02-SplineInterpolator/SplineInterpolator_test/hds/.cache.dat Normal file
View File

Binary file not shown.

12
02-SplineInterpolator/SplineInterpolator_test/hds/.xrf/sinegen_tb_entity.xrf Normal file
View File

@ -0,0 +1,12 @@
DESIGN sine@gen_tb
VIEW symbol.sb
NO_GRAPHIC 0
DESIGN sine@gen_tb
VIEW symbol.sb
GRAPHIC 50,0 8 0
DESIGN sine@gen_tb
VIEW symbol.sb
GRAPHIC 1,0 11 0
DESIGN sine@gen_tb
VIEW symbol.sb
GRAPHIC 1,0 12 0

153
02-SplineInterpolator/SplineInterpolator_test/hds/.xrf/sinegen_tb_struct.xrf Normal file
View File

@ -0,0 +1,153 @@
DESIGN sine@gen_tb
VIEW struct.bd
NO_GRAPHIC 0
DESIGN sine@gen_tb
VIEW struct.bd
GRAPHIC 142,0 9 0
DESIGN sine@gen_tb
VIEW struct.bd
NO_GRAPHIC 12
DESIGN sine@gen_tb
VIEW struct.bd
GRAPHIC 0,0 16 2
DESIGN sine@gen_tb
VIEW struct.bd
GRAPHIC 1,0 19 0
DESIGN sine@gen_tb
VIEW struct.bd
NO_GRAPHIC 19
DESIGN sine@gen_tb
VIEW struct.bd
GRAPHIC 53,0 25 0
DESIGN sine@gen_tb
VIEW struct.bd
GRAPHIC 45,0 26 0
DESIGN sine@gen_tb
VIEW struct.bd
GRAPHIC 933,0 27 0
DESIGN sine@gen_tb
VIEW struct.bd
GRAPHIC 909,0 28 0
DESIGN sine@gen_tb
VIEW struct.bd
GRAPHIC 925,0 29 0
DESIGN sine@gen_tb
VIEW struct.bd
GRAPHIC 996,0 30 0
DESIGN sine@gen_tb
VIEW struct.bd
GRAPHIC 917,0 31 0
DESIGN sine@gen_tb
VIEW struct.bd
NO_GRAPHIC 32
DESIGN sine@gen_tb
VIEW struct.bd
NO_GRAPHIC 33
LIBRARY SplineInterpolator
DESIGN sine@gen
VIEW struct
GRAPHIC 1519,0 35 0
DESIGN sine@gen
VIEW symbol.sb
GRAPHIC 14,0 36 1
DESIGN sine@gen
VIEW symbol.sb
GRAPHIC 52,0 41 0
DESIGN sine@gen
VIEW symbol.sb
GRAPHIC 88,0 42 0
DESIGN sine@gen
VIEW symbol.sb
GRAPHIC 128,0 43 0
DESIGN sine@gen
VIEW symbol.sb
GRAPHIC 98,0 44 0
DESIGN sine@gen
VIEW symbol.sb
GRAPHIC 103,0 45 0
DESIGN sine@gen
VIEW symbol.sb
GRAPHIC 108,0 46 0
DESIGN sine@gen
VIEW symbol.sb
GRAPHIC 118,0 47 0
LIBRARY SplineInterpolator_test
DESIGN sine@gen_tester
VIEW test
GRAPHIC 421,0 50 0
DESIGN sine@gen_tester
VIEW interface
GRAPHIC 14,0 51 1
DESIGN sine@gen_tb
VIEW struct.bd
GRAPHIC 935,0 57 0
DESIGN sine@gen_tb
VIEW struct.bd
GRAPHIC 911,0 58 0
DESIGN sine@gen_tb
VIEW struct.bd
GRAPHIC 927,0 59 0
DESIGN sine@gen_tb
VIEW struct.bd
GRAPHIC 919,0 60 0
DESIGN sine@gen_tb
VIEW struct.bd
GRAPHIC 55,0 61 0
DESIGN sine@gen_tb
VIEW struct.bd
GRAPHIC 47,0 62 0
DESIGN sine@gen_tb
VIEW struct.bd
GRAPHIC 998,0 63 0
LIBRARY SplineInterpolator_test
DESIGN sine@gen_tb
VIEW struct.bd
NO_GRAPHIC 66
DESIGN sine@gen_tb
VIEW struct.bd
GRAPHIC 1519,0 69 0
DESIGN sine@gen_tb
VIEW struct.bd
GRAPHIC 421,0 70 0
DESIGN sine@gen_tb
VIEW struct.bd
NO_GRAPHIC 73
DESIGN sine@gen_tb
VIEW struct.bd
NO_GRAPHIC 75
DESIGN sine@gen_tb
VIEW struct.bd
GRAPHIC 1519,0 77 0
DESIGN sine@gen_tb
VIEW struct.bd
GRAPHIC 1526,0 78 1
DESIGN sine@gen_tb
VIEW struct.bd
GRAPHIC 55,0 83 0
DESIGN sine@gen_tb
VIEW struct.bd
GRAPHIC 47,0 84 0
DESIGN sine@gen_tb
VIEW struct.bd
GRAPHIC 998,0 85 0
DESIGN sine@gen_tb
VIEW struct.bd
GRAPHIC 935,0 86 0
DESIGN sine@gen_tb
VIEW struct.bd
GRAPHIC 911,0 87 0
DESIGN sine@gen_tb
VIEW struct.bd
GRAPHIC 927,0 88 0
DESIGN sine@gen_tb
VIEW struct.bd
GRAPHIC 919,0 89 0
DESIGN sine@gen_tb
VIEW struct.bd
GRAPHIC 421,0 91 0
DESIGN sine@gen_tb
VIEW struct.bd
GRAPHIC 428,0 92 1
DESIGN sine@gen_tb
VIEW struct.bd
NO_GRAPHIC 107

36
02-SplineInterpolator/SplineInterpolator_test/hds/.xrf/sinegen_tester_entity.xrf Normal file
View File

@ -0,0 +1,36 @@
DESIGN sine@gen_tester
VIEW interface
NO_GRAPHIC 0
DESIGN sine@gen_tester
VIEW interface
GRAPHIC 50,0 8 0
DESIGN sine@gen_tester
VIEW interface
GRAPHIC 13,0 13 1
DESIGN sine@gen_tester
VIEW interface
GRAPHIC 409,0 19 0
DESIGN sine@gen_tester
VIEW interface
GRAPHIC 414,0 20 0
DESIGN sine@gen_tester
VIEW interface
GRAPHIC 419,0 21 0
DESIGN sine@gen_tester
VIEW interface
GRAPHIC 429,0 22 0
DESIGN sine@gen_tester
VIEW interface
GRAPHIC 399,0 23 0
DESIGN sine@gen_tester
VIEW interface
GRAPHIC 404,0 24 0
DESIGN sine@gen_tester
VIEW interface
GRAPHIC 424,0 25 0
DESIGN sine@gen_tester
VIEW interface
GRAPHIC 1,0 28 0
DESIGN sine@gen_tester
VIEW interface
GRAPHIC 1,0 29 0

BIN
solution_lab.zip Normal file
View File

Binary file not shown.

64
zz-solutions/01-WaveformGenerator/Prefs/dp_user/v2_72/dp_user_prefs Normal file
View File

@ -0,0 +1,64 @@
[LexParser.LexVHDL2008]
[LexParser]
[Editor]
recentFile0=/usr/opt/HDS/hdl_libs/ieee/hdl/std_logic_1164.vhdl
lastFilter=.vhdl
mark.lineImage=blueball
[Printer]
ENSCRIPT_LIBRARY=/usr/opt/HDS/resources/enscript/share/enscript
[ToolbarFrames]
geom0Group1=top H
geom0Group2=top H
geom0Group3=top H
state0Search=1
Num=0
state0VersionManagement=1
state0Tasks=1
state0View=1
state0Standard=1
state0Edit=1
Group1=Standard Search
Group2=Edit Bookmarks View Macros DocumentTools Windows
Group3=VersionManagement Tasks
state0Macros=1
state0Bookmarks=1
state0Windows=1
state0DocumentTools=1
[LexParser.LexPSL]
[DND]
TrackerBg=#c3c3c3
signalAcceptDropBg=white
signalRefuseDropBg=red
[General]
[Browser]
normalTextBg=white
normalTextFg=black
[Replace]
historyMax=4
atomicReplaceAll=No
[Console]
[Templates]
Visibility=No
[SearchInFiles]
SearchAsRegExp=0
MatchCase=0
LookInSubfolders=0
historyMax=4
[VDiff]
[R72]
indentType=spaces
indentString=\#\#\#
[TCOM]
logTCOMActivity=No
afterIdleHandlerTimeSlice=300
[Menus]
DocAndVis=
[Help]
default=te_guide
[Plugins]
userLanguages=
[Search]
historyMax=4
[Geometry]
TopWindow0=1286x981+317+1103
FrameSupp0,0=165

19
zz-solutions/01-WaveformGenerator/Prefs/hds.hdp Normal file
View File

@ -0,0 +1,19 @@
[Concat]
[ModelSim]
WaveformGenerator = $SCRATCH_DIR/WaveformGenerator
WaveformGenerator_test = $SCRATCH_DIR/WaveformGenerator_test
[hdl]
ieee = $HDS_HOME/hdl_libs/ieee/hdl
std = $HDS_HOME/hdl_libs/std/hdl
WaveformGenerator = $HDS_PROJECT_DIR/../WaveformGenerator/hdl
WaveformGenerator_test = $HDS_PROJECT_DIR/../WaveformGenerator_test/hdl
[hds]
ieee = $HDS_HOME/hdl_libs/ieee/hds
std = $HDS_HOME/hdl_libs/std/hds
WaveformGenerator = $HDS_PROJECT_DIR/../WaveformGenerator/hds
WaveformGenerator_test = $HDS_PROJECT_DIR/../WaveformGenerator_test/hds
[library_type]
ieee = standard
std = standard
[shared]
others = $HDS_TEAM_HOME/shared.hdp

23
zz-solutions/01-WaveformGenerator/Prefs/hds_team/shared.hdp Normal file
View File

@ -0,0 +1,23 @@
[hds_settings]
version = 1
project_description = The standard HDS shared project
[hds]
ieee = $HDS_HOME/hdl_libs/ieee/hds
std = $HDS_HOME/hdl_libs/std/hds
synopsys = $HDS_HOME/hdl_libs/synopsys/hds
verilog = $HDS_HOME/hdl_libs/verilog/hds
vital2000 = $HDS_HOME/hdl_libs/vital2000/hds
[hdl]
ieee = $HDS_HOME/hdl_libs/ieee/hdl
std = $HDS_HOME/hdl_libs/std/hdl
synopsys = $HDS_HOME/hdl_libs/synopsys/hdl
verilog = $HDS_HOME/hdl_libs/verilog/hdl
vital2000 = $HDS_HOME/hdl_libs/vital2000/hdl
[library_type]
ieee = standard
std = standard
synopsys = standard
verilog = standard
vital2000 = standard

55
zz-solutions/01-WaveformGenerator/Prefs/hds_team/v2018.1/hds_team_prefs Normal file
View File

@ -0,0 +1,55 @@
version "8.0"
RenoirTeamPreferences [
(BaseTeamPreferences
version "1.1"
verConcat 0
ttDGProps [
]
fcDGProps [
]
smDGProps [
]
asmDGProps [
]
bdDGProps [
]
syDGProps [
]
)
(VersionControlTeamPreferences
version "1.1"
VMPlugin ""
VMRepository "$HDS_HOME/examples/hds_scratch/hds_repository"
VMRcsHdsRepository "$HDS_HOME/examples/hds_scratch/hds_repository/%(library)/hds_vm"
VMRcsHdlRepository "$HDS_HOME/examples/hds_scratch/hds_repository/%(library)/hdl_vm"
VMCvsHdsRepository "$HDS_HOME/examples/hds_scratch/hds_repository/hds_vm"
VMCvsHdlRepository "$HDS_HOME/examples/hds_scratch/hds_repository/hdl_vm"
VMCVSmkIIHdsRepository "$HDS_HOME/examples/hds_scratch/hds_repository/hds_vm"
VMCVSmkIIHdlRepository "$HDS_HOME/examples/hds_scratch/hds_repository"
VMVssHdsRepository "$/hds_scratch/hds_repository/%(library)/hds_vm"
VMVssHdlRepository "$/hds_scratch/hds_repository/%(library)/hdl_vm"
VMDsHdsRepository "sync://<host_name>:<port>/hds_scratch/hds_repository/hds_vm"
VMDsHdlRepository "sync://<host_name>:<port>/hds_scratch/hds_repository/hdl_vm"
VMPvcsHdsRepository "$HDS_HOME/examples/hds_scratch/hds_repository/hds_vm"
VMPvcsHdlRepository "$HDS_HOME/examples/hds_scratch/hds_repository/hdl_vm"
VMSvnHdlRepository ""
VMDefaultView 1
VMCurrentDesignHierarchyOnly 0
VMUserData 1
VMGeneratedHDL 0
VMVerboseMode 0
VMAlwaysEmpty 0
VMSetTZ 1
VMSymbol 1
VMCurrentDesignHierarchy 0
VMMultipleRepositoryMode 0
VMSnapshotViewMode 0
backupNameClashes 1
clearCaseMaster 0
)
(CustomizeTeamPreferences
version "1.1"
FileTypes [
]
)
]

273
zz-solutions/01-WaveformGenerator/Prefs/hds_team/v2018.1/title_block.tmpl Normal file
View File

@ -0,0 +1,273 @@
version "4.1"
TitleBlockTemplateRegistrar (TitleBlockTemplate
TitleBlock (Grouping
optionalChildren [
*1 (CommentText
shape (Rectangle
sl 0
va (VaSet
vasetType 1
fg "65280,65280,46080"
)
xt "18000,70000,35000,71000"
)
text (MLText
va (VaSet
fg "0,0,32768"
bg "0,0,32768"
font "Arial,8,0"
)
xt "18200,70000,27100,71000"
st "
by %user on %dd %month %year"
tm "CommentText"
wrapOption 3
visibleHeight 1000
visibleWidth 17000
)
position 1
ignorePrefs 1
)
*2 (CommentText
shape (Rectangle
sl 0
va (VaSet
vasetType 1
fg "65280,65280,46080"
)
xt "35000,66000,39000,67000"
)
text (MLText
va (VaSet
fg "0,0,32768"
bg "0,0,32768"
font "Arial,8,0"
)
xt "35200,66000,37800,67000"
st "
Project:"
tm "CommentText"
wrapOption 3
visibleHeight 1000
visibleWidth 4000
)
position 1
ignorePrefs 1
)
*3 (CommentText
shape (Rectangle
sl 0
va (VaSet
vasetType 1
fg "65280,65280,46080"
)
xt "18000,68000,35000,69000"
)
text (MLText
va (VaSet
fg "0,0,32768"
bg "0,0,32768"
font "Arial,8,0"
)
xt "18200,68000,27800,69000"
st "
<enter diagram title here>"
tm "CommentText"
wrapOption 3
visibleHeight 1000
visibleWidth 17000
)
position 1
ignorePrefs 1
)
*4 (CommentText
shape (Rectangle
sl 0
va (VaSet
vasetType 1
fg "65280,65280,46080"
)
xt "14000,68000,18000,69000"
)
text (MLText
va (VaSet
fg "0,0,32768"
bg "0,0,32768"
font "Arial,8,0"
)
xt "14200,68000,15900,69000"
st "
Title:"
tm "CommentText"
wrapOption 3
visibleHeight 1000
visibleWidth 4000
)
position 1
ignorePrefs 1
)
*5 (CommentText
shape (Rectangle
sl 0
va (VaSet
vasetType 1
fg "65280,65280,46080"
)
xt "35000,67000,55000,71000"
)
text (MLText
va (VaSet
fg "0,0,32768"
bg "0,0,32768"
font "Arial,8,0"
)
xt "35200,67200,44000,68200"
st "
<enter comments here>"
tm "CommentText"
wrapOption 3
visibleHeight 4000
visibleWidth 20000
)
ignorePrefs 1
)
*6 (CommentText
shape (Rectangle
sl 0
va (VaSet
vasetType 1
fg "65280,65280,46080"
)
xt "39000,66000,55000,67000"
)
text (MLText
va (VaSet
fg "0,0,32768"
bg "0,0,32768"
font "Arial,8,0"
)
xt "39200,66000,48900,67000"
st "%project_name"
tm "CommentText"
wrapOption 3
visibleHeight 1000
visibleWidth 16000
)
position 1
ignorePrefs 1
)
*7 (CommentText
shape (Rectangle
sl 0
va (VaSet
vasetType 1
fg "65280,65280,46080"
)
xt "14000,66000,35000,68000"
)
text (MLText
va (VaSet
fg "32768,0,0"
)
xt "19950,66350,29050,67650"
st "
<company name>"
ju 0
tm "CommentText"
wrapOption 3
visibleHeight 2000
visibleWidth 21000
)
position 1
ignorePrefs 1
)
*8 (CommentText
shape (Rectangle
sl 0
va (VaSet
vasetType 1
fg "65280,65280,46080"
)
xt "14000,69000,18000,70000"
)
text (MLText
va (VaSet
fg "0,0,32768"
bg "0,0,32768"
font "Arial,8,0"
)
xt "14200,69000,15900,70000"
st "
Path:"
tm "CommentText"
wrapOption 3
visibleHeight 1000
visibleWidth 4000
)
position 1
ignorePrefs 1
)
*9 (CommentText
shape (Rectangle
sl 0
va (VaSet
vasetType 1
fg "65280,65280,46080"
)
xt "14000,70000,18000,71000"
)
text (MLText
va (VaSet
fg "0,0,32768"
bg "0,0,32768"
font "Arial,8,0"
)
xt "14200,70000,16500,71000"
st "
Edited:"
tm "CommentText"
wrapOption 3
visibleHeight 1000
visibleWidth 4000
)
position 1
ignorePrefs 1
)
*10 (CommentText
shape (Rectangle
sl 0
va (VaSet
vasetType 1
fg "65280,65280,46080"
)
xt "18000,69000,35000,70000"
)
text (MLText
va (VaSet
fg "0,0,32768"
bg "0,0,32768"
font "Arial,8,0"
)
xt "18200,69000,25400,70000"
st "
%library/%unit/%view"
tm "CommentText"
wrapOption 3
visibleHeight 1000
visibleWidth 17000
)
position 1
ignorePrefs 1
)
]
shape (GroupingShape
va (VaSet
vasetType 1
fg "65535,65535,65535"
lineStyle 2
lineWidth 2
)
xt "14000,66000,55000,71000"
)
)
)

55
zz-solutions/01-WaveformGenerator/Prefs/hds_team/v2019.2/hds_team_prefs Normal file
View File

@ -0,0 +1,55 @@
version "8.0"
RenoirTeamPreferences [
(BaseTeamPreferences
version "1.1"
verConcat 0
ttDGProps [
]
fcDGProps [
]
smDGProps [
]
asmDGProps [
]
bdDGProps [
]
syDGProps [
]
)
(VersionControlTeamPreferences
version "1.1"
VMPlugin ""
VMRepository "$HDS_HOME/examples/hds_scratch/hds_repository"
VMRcsHdsRepository "$HDS_HOME/examples/hds_scratch/hds_repository/%(library)/hds_vm"
VMRcsHdlRepository "$HDS_HOME/examples/hds_scratch/hds_repository/%(library)/hdl_vm"
VMCvsHdsRepository "$HDS_HOME/examples/hds_scratch/hds_repository/hds_vm"
VMCvsHdlRepository "$HDS_HOME/examples/hds_scratch/hds_repository/hdl_vm"
VMCVSmkIIHdsRepository "$HDS_HOME/examples/hds_scratch/hds_repository/hds_vm"
VMCVSmkIIHdlRepository "$HDS_HOME/examples/hds_scratch/hds_repository"
VMVssHdsRepository "$/hds_scratch/hds_repository/%(library)/hds_vm"
VMVssHdlRepository "$/hds_scratch/hds_repository/%(library)/hdl_vm"
VMDsHdsRepository "sync://<host_name>:<port>/hds_scratch/hds_repository/hds_vm"
VMDsHdlRepository "sync://<host_name>:<port>/hds_scratch/hds_repository/hdl_vm"
VMPvcsHdsRepository "$HDS_HOME/examples/hds_scratch/hds_repository/hds_vm"
VMPvcsHdlRepository "$HDS_HOME/examples/hds_scratch/hds_repository/hdl_vm"
VMSvnHdlRepository ""
VMDefaultView 1
VMCurrentDesignHierarchyOnly 0
VMUserData 1
VMGeneratedHDL 0
VMVerboseMode 0
VMAlwaysEmpty 0
VMSetTZ 1
VMSymbol 1
VMCurrentDesignHierarchy 0
VMMultipleRepositoryMode 0
VMSnapshotViewMode 0
backupNameClashes 1
clearCaseMaster 0
)
(CustomizeTeamPreferences
version "1.1"
FileTypes [
]
)
]

55
zz-solutions/01-WaveformGenerator/Prefs/hds_team/v2019.2/hds_team_prefs.bak Normal file
View File

@ -0,0 +1,55 @@
version "8.0"
RenoirTeamPreferences [
(BaseTeamPreferences
version "1.1"
verConcat 0
ttDGProps [
]
fcDGProps [
]
smDGProps [
]
asmDGProps [
]
bdDGProps [
]
syDGProps [
]
)
(VersionControlTeamPreferences
version "1.1"
VMPlugin ""
VMRepository "$HDS_HOME/examples/hds_scratch/hds_repository"
VMRcsHdsRepository "$HDS_HOME/examples/hds_scratch/hds_repository/%(library)/hds_vm"
VMRcsHdlRepository "$HDS_HOME/examples/hds_scratch/hds_repository/%(library)/hdl_vm"
VMCvsHdsRepository "$HDS_HOME/examples/hds_scratch/hds_repository/hds_vm"
VMCvsHdlRepository "$HDS_HOME/examples/hds_scratch/hds_repository/hdl_vm"
VMCVSmkIIHdsRepository "$HDS_HOME/examples/hds_scratch/hds_repository/hds_vm"
VMCVSmkIIHdlRepository "$HDS_HOME/examples/hds_scratch/hds_repository"
VMVssHdsRepository "$/hds_scratch/hds_repository/%(library)/hds_vm"
VMVssHdlRepository "$/hds_scratch/hds_repository/%(library)/hdl_vm"
VMDsHdsRepository "sync://<host_name>:<port>/hds_scratch/hds_repository/hds_vm"
VMDsHdlRepository "sync://<host_name>:<port>/hds_scratch/hds_repository/hdl_vm"
VMPvcsHdsRepository "$HDS_HOME/examples/hds_scratch/hds_repository/hds_vm"
VMPvcsHdlRepository "$HDS_HOME/examples/hds_scratch/hds_repository/hdl_vm"
VMSvnHdlRepository ""
VMDefaultView 1
VMCurrentDesignHierarchyOnly 0
VMUserData 1
VMGeneratedHDL 0
VMVerboseMode 0
VMAlwaysEmpty 0
VMSetTZ 1
VMSymbol 1
VMCurrentDesignHierarchy 0
VMMultipleRepositoryMode 0
VMSnapshotViewMode 0
backupNameClashes 1
clearCaseMaster 0
)
(CustomizeTeamPreferences
version "1.1"
FileTypes [
]
)
]

273
zz-solutions/01-WaveformGenerator/Prefs/hds_team/v2019.2/title_block.tmpl Normal file
View File

@ -0,0 +1,273 @@
version "4.1"
TitleBlockTemplateRegistrar (TitleBlockTemplate
TitleBlock (Grouping
optionalChildren [
*1 (CommentText
shape (Rectangle
sl 0
va (VaSet
vasetType 1
fg "65280,65280,46080"
)
xt "18000,70000,35000,71000"
)
text (MLText
va (VaSet
fg "0,0,32768"
bg "0,0,32768"
font "Arial,8,0"
)
xt "18200,70000,27100,71000"
st "
by %user on %dd %month %year"
tm "CommentText"
wrapOption 3
visibleHeight 1000
visibleWidth 17000
)
position 1
ignorePrefs 1
)
*2 (CommentText
shape (Rectangle
sl 0
va (VaSet
vasetType 1
fg "65280,65280,46080"
)
xt "35000,66000,39000,67000"
)
text (MLText
va (VaSet
fg "0,0,32768"
bg "0,0,32768"
font "Arial,8,0"
)
xt "35200,66000,37800,67000"
st "
Project:"
tm "CommentText"
wrapOption 3
visibleHeight 1000
visibleWidth 4000
)
position 1
ignorePrefs 1
)
*3 (CommentText
shape (Rectangle
sl 0
va (VaSet
vasetType 1
fg "65280,65280,46080"
)
xt "18000,68000,35000,69000"
)
text (MLText
va (VaSet
fg "0,0,32768"
bg "0,0,32768"
font "Arial,8,0"
)
xt "18200,68000,27800,69000"
st "
<enter diagram title here>"
tm "CommentText"
wrapOption 3
visibleHeight 1000
visibleWidth 17000
)
position 1
ignorePrefs 1
)
*4 (CommentText
shape (Rectangle
sl 0
va (VaSet
vasetType 1
fg "65280,65280,46080"
)
xt "14000,68000,18000,69000"
)
text (MLText
va (VaSet
fg "0,0,32768"
bg "0,0,32768"
font "Arial,8,0"
)
xt "14200,68000,15900,69000"
st "
Title:"
tm "CommentText"
wrapOption 3
visibleHeight 1000
visibleWidth 4000
)
position 1
ignorePrefs 1
)
*5 (CommentText
shape (Rectangle
sl 0
va (VaSet
vasetType 1
fg "65280,65280,46080"
)
xt "35000,67000,55000,71000"
)
text (MLText
va (VaSet
fg "0,0,32768"
bg "0,0,32768"
font "Arial,8,0"
)
xt "35200,67200,44000,68200"
st "
<enter comments here>"
tm "CommentText"
wrapOption 3
visibleHeight 4000
visibleWidth 20000
)
ignorePrefs 1
)
*6 (CommentText
shape (Rectangle
sl 0
va (VaSet
vasetType 1
fg "65280,65280,46080"
)
xt "39000,66000,55000,67000"
)
text (MLText
va (VaSet
fg "0,0,32768"
bg "0,0,32768"
font "Arial,8,0"
)
xt "39200,66000,48900,67000"
st "%project_name"
tm "CommentText"
wrapOption 3
visibleHeight 1000
visibleWidth 16000
)
position 1
ignorePrefs 1
)
*7 (CommentText
shape (Rectangle
sl 0
va (VaSet
vasetType 1
fg "65280,65280,46080"
)
xt "14000,66000,35000,68000"
)
text (MLText
va (VaSet
fg "32768,0,0"
)
xt "19950,66350,29050,67650"
st "
<company name>"
ju 0
tm "CommentText"
wrapOption 3
visibleHeight 2000
visibleWidth 21000
)
position 1
ignorePrefs 1
)
*8 (CommentText
shape (Rectangle
sl 0
va (VaSet
vasetType 1
fg "65280,65280,46080"
)
xt "14000,69000,18000,70000"
)
text (MLText
va (VaSet
fg "0,0,32768"
bg "0,0,32768"
font "Arial,8,0"
)
xt "14200,69000,15900,70000"
st "
Path:"
tm "CommentText"
wrapOption 3
visibleHeight 1000
visibleWidth 4000
)
position 1
ignorePrefs 1
)
*9 (CommentText
shape (Rectangle
sl 0
va (VaSet
vasetType 1
fg "65280,65280,46080"
)
xt "14000,70000,18000,71000"
)
text (MLText
va (VaSet
fg "0,0,32768"
bg "0,0,32768"
font "Arial,8,0"
)
xt "14200,70000,16500,71000"
st "
Edited:"
tm "CommentText"
wrapOption 3
visibleHeight 1000
visibleWidth 4000
)
position 1
ignorePrefs 1
)
*10 (CommentText
shape (Rectangle
sl 0
va (VaSet
vasetType 1
fg "65280,65280,46080"
)
xt "18000,69000,35000,70000"
)
text (MLText
va (VaSet
fg "0,0,32768"
bg "0,0,32768"
font "Arial,8,0"
)
xt "18200,69000,25400,70000"
st "
%library/%unit/%view"
tm "CommentText"
wrapOption 3
visibleHeight 1000
visibleWidth 17000
)
position 1
ignorePrefs 1
)
]
shape (GroupingShape
va (VaSet
vasetType 1
fg "65535,65535,65535"
lineStyle 2
lineWidth 2
)
xt "14000,66000,55000,71000"
)
)
)

55
zz-solutions/01-WaveformGenerator/Prefs/hds_team/v2019.3/hds_team_prefs Normal file
View File

@ -0,0 +1,55 @@
version "8.0"
RenoirTeamPreferences [
(BaseTeamPreferences
version "1.1"
verConcat 0
ttDGProps [
]
fcDGProps [
]
smDGProps [
]
asmDGProps [
]
bdDGProps [
]
syDGProps [
]
)
(VersionControlTeamPreferences
version "1.1"
VMPlugin ""
VMRepository "$HDS_HOME/examples/hds_scratch/hds_repository"
VMRcsHdsRepository "$HDS_HOME/examples/hds_scratch/hds_repository/%(library)/hds_vm"
VMRcsHdlRepository "$HDS_HOME/examples/hds_scratch/hds_repository/%(library)/hdl_vm"
VMCvsHdsRepository "$HDS_HOME/examples/hds_scratch/hds_repository/hds_vm"
VMCvsHdlRepository "$HDS_HOME/examples/hds_scratch/hds_repository/hdl_vm"
VMCVSmkIIHdsRepository "$HDS_HOME/examples/hds_scratch/hds_repository/hds_vm"
VMCVSmkIIHdlRepository "$HDS_HOME/examples/hds_scratch/hds_repository"
VMVssHdsRepository "$/hds_scratch/hds_repository/%(library)/hds_vm"
VMVssHdlRepository "$/hds_scratch/hds_repository/%(library)/hdl_vm"
VMDsHdsRepository "sync://<host_name>:<port>/hds_scratch/hds_repository/hds_vm"
VMDsHdlRepository "sync://<host_name>:<port>/hds_scratch/hds_repository/hdl_vm"
VMPvcsHdsRepository "$HDS_HOME/examples/hds_scratch/hds_repository/hds_vm"
VMPvcsHdlRepository "$HDS_HOME/examples/hds_scratch/hds_repository/hdl_vm"
VMSvnHdlRepository ""
VMDefaultView 1
VMCurrentDesignHierarchyOnly 0
VMUserData 1
VMGeneratedHDL 0
VMVerboseMode 0
VMAlwaysEmpty 0
VMSetTZ 1
VMSymbol 1
VMCurrentDesignHierarchy 0
VMMultipleRepositoryMode 0
VMSnapshotViewMode 0
backupNameClashes 1
clearCaseMaster 0
)
(CustomizeTeamPreferences
version "1.1"
FileTypes [
]
)
]

273
zz-solutions/01-WaveformGenerator/Prefs/hds_team/v2019.3/title_block.tmpl Normal file
View File

@ -0,0 +1,273 @@
version "4.1"
TitleBlockTemplateRegistrar (TitleBlockTemplate
TitleBlock (Grouping
optionalChildren [
*1 (CommentText
shape (Rectangle
sl 0
va (VaSet
vasetType 1
fg "65280,65280,46080"
)
xt "18000,70000,35000,71000"
)
text (MLText
va (VaSet
fg "0,0,32768"
bg "0,0,32768"
font "Arial,8,0"
)
xt "18200,70000,27100,71000"
st "
by %user on %dd %month %year"
tm "CommentText"
wrapOption 3
visibleHeight 1000
visibleWidth 17000
)
position 1
ignorePrefs 1
)
*2 (CommentText
shape (Rectangle
sl 0
va (VaSet
vasetType 1
fg "65280,65280,46080"
)
xt "35000,66000,39000,67000"
)
text (MLText
va (VaSet
fg "0,0,32768"
bg "0,0,32768"
font "Arial,8,0"
)
xt "35200,66000,37800,67000"
st "
Project:"
tm "CommentText"
wrapOption 3
visibleHeight 1000
visibleWidth 4000
)
position 1
ignorePrefs 1
)
*3 (CommentText
shape (Rectangle
sl 0
va (VaSet
vasetType 1
fg "65280,65280,46080"
)
xt "18000,68000,35000,69000"
)
text (MLText
va (VaSet
fg "0,0,32768"
bg "0,0,32768"
font "Arial,8,0"
)
xt "18200,68000,27800,69000"
st "
<enter diagram title here>"
tm "CommentText"
wrapOption 3
visibleHeight 1000
visibleWidth 17000
)
position 1
ignorePrefs 1
)
*4 (CommentText
shape (Rectangle
sl 0
va (VaSet
vasetType 1
fg "65280,65280,46080"
)
xt "14000,68000,18000,69000"
)
text (MLText
va (VaSet
fg "0,0,32768"
bg "0,0,32768"
font "Arial,8,0"
)
xt "14200,68000,15900,69000"
st "
Title:"
tm "CommentText"
wrapOption 3
visibleHeight 1000
visibleWidth 4000
)
position 1
ignorePrefs 1
)
*5 (CommentText
shape (Rectangle
sl 0
va (VaSet
vasetType 1
fg "65280,65280,46080"
)
xt "35000,67000,55000,71000"
)
text (MLText
va (VaSet
fg "0,0,32768"
bg "0,0,32768"
font "Arial,8,0"
)
xt "35200,67200,44000,68200"
st "
<enter comments here>"
tm "CommentText"
wrapOption 3
visibleHeight 4000
visibleWidth 20000
)
ignorePrefs 1
)
*6 (CommentText
shape (Rectangle
sl 0
va (VaSet
vasetType 1
fg "65280,65280,46080"
)
xt "39000,66000,55000,67000"
)
text (MLText
va (VaSet
fg "0,0,32768"
bg "0,0,32768"
font "Arial,8,0"
)
xt "39200,66000,48900,67000"
st "%project_name"
tm "CommentText"
wrapOption 3
visibleHeight 1000
visibleWidth 16000
)
position 1
ignorePrefs 1
)
*7 (CommentText
shape (Rectangle
sl 0
va (VaSet
vasetType 1
fg "65280,65280,46080"
)
xt "14000,66000,35000,68000"
)
text (MLText
va (VaSet
fg "32768,0,0"
)
xt "19950,66350,29050,67650"
st "
<company name>"
ju 0
tm "CommentText"
wrapOption 3
visibleHeight 2000
visibleWidth 21000
)
position 1
ignorePrefs 1
)
*8 (CommentText
shape (Rectangle
sl 0
va (VaSet
vasetType 1
fg "65280,65280,46080"
)
xt "14000,69000,18000,70000"
)
text (MLText
va (VaSet
fg "0,0,32768"
bg "0,0,32768"
font "Arial,8,0"
)
xt "14200,69000,15900,70000"
st "
Path:"
tm "CommentText"
wrapOption 3
visibleHeight 1000
visibleWidth 4000
)
position 1
ignorePrefs 1
)
*9 (CommentText
shape (Rectangle
sl 0
va (VaSet
vasetType 1
fg "65280,65280,46080"
)
xt "14000,70000,18000,71000"
)
text (MLText
va (VaSet
fg "0,0,32768"
bg "0,0,32768"
font "Arial,8,0"
)
xt "14200,70000,16500,71000"
st "
Edited:"
tm "CommentText"
wrapOption 3
visibleHeight 1000
visibleWidth 4000
)
position 1
ignorePrefs 1
)
*10 (CommentText
shape (Rectangle
sl 0
va (VaSet
vasetType 1
fg "65280,65280,46080"
)
xt "18000,69000,35000,70000"
)
text (MLText
va (VaSet
fg "0,0,32768"
bg "0,0,32768"
font "Arial,8,0"
)
xt "18200,69000,25400,70000"
st "
%library/%unit/%view"
tm "CommentText"
wrapOption 3
visibleHeight 1000
visibleWidth 17000
)
position 1
ignorePrefs 1
)
]
shape (GroupingShape
va (VaSet
vasetType 1
fg "65535,65535,65535"
lineStyle 2
lineWidth 2
)
xt "14000,66000,55000,71000"
)
)
)

6097
zz-solutions/01-WaveformGenerator/Prefs/hds_user-linux/v2019.3/hds_user_prefs Normal file
View File

File diff suppressed because it is too large Load Diff

41
zz-solutions/01-WaveformGenerator/Prefs/hds_user-linux/v2019.3/tasks/generate.tsk Normal file
View File

@ -0,0 +1,41 @@
version "1.1"
HDSTool (HDSTool
hasAssociatedFileExt 0
associatedFileExt ""
TaskName "Generate"
bitmap "$HDS_HOME\\resources\\bitmaps\\tools/tool_generate.bmp"
hasBitmap 1
tooltip "Performs generation of graphics files"
taskSettings [
"InternalTaskSetting"
(SettingsMap
settingsMap [
"additionalToolArgs"
""
"captureOutput"
"0"
"customPrompt"
""
"initialDir"
""
"promptForRunSettings"
"0"
"runMethod"
"gui"
"runnableObject"
"Generator"
"runnableObjectType"
"tcl_plugin"
"useViewSpecific"
"0"
]
)
]
PreferedTasks [
]
onShortcutBar 1
onPulldownMenu 1
onToolbar 1
enabled 1
hierDepth 1
)

98
zz-solutions/01-WaveformGenerator/Prefs/hds_user-linux/v2019.3/tasks/modelsim_compile.tsk Normal file
View File

@ -0,0 +1,98 @@
version "1.1"
HDSTool (HDSTool
hasAssociatedFileExt 0
associatedFileExt ""
TaskName "ModelSim Compile"
bitmap "$HDS_HOME\\resources\\bitmaps\\tools/tool_modelsim_compile.bmp"
hasBitmap 1
tooltip "Runs ModelSim compilation"
taskSettings [
"InternalTaskSetting"
(SettingsMap
settingsMap [
"additionalToolArgs"
""
"captureOutput"
"0"
"customPrompt"
""
"initialDir"
""
"promptForRunSettings"
"0"
"runMethod"
"gui"
"runnableObject"
"ModelSimCompiler"
"runnableObjectType"
"tcl_plugin"
"useViewSpecific"
"0"
]
)
"TaskSetting"
(SettingsMap
settingsMap [
"64bit"
"0"
"compAlways"
"0"
"covSwitch"
""
"coverNoSub"
""
"dontAskAgain"
"0"
"enableMFCU"
"1"
"excludePSL"
"0"
"exepath"
"$MODELSIM_HOME"
"logFile"
""
"logicalLib"
"1"
"mapAllLib"
"0"
"mapQuartusIPs"
"1"
"masterCov"
"0"
"peSe"
"EE"
"prevOnly"
"0"
"quartusSimDir"
"$HDS_PROJECT_DIR/QuartusIPSimLibs"
"replayScriptPath"
""
"saveReplayScript"
"0"
"server"
""
"showCmd"
"0"
"transcript"
"1"
"useFlatLibrary"
"0"
"useRemote"
"0"
"useShortName"
"0"
"vhdlSwitches"
" -nologo"
"vlogSwitches"
" -nologo"
]
)
]
PreferedTasks [
]
onShortcutBar 1
onPulldownMenu 0
onToolbar 0
enabled 1
hierDepth 1
)

83
zz-solutions/01-WaveformGenerator/Prefs/hds_user-linux/v2019.3/tasks/modelsim_flow.tsk Normal file
View File

@ -0,0 +1,83 @@
version "1.1"
HDSFlow (HDSFlow
TaskName "ModelSim Flow"
bitmap "$HDS_HOME\\resources\\bitmaps\\tools/tool_modelsim.bmp"
hasBitmap 1
tooltip "Generate and run entire ModelSim flow"
taskSettings [
"InternalTaskSetting"
(SettingsMap
settingsMap [
"flowSettingsDlg"
""
"taskInvocationScript"
""
]
)
]
PreferedTasks [
(preferedMap
preferedEnum 0
preferedSetting "$MODELSIM_HOME"
)
(preferedMap
preferedEnum 2
preferedSetting "ModelSim"
)
]
onShortcutBar 1
onPulldownMenu 1
onToolbar 1
enabled 1
hierDepth 1
subTasks [
(HDSTaskRef
TaskName "Generate"
bitmap ""
hasBitmap 1
tooltip ""
taskSettings [
]
PreferedTasks [
]
onShortcutBar 0
onPulldownMenu 0
onToolbar 0
enabled 1
hierDepth 1
reffedTaskName "USER:Generate"
)
(HDSTaskRef
TaskName "ModelSim Compile"
bitmap ""
hasBitmap 1
tooltip ""
taskSettings [
]
PreferedTasks [
]
onShortcutBar 0
onPulldownMenu 0
onToolbar 0
enabled 1
hierDepth 1
reffedTaskName "USER:ModelSim Compile"
)
(HDSTaskRef
TaskName "ModelSim Simulate"
bitmap ""
hasBitmap 1
tooltip ""
taskSettings [
]
PreferedTasks [
]
onShortcutBar 0
onPulldownMenu 0
onToolbar 0
enabled 1
hierDepth 3
reffedTaskName "USER:ModelSim Simulate"
)
]
)

98
zz-solutions/01-WaveformGenerator/Prefs/hds_user-linux/v2019.3/tasks/modelsim_simulate.tsk Normal file
View File

@ -0,0 +1,98 @@
version "1.1"
HDSTool (HDSTool
hasAssociatedFileExt 0
associatedFileExt ""
TaskName "ModelSim Simulate"
bitmap "$HDS_HOME\\resources\\bitmaps\\tools/tool_modelsim_invoke.bmp"
hasBitmap 1
tooltip "Invokes the ModelSim Simulator"
taskSettings [
"InternalTaskSetting"
(SettingsMap
settingsMap [
"additionalToolArgs"
""
"captureOutput"
"0"
"customPrompt"
""
"initialDir"
""
"promptForRunSettings"
"1"
"runMethod"
"gui"
"runnableObject"
"ModelSimSimulator"
"runnableObjectType"
"tcl_plugin"
"useViewSpecific"
"0"
]
)
"TaskSetting"
(SettingsMap
settingsMap [
"Arguments"
""
"Arguments1"
"do controller.do"
"Arguments2"
"controller.do"
"Communication"
"1"
"DelaySelection"
"typ"
"GlitchGeneration"
"1"
"InitCmd"
"$SIMULATION_DIR/waveformGen.do"
"LogFile"
""
"RemoteHost"
""
"Resolution"
"ps"
"SdfDelay"
"typ"
"SdfMultiSrcDelay"
"latest"
"SdfReduce"
"0"
"SdfWarnings"
"1"
"TimingChecks"
"1"
"UseBatch"
"0"
"UseCLI"
"0"
"UseGUI"
"1"
"VitalVersion"
"95"
"autoNames"
"1"
"coverage"
"0"
"excludePSL"
"0"
"exepath"
"$MODELSIM_HOME"
"minimumSimSetting"
"0"
"saveReplayScript"
"0"
"useCustomSimDir"
"0"
]
)
]
PreferedTasks [
]
onShortcutBar 1
onPulldownMenu 0
onToolbar 0
enabled 1
hierDepth 3
)

162
zz-solutions/01-WaveformGenerator/Prefs/hds_user-linux/v2019.3/tasks/prepare_for_synthesis.tsk Normal file
View File

@ -0,0 +1,162 @@
version "1.1"
HDSFlow (HDSFlow
TaskName "Prepare for Synthesis"
bitmap "$HDS_HOME\\resources\\bitmaps\\tools\\tool_synthesis.bmp"
hasBitmap 1
tooltip "generates a single file"
taskSettings [
"InternalTaskSetting"
(SettingsMap
settingsMap [
"flowSettingsDlg"
""
"taskInvocationScript"
""
]
)
]
PreferedTasks [
]
onShortcutBar 1
onPulldownMenu 0
onToolbar 1
enabled 1
hierDepth 1
subTasks [
(HDSTool
hasAssociatedFileExt 0
associatedFileExt ""
TaskName "Generate"
bitmap "$HDS_HOME\\resources\\bitmaps\\tools/tool_generate.bmp"
hasBitmap 1
tooltip "Performs generation of graphics files"
taskSettings [
"InternalTaskSetting"
(SettingsMap
settingsMap [
"additionalToolArgs"
""
"captureOutput"
"0"
"customPrompt"
""
"initialDir"
""
"promptForRunSettings"
"0"
"runMethod"
"gui"
"runnableObject"
"Generator"
"runnableObjectType"
"tcl_plugin"
"useViewSpecific"
"0"
]
)
]
PreferedTasks [
]
onShortcutBar 0
onPulldownMenu 0
onToolbar 0
enabled 1
hierDepth 1
)
(HDSTool
hasAssociatedFileExt 0
associatedFileExt ""
TaskName "Concatenate HDL"
bitmap "$HDS_HOME\\resources\\bitmaps\\tools/tool_concatenate.bmp"
hasBitmap 1
tooltip "Appends all HDL files together"
taskSettings [
"InternalTaskSetting"
(SettingsMap
settingsMap [
"additionalToolArgs"
""
"captureOutput"
"0"
"customPrompt"
""
"initialDir"
""
"promptForRunSettings"
"0"
"runMethod"
"gui"
"runnableObject"
"Concatenation"
"runnableObjectType"
"tcl_plugin"
"useViewSpecific"
"1"
]
)
"TaskSetting"
(SettingsMap
settingsMap [
"outputFileNameRoot"
"%(concat_file)"
"outputVerilogFileExtension"
"v"
"outputVhdlFileExtension"
"vhd"
"place"
"0"
"specifyDir"
""
]
)
]
PreferedTasks [
]
onShortcutBar 0
onPulldownMenu 0
onToolbar 0
enabled 1
hierDepth 1
)
(HDSTool
hasAssociatedFileExt 0
associatedFileExt ""
TaskName "Trim libraries"
bitmap "tool_default_tool.bmp"
hasBitmap 1
tooltip "comment out library declarations for singles file"
taskSettings [
"InternalTaskSetting"
(SettingsMap
settingsMap [
"additionalToolArgs"
".\\..\\..\\Scripts\\trimLibs.pl %(concat_file).vhd $DESIGN_NAME.vhd"
"captureOutput"
"1"
"customPrompt"
""
"initialDir"
"$CONCAT_DIR"
"promptForRunSettings"
"0"
"runMethod"
"gui"
"runnableObject"
"/usr/bin/perl"
"runnableObjectType"
"executable"
"useViewSpecific"
"0"
]
)
]
PreferedTasks [
]
onShortcutBar 0
onPulldownMenu 0
onToolbar 0
enabled 1
hierDepth 3
)
]
)

114
zz-solutions/01-WaveformGenerator/Prefs/hds_user-linux/v2019.3/tasks/xilinx_project_navigator.tsk Normal file
View File

@ -0,0 +1,114 @@
version "1.1"
HDSFlow (HDSFlow
TaskName "Xilinx Project Navigator"
bitmap "/usr/opt/HDS/resources/bitmaps/tools/tool_xilinx_synthesis.bmp"
hasBitmap 1
tooltip "Xilinx Flow"
taskSettings [
"InternalTaskSetting"
(SettingsMap
settingsMap [
"flowSettingsDlg"
""
"taskInvocationScript"
""
]
)
]
PreferedTasks [
]
onShortcutBar 0
onPulldownMenu 0
onToolbar 1
enabled 1
hierDepth 1
subTasks [
(HDSTool
hasAssociatedFileExt 0
associatedFileExt ""
TaskName "Update Project"
bitmap "tool_default_tool.bmp"
hasBitmap 1
tooltip "Update file references in the Xilinx project .xise file"
taskSettings [
"InternalTaskSetting"
(SettingsMap
settingsMap [
"additionalToolArgs"
"$SYNTHESIS_BASE_DIR/../../Scripts/update_ise.pl $DESIGN_NAME.xise $CONCAT_DIR/$DESIGN_NAME.vhd $CONCAT_DIR/$DESIGN_NAME.ucf"
"captureOutput"
"1"
"customPrompt"
""
"initialDir"
"$SYNTHESIS_WORK_DIR"
"promptForRunSettings"
"0"
"runMethod"
"gui"
"runnableObject"
"/usr/bin/perl"
"runnableObjectType"
"executable"
"useViewSpecific"
"0"
]
)
]
PreferedTasks [
]
onShortcutBar 0
onPulldownMenu 0
onToolbar 0
enabled 1
hierDepth 3
)
(HDSTool
hasAssociatedFileExt 0
associatedFileExt ""
TaskName "Xilinx Project Navigator"
bitmap "$HDS_HOME/resources/bitmaps/tools/tool_xilinx_synthesis.bmp"
hasBitmap 1
tooltip "Invokes Xilinx ISE Synthesis Tool"
taskSettings [
"InternalTaskSetting"
(SettingsMap
settingsMap [
"additionalToolArgs"
""
"captureOutput"
"0"
"customPrompt"
""
"initialDir"
"$SYNTHESIS_WORK_DIR"
"promptForRunSettings"
"0"
"runMethod"
"gui"
"runnableObject"
"$SYNTHESIS_HOME/bin/lin64/ise"
"runnableObjectType"
"executable"
"useViewSpecific"
"0"
]
)
"TaskSetting"
(SettingsMap
settingsMap [
"exePath"
"/usr/opt/Xilinx/14.7/ISE_DS/ISE/bin/lin64"
]
)
]
PreferedTasks [
]
onShortcutBar 0
onPulldownMenu 0
onToolbar 0
enabled 1
hierDepth 3
)
]
)

15
zz-solutions/01-WaveformGenerator/Prefs/hds_user-linux/v2019.3/templates/vhdl_architecture/architecture.vhd Normal file
View File

@ -0,0 +1,15 @@
FILE_NAMING_RULE: %(entity_name)_%(arch_name).vhd
DESCRIPTION_START
This is the default template used for the creation of VHDL Architecture files.
Template supplied by Mentor Graphics.
DESCRIPTION_END
--
-- VHDL Architecture %(library).%(unit).%(view)
--
-- Created:
-- by - %(user).%(group) (%(host))
-- at - %(time) %(date)
--
-- using Mentor Graphics HDL Designer(TM) %(version)
--
%(architecture)

17
zz-solutions/01-WaveformGenerator/Prefs/hds_user-linux/v2019.3/templates/vhdl_combined/combined.vhd Normal file
View File

@ -0,0 +1,17 @@
FILE_NAMING_RULE: %(entity_name)_%(arch_name).vhd
DESCRIPTION_START
This is the default template used for the creation of combined VHDL Architecture and Entity files.
Template supplied by Mentor Graphics.
DESCRIPTION_END
--
-- VHDL Architecture %(library).%(unit).%(view)
--
-- Created:
-- by - %(user).%(group) (%(host))
-- at - %(time) %(date)
--
-- using Mentor Graphics HDL Designer(TM) %(version)
--
%(entity)
--
%(architecture)

19
zz-solutions/01-WaveformGenerator/Prefs/hds_user-linux/v2019.3/templates/vhdl_configuration/configuration.vhd Normal file
View File

@ -0,0 +1,19 @@
FILE_NAMING_RULE: %(entity_name)_%(arch_name)_config.vhd
DESCRIPTION_START
This is the default template used for the creation of VHDL Configuration files.
Template supplied by Mentor Graphics.
DESCRIPTION_END
--
-- VHDL Configuration %(library).%(unit).%(view)
--
-- Created:
-- by - %(user).%(group) (%(host))
-- at - %(time) %(date)
--
-- using Mentor Graphics HDL Designer(TM) %(version)
--
CONFIGURATION %(entity_name)_config OF %(entity_name) IS
FOR %(arch_name)
END FOR;
END %(entity_name)_config;

15
zz-solutions/01-WaveformGenerator/Prefs/hds_user-linux/v2019.3/templates/vhdl_entity/entity.vhd Normal file
View File

@ -0,0 +1,15 @@
FILE_NAMING_RULE: %(entity_name)_entity.vhd
DESCRIPTION_START
This is the default template used for the creation of VHDL Entity files.
Template supplied by Mentor Graphics.
DESCRIPTION_END
--
-- VHDL Entity %(library).%(unit).%(view)
--
-- Created:
-- by - %(user).%(group) (%(host))
-- at - %(time) %(date)
--
-- using Mentor Graphics HDL Designer(TM) %(version)
--
%(entity)

16
zz-solutions/01-WaveformGenerator/Prefs/hds_user-linux/v2019.3/templates/vhdl_package_body/package_body.vhd Normal file
View File

@ -0,0 +1,16 @@
FILE_NAMING_RULE: %(entity_name)_pkg_body.vhd
DESCRIPTION_START
This is the default template used for the creation of VHDL Package Body files.
Template supplied by Mentor Graphics.
DESCRIPTION_END
--
-- VHDL Package Body %(library).%(unit)
--
-- Created:
-- by - %(user).%(group) (%(host))
-- at - %(time) %(date)
--
-- using Mentor Graphics HDL Designer(TM) %(version)
--
PACKAGE BODY %(entity_name) IS
END %(entity_name);

Some files were not shown because too many files have changed in this diff Show More