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536477d656
...
8a64f5c04b
@ -18,123 +18,16 @@
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-- 00, data register provides the values detected on the lines.
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--
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ARCHITECTURE studentVersion OF ahbGpio IS
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signal addresses: unsigned(hAddr'range);
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signal bRead: std_ulogic;
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signal bWrite: std_ulogic;
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signal bDone: std_ulogic;
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BEGIN
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process(hReset_n, hClk) begin
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if hReset_n = '0' then
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-- AHB-Lite
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--hRData <= (OTHERS => 'Z');
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hRData <= (OTHERS => '0');
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hReady <= '1';
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hReady <= '0';
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hResp <= '0';
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-- Out
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ioOut <= (OTHERS => '0');
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ioEn <= (OTHERS => '0');
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addresses <= (OTHERS => '0');
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bRead <= '0';
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bWrite <= '0';
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bDone <= '0';
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elsif rising_edge(hClk) then
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if hSel = '1' then
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bWrite <= hWrite;
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bRead <= not hWrite;
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addresses <= hAddr;
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hReady <= '0';
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bDone <= '0';
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else
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bWrite <= '0';
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bRead <= '0';
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end if;
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if bRead = '1' and bWrite = '0' then
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-------------------------------------------------------------------------
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-- READ
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-------------------------------------------------------------------------
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if addresses = "00" then
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-- ##### Read data register #####
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--hRData <= unsigned(resize(ioIn, ioNb));
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for i in 0 to ioNb-1 loop
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hRData(i) <= ioIn(i);
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end loop;
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bDone <= '1';
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elsif addresses = "01" then
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report "@@@@@@@@@@ Not possible to change output in READ mode @@@@@@@@@@" severity error;
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end if;
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elsif bRead = '0' and bWrite = '1' then
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-------------------------------------------------------------------------
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-- WRITE
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-------------------------------------------------------------------------
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if addresses = "00" then
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-- ##### Write data register #####
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--ioOut <= resize(std_ulogic_vector(hWData), ioNb);
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for i in 0 to ioNb-1 loop
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ioOut(i) <= hWData(i);
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end loop;
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bDone <= '1';
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elsif addresses = "01" then
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-- ##### Write direction register #####
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--ioEn <= hWData;
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for i in 0 to ioNb-1 loop
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ioEn(i) <= hWData(i);
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end loop;
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bDone <= '1';
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end if;
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elsif bRead = '1' and bWrite = '1' then
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-------------------------------------------------------------------------
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-- SHOULD NEVER HAPPEN
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-------------------------------------------------------------------------
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report "@@@@@@@@@@ READ and WRITE can't happened in same time @@@@@@@@@@" severity error;
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end if;
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if (ioIn and ioEn) = (ioEn and ioOut) then
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hResp <= '0';
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else
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hResp <= '1';
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end if;
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if bDone = '1' then
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--hRData <= (OTHERS => 'Z');
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bDone <= '0';
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hReady <= '1';
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end if;
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end if;
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for i in (ioNb-1) downto 0 loop
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if (ioEn(i) and ioIn(i)) /= (ioEn(i) and ioOut(i)) then
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--ioEn(i) <= '0';
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report "an output was in conflict" severity note;
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end if;
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end loop;
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end process;
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-- AHB-Lite
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-- hRData <= (OTHERS => '0');
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-- hReady <= '0';
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-- hResp <= '0';
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-- Out
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-- ioOut <= (OTHERS => '0');
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-- ioEn <= (OTHERS => '0');
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END ARCHITECTURE studentVersion;
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@ -1,38 +0,0 @@
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-- VHDL Entity AhbLiteComponents.ahbGpio.symbol
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--
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-- Created:
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-- by - remi.heredero.UNKNOWN (WE2330808)
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-- at - 15:08:33 23.02.2024
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--
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-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5)
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--
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LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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USE ieee.numeric_std.all;
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LIBRARY AhbLite;
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USE AhbLite.ahbLite.all;
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ENTITY ahbGpio IS
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GENERIC(
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ioNb : positive := 8
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);
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PORT(
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hAddr : IN unsigned ( ahbAddressBitNb-1 DOWNTO 0 );
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hClk : IN std_uLogic;
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hReset_n : IN std_uLogic;
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hSel : IN std_uLogic;
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hTrans : IN std_ulogic_vector (ahbTransBitNb-1 DOWNTO 0);
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hWData : IN std_ulogic_vector (ahbDataBitNb-1 DOWNTO 0);
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hWrite : IN std_uLogic;
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ioIn : IN std_ulogic_vector (ioNb-1 DOWNTO 0);
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hRData : OUT std_ulogic_vector (ahbDataBitNb-1 DOWNTO 0);
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hReady : OUT std_uLogic;
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hResp : OUT std_uLogic;
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ioEn : OUT std_ulogic_vector (ioNb-1 DOWNTO 0);
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ioOut : OUT std_ulogic_vector (ioNb-1 DOWNTO 0)
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);
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-- Declarations
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END ahbGpio ;
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@ -1,38 +0,0 @@
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-- VHDL Entity AhbLiteComponents.ahbUart.symbol
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--
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-- Created:
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||||
-- by - remi.heredero.UNKNOWN (WE2330808)
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||||
-- at - 15:08:33 23.02.2024
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--
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-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5)
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||||
--
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LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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USE ieee.numeric_std.all;
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LIBRARY AhbLite;
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USE AhbLite.ahbLite.all;
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ENTITY ahbUart IS
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GENERIC(
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txFifoDepth : positive := 8;
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rxFifoDepth : positive := 1
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);
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PORT(
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RxD : IN std_ulogic;
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hAddr : IN unsigned ( ahbAddressBitNb-1 DOWNTO 0 );
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hClk : IN std_uLogic;
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hReset_n : IN std_uLogic;
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hSel : IN std_uLogic;
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hTrans : IN std_ulogic_vector (ahbTransBitNb-1 DOWNTO 0);
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hWData : IN std_ulogic_vector (ahbDataBitNb-1 DOWNTO 0);
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hWrite : IN std_uLogic;
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TxD : OUT std_ulogic;
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hRData : OUT std_ulogic_vector (ahbDataBitNb-1 DOWNTO 0);
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hReady : OUT std_uLogic;
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hResp : OUT std_uLogic
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||||
);
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||||
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-- Declarations
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||||
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||||
END ahbUart ;
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Binary file not shown.
@ -1,54 +0,0 @@
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DESIGN ahb@gpio
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VIEW symbol.sb
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NO_GRAPHIC 0
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DESIGN ahb@gpio
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VIEW symbol.sb
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GRAPHIC 104,0 8 0
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||||
DESIGN ahb@gpio
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||||
VIEW symbol.sb
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||||
GRAPHIC 13,0 15 1
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DESIGN ahb@gpio
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||||
VIEW symbol.sb
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GRAPHIC 2452,0 19 0
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||||
DESIGN ahb@gpio
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||||
VIEW symbol.sb
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||||
GRAPHIC 2514,0 20 0
|
||||
DESIGN ahb@gpio
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||||
VIEW symbol.sb
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GRAPHIC 2519,0 21 0
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||||
DESIGN ahb@gpio
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||||
VIEW symbol.sb
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||||
GRAPHIC 2692,0 22 0
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||||
DESIGN ahb@gpio
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||||
VIEW symbol.sb
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GRAPHIC 2494,0 23 0
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||||
DESIGN ahb@gpio
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||||
VIEW symbol.sb
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GRAPHIC 2464,0 24 0
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DESIGN ahb@gpio
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VIEW symbol.sb
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GRAPHIC 2474,0 25 0
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DESIGN ahb@gpio
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||||
VIEW symbol.sb
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GRAPHIC 2839,0 26 0
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||||
DESIGN ahb@gpio
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||||
VIEW symbol.sb
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||||
GRAPHIC 2469,0 27 0
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||||
DESIGN ahb@gpio
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||||
VIEW symbol.sb
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||||
GRAPHIC 2504,0 28 0
|
||||
DESIGN ahb@gpio
|
||||
VIEW symbol.sb
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||||
GRAPHIC 2509,0 29 0
|
||||
DESIGN ahb@gpio
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||||
VIEW symbol.sb
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||||
GRAPHIC 2846,0 30 0
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||||
DESIGN ahb@gpio
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||||
VIEW symbol.sb
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||||
GRAPHIC 2651,0 31 0
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||||
DESIGN ahb@gpio
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VIEW symbol.sb
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GRAPHIC 1,0 34 0
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||||
DESIGN ahb@gpio
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||||
VIEW symbol.sb
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||||
GRAPHIC 1,0 35 0
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||||
@ -1,51 +0,0 @@
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||||
DESIGN ahb@uart
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||||
VIEW symbol.sb
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||||
NO_GRAPHIC 0
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||||
DESIGN ahb@uart
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||||
VIEW symbol.sb
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||||
GRAPHIC 104,0 8 0
|
||||
DESIGN ahb@uart
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||||
VIEW symbol.sb
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||||
GRAPHIC 13,0 15 1
|
||||
DESIGN ahb@uart
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||||
VIEW symbol.sb
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||||
GRAPHIC 2839,0 20 0
|
||||
DESIGN ahb@uart
|
||||
VIEW symbol.sb
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||||
GRAPHIC 2452,0 21 0
|
||||
DESIGN ahb@uart
|
||||
VIEW symbol.sb
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||||
GRAPHIC 2514,0 22 0
|
||||
DESIGN ahb@uart
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 2519,0 23 0
|
||||
DESIGN ahb@uart
|
||||
VIEW symbol.sb
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||||
GRAPHIC 2692,0 24 0
|
||||
DESIGN ahb@uart
|
||||
VIEW symbol.sb
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||||
GRAPHIC 2494,0 25 0
|
||||
DESIGN ahb@uart
|
||||
VIEW symbol.sb
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||||
GRAPHIC 2464,0 26 0
|
||||
DESIGN ahb@uart
|
||||
VIEW symbol.sb
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||||
GRAPHIC 2474,0 27 0
|
||||
DESIGN ahb@uart
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 2651,0 28 0
|
||||
DESIGN ahb@uart
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 2469,0 29 0
|
||||
DESIGN ahb@uart
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 2504,0 30 0
|
||||
DESIGN ahb@uart
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 2509,0 31 0
|
||||
DESIGN ahb@uart
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 1,0 34 0
|
||||
DESIGN ahb@uart
|
||||
VIEW symbol.sb
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||||
GRAPHIC 1,0 35 0
|
||||
@ -1,15 +0,0 @@
|
||||
-- VHDL Entity AhbLiteComponents_test.ahbGpio_tb.symbol
|
||||
--
|
||||
-- Created:
|
||||
-- by - axel.amand.UNKNOWN (WE7860)
|
||||
-- at - 14:51:39 28.04.2023
|
||||
--
|
||||
-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5)
|
||||
--
|
||||
|
||||
|
||||
ENTITY ahbGpio_tb IS
|
||||
-- Declarations
|
||||
|
||||
END ahbGpio_tb ;
|
||||
|
||||
@ -1,148 +0,0 @@
|
||||
--
|
||||
-- VHDL Architecture AhbLiteComponents_test.ahbGpio_tb.struct
|
||||
--
|
||||
-- Created:
|
||||
-- by - remi.heredero.UNKNOWN (WE2330808)
|
||||
-- at - 14:16:25 19.04.2024
|
||||
--
|
||||
-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5)
|
||||
--
|
||||
LIBRARY ieee;
|
||||
USE ieee.std_logic_1164.all;
|
||||
USE ieee.numeric_std.all;
|
||||
LIBRARY AhbLite;
|
||||
USE AhbLite.ahbLite.all;
|
||||
|
||||
LIBRARY AhbLiteComponents;
|
||||
LIBRARY AhbLiteComponents_test;
|
||||
|
||||
ARCHITECTURE struct OF ahbGpio_tb IS
|
||||
|
||||
-- Architecture declarations
|
||||
constant ioNb: positive := 8;
|
||||
|
||||
constant clockFrequency : real := 60.0E6;
|
||||
--constant clockFrequency : real := 66.0E6;
|
||||
|
||||
-- Internal signal declarations
|
||||
SIGNAL hAddr : unsigned( ahbAddressBitNb-1 DOWNTO 0 );
|
||||
SIGNAL hClk : std_uLogic;
|
||||
SIGNAL hRData : std_ulogic_vector(ahbDataBitNb-1 DOWNTO 0);
|
||||
SIGNAL hReady : std_uLogic;
|
||||
SIGNAL hReset_n : std_uLogic;
|
||||
SIGNAL hResp : std_uLogic;
|
||||
SIGNAL hSel : std_uLogic;
|
||||
SIGNAL hTrans : std_ulogic_vector(ahbTransBitNb-1 DOWNTO 0);
|
||||
SIGNAL hWData : std_ulogic_vector(ahbDataBitNb-1 DOWNTO 0);
|
||||
SIGNAL hWrite : std_uLogic;
|
||||
SIGNAL io : std_logic_vector(ioNb-1 DOWNTO 0);
|
||||
SIGNAL ioEn : std_ulogic_vector(ioNb-1 DOWNTO 0);
|
||||
SIGNAL ioIn : std_ulogic_vector(ioNb-1 DOWNTO 0);
|
||||
SIGNAL ioOut : std_ulogic_vector(ioNb-1 DOWNTO 0);
|
||||
|
||||
|
||||
-- Component Declarations
|
||||
COMPONENT ahbGpio
|
||||
GENERIC (
|
||||
ioNb : positive := 8
|
||||
);
|
||||
PORT (
|
||||
hAddr : IN unsigned ( ahbAddressBitNb-1 DOWNTO 0 );
|
||||
hClk : IN std_uLogic ;
|
||||
hReset_n : IN std_uLogic ;
|
||||
hSel : IN std_uLogic ;
|
||||
hTrans : IN std_ulogic_vector (ahbTransBitNb-1 DOWNTO 0);
|
||||
hWData : IN std_ulogic_vector (ahbDataBitNb-1 DOWNTO 0);
|
||||
hWrite : IN std_uLogic ;
|
||||
ioIn : IN std_ulogic_vector (ioNb-1 DOWNTO 0);
|
||||
hRData : OUT std_ulogic_vector (ahbDataBitNb-1 DOWNTO 0);
|
||||
hReady : OUT std_uLogic ;
|
||||
hResp : OUT std_uLogic ;
|
||||
ioEn : OUT std_ulogic_vector (ioNb-1 DOWNTO 0);
|
||||
ioOut : OUT std_ulogic_vector (ioNb-1 DOWNTO 0)
|
||||
);
|
||||
END COMPONENT;
|
||||
COMPONENT ahbGpio_tester
|
||||
GENERIC (
|
||||
ioNb : positive;
|
||||
clockFrequency : real
|
||||
);
|
||||
PORT (
|
||||
hRData : IN std_ulogic_vector (ahbDataBitNb-1 DOWNTO 0);
|
||||
hReady : IN std_uLogic ;
|
||||
hResp : IN std_uLogic ;
|
||||
hAddr : OUT unsigned ( ahbAddressBitNb-1 DOWNTO 0 );
|
||||
hClk : OUT std_uLogic ;
|
||||
hReset_n : OUT std_uLogic ;
|
||||
hSel : OUT std_uLogic ;
|
||||
hTrans : OUT std_ulogic_vector (ahbTransBitNb-1 DOWNTO 0);
|
||||
hWData : OUT std_ulogic_vector (ahbDataBitNb-1 DOWNTO 0);
|
||||
hWrite : OUT std_uLogic ;
|
||||
io : INOUT std_logic_vector (ioNb-1 DOWNTO 0)
|
||||
);
|
||||
END COMPONENT;
|
||||
|
||||
-- Optional embedded configurations
|
||||
-- pragma synthesis_off
|
||||
FOR ALL : ahbGpio USE ENTITY AhbLiteComponents.ahbGpio;
|
||||
FOR ALL : ahbGpio_tester USE ENTITY AhbLiteComponents_test.ahbGpio_tester;
|
||||
-- pragma synthesis_on
|
||||
|
||||
|
||||
BEGIN
|
||||
-- Architecture concurrent statements
|
||||
-- HDL Embedded Text Block 1 eb1
|
||||
tristate: process(ioEn, ioOut)
|
||||
begin
|
||||
for index in io'range loop
|
||||
if ioEn(index) = '1' then
|
||||
io(index) <= ioOut(index);
|
||||
else
|
||||
io(index) <= 'Z';
|
||||
end if;
|
||||
end loop;
|
||||
end process tristate;
|
||||
|
||||
ioIn <= std_ulogic_vector(io);
|
||||
|
||||
|
||||
-- Instance port mappings.
|
||||
I_DUT : ahbGpio
|
||||
GENERIC MAP (
|
||||
ioNb => ioNb
|
||||
)
|
||||
PORT MAP (
|
||||
hAddr => hAddr,
|
||||
hClk => hClk,
|
||||
hReset_n => hReset_n,
|
||||
hSel => hSel,
|
||||
hTrans => hTrans,
|
||||
hWData => hWData,
|
||||
hWrite => hWrite,
|
||||
ioIn => ioIn,
|
||||
hRData => hRData,
|
||||
hReady => hReady,
|
||||
hResp => hResp,
|
||||
ioEn => ioEn,
|
||||
ioOut => ioOut
|
||||
);
|
||||
I_tester : ahbGpio_tester
|
||||
GENERIC MAP (
|
||||
ioNb => ioNb,
|
||||
clockFrequency => clockFrequency
|
||||
)
|
||||
PORT MAP (
|
||||
hRData => hRData,
|
||||
hReady => hReady,
|
||||
hResp => hResp,
|
||||
hAddr => hAddr,
|
||||
hClk => hClk,
|
||||
hReset_n => hReset_n,
|
||||
hSel => hSel,
|
||||
hTrans => hTrans,
|
||||
hWData => hWData,
|
||||
hWrite => hWrite,
|
||||
io => io
|
||||
);
|
||||
|
||||
END struct;
|
||||
@ -1,37 +0,0 @@
|
||||
-- VHDL Entity AhbLiteComponents_test.ahbGpio_tester.interface
|
||||
--
|
||||
-- Created:
|
||||
-- by - axel.amand.UNKNOWN (WE7860)
|
||||
-- at - 14:51:40 28.04.2023
|
||||
--
|
||||
-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5)
|
||||
--
|
||||
LIBRARY ieee;
|
||||
USE ieee.std_logic_1164.all;
|
||||
USE ieee.numeric_std.all;
|
||||
LIBRARY AhbLite;
|
||||
USE AhbLite.ahbLite.all;
|
||||
|
||||
ENTITY ahbGpio_tester IS
|
||||
GENERIC(
|
||||
ioNb : positive;
|
||||
clockFrequency : real
|
||||
);
|
||||
PORT(
|
||||
hRData : IN std_ulogic_vector (ahbDataBitNb-1 DOWNTO 0);
|
||||
hReady : IN std_uLogic;
|
||||
hResp : IN std_uLogic;
|
||||
hAddr : OUT unsigned ( ahbAddressBitNb-1 DOWNTO 0 );
|
||||
hClk : OUT std_uLogic;
|
||||
hReset_n : OUT std_uLogic;
|
||||
hSel : OUT std_uLogic;
|
||||
hTrans : OUT std_ulogic_vector (ahbTransBitNb-1 DOWNTO 0);
|
||||
hWData : OUT std_ulogic_vector (ahbDataBitNb-1 DOWNTO 0);
|
||||
hWrite : OUT std_uLogic;
|
||||
io : INOUT std_logic_vector (ioNb-1 DOWNTO 0)
|
||||
);
|
||||
|
||||
-- Declarations
|
||||
|
||||
END ahbGpio_tester ;
|
||||
|
||||
@ -1,15 +0,0 @@
|
||||
-- VHDL Entity AhbLiteComponents_test.ahbUart_tb.symbol
|
||||
--
|
||||
-- Created:
|
||||
-- by - zas.UNKNOWN (ZELL)
|
||||
-- at - 17:08:42 02/17/2020
|
||||
--
|
||||
-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5)
|
||||
--
|
||||
|
||||
|
||||
ENTITY ahbUart_tb IS
|
||||
-- Declarations
|
||||
|
||||
END ahbUart_tb ;
|
||||
|
||||
@ -1,132 +0,0 @@
|
||||
--
|
||||
-- VHDL Architecture AhbLiteComponents_test.ahbUart_tb.struct
|
||||
--
|
||||
-- Created:
|
||||
-- by - axel.amand.UNKNOWN (WE7860)
|
||||
-- at - 15:07:00 28.04.2023
|
||||
--
|
||||
-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5)
|
||||
--
|
||||
LIBRARY ieee;
|
||||
USE ieee.std_logic_1164.all;
|
||||
USE ieee.numeric_std.all;
|
||||
LIBRARY AhbLite;
|
||||
USE AhbLite.ahbLite.all;
|
||||
|
||||
LIBRARY AhbLiteComponents;
|
||||
LIBRARY AhbLiteComponents_test;
|
||||
|
||||
ARCHITECTURE struct OF ahbUart_tb IS
|
||||
|
||||
-- Architecture declarations
|
||||
constant txFifoDepth: positive := 1;
|
||||
constant rxFifoDepth: positive := 1;
|
||||
|
||||
constant clockFrequency : real := 60.0E6;
|
||||
--constant clockFrequency : real := 66.0E6;
|
||||
|
||||
-- Internal signal declarations
|
||||
SIGNAL RxD : std_ulogic;
|
||||
SIGNAL TxD : std_ulogic;
|
||||
SIGNAL hAddr : unsigned( ahbAddressBitNb-1 DOWNTO 0 );
|
||||
SIGNAL hClk : std_uLogic;
|
||||
SIGNAL hRData : std_ulogic_vector(ahbDataBitNb-1 DOWNTO 0);
|
||||
SIGNAL hReady : std_uLogic;
|
||||
SIGNAL hReset_n : std_uLogic;
|
||||
SIGNAL hResp : std_uLogic;
|
||||
SIGNAL hSel : std_uLogic;
|
||||
SIGNAL hTrans : std_ulogic_vector(ahbTransBitNb-1 DOWNTO 0);
|
||||
SIGNAL hWData : std_ulogic_vector(ahbDataBitNb-1 DOWNTO 0);
|
||||
SIGNAL hWrite : std_uLogic;
|
||||
|
||||
|
||||
-- Component Declarations
|
||||
COMPONENT ahbUart
|
||||
GENERIC (
|
||||
txFifoDepth : positive := 8;
|
||||
rxFifoDepth : positive := 1
|
||||
);
|
||||
PORT (
|
||||
RxD : IN std_ulogic ;
|
||||
hAddr : IN unsigned ( ahbAddressBitNb-1 DOWNTO 0 );
|
||||
hClk : IN std_uLogic ;
|
||||
hReset_n : IN std_uLogic ;
|
||||
hSel : IN std_uLogic ;
|
||||
hTrans : IN std_ulogic_vector (ahbTransBitNb-1 DOWNTO 0);
|
||||
hWData : IN std_ulogic_vector (ahbDataBitNb-1 DOWNTO 0);
|
||||
hWrite : IN std_uLogic ;
|
||||
TxD : OUT std_ulogic ;
|
||||
hRData : OUT std_ulogic_vector (ahbDataBitNb-1 DOWNTO 0);
|
||||
hReady : OUT std_uLogic ;
|
||||
hResp : OUT std_uLogic
|
||||
);
|
||||
END COMPONENT;
|
||||
COMPONENT ahbUart_tester
|
||||
GENERIC (
|
||||
clockFrequency : real
|
||||
);
|
||||
PORT (
|
||||
TxD : IN std_ulogic ;
|
||||
hRData : IN std_ulogic_vector (ahbDataBitNb-1 DOWNTO 0);
|
||||
hReady : IN std_uLogic ;
|
||||
hResp : IN std_uLogic ;
|
||||
RxD : OUT std_ulogic ;
|
||||
hAddr : OUT unsigned ( ahbAddressBitNb-1 DOWNTO 0 );
|
||||
hClk : OUT std_uLogic ;
|
||||
hReset_n : OUT std_uLogic ;
|
||||
hSel : OUT std_uLogic ;
|
||||
hTrans : OUT std_ulogic_vector (ahbTransBitNb-1 DOWNTO 0);
|
||||
hWData : OUT std_ulogic_vector (ahbDataBitNb-1 DOWNTO 0);
|
||||
hWrite : OUT std_uLogic
|
||||
);
|
||||
END COMPONENT;
|
||||
|
||||
-- Optional embedded configurations
|
||||
-- pragma synthesis_off
|
||||
FOR ALL : ahbUart USE ENTITY AhbLiteComponents.ahbUart;
|
||||
FOR ALL : ahbUart_tester USE ENTITY AhbLiteComponents_test.ahbUart_tester;
|
||||
-- pragma synthesis_on
|
||||
|
||||
|
||||
BEGIN
|
||||
|
||||
-- Instance port mappings.
|
||||
I_DUT : ahbUart
|
||||
GENERIC MAP (
|
||||
txFifoDepth => txFifoDepth,
|
||||
rxFifoDepth => rxFifoDepth
|
||||
)
|
||||
PORT MAP (
|
||||
RxD => RxD,
|
||||
hAddr => hAddr,
|
||||
hClk => hClk,
|
||||
hReset_n => hReset_n,
|
||||
hSel => hSel,
|
||||
hTrans => hTrans,
|
||||
hWData => hWData,
|
||||
hWrite => hWrite,
|
||||
TxD => TxD,
|
||||
hRData => hRData,
|
||||
hReady => hReady,
|
||||
hResp => hResp
|
||||
);
|
||||
I_tester : ahbUart_tester
|
||||
GENERIC MAP (
|
||||
clockFrequency => clockFrequency
|
||||
)
|
||||
PORT MAP (
|
||||
TxD => TxD,
|
||||
hRData => hRData,
|
||||
hReady => hReady,
|
||||
hResp => hResp,
|
||||
RxD => RxD,
|
||||
hAddr => hAddr,
|
||||
hClk => hClk,
|
||||
hReset_n => hReset_n,
|
||||
hSel => hSel,
|
||||
hTrans => hTrans,
|
||||
hWData => hWData,
|
||||
hWrite => hWrite
|
||||
);
|
||||
|
||||
END struct;
|
||||
@ -1,37 +0,0 @@
|
||||
-- VHDL Entity AhbLiteComponents_test.ahbUart_tester.interface
|
||||
--
|
||||
-- Created:
|
||||
-- by - zas.UNKNOWN (ZELL)
|
||||
-- at - 17:08:42 02/17/2020
|
||||
--
|
||||
-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5)
|
||||
--
|
||||
LIBRARY ieee;
|
||||
USE ieee.std_logic_1164.all;
|
||||
USE ieee.numeric_std.all;
|
||||
LIBRARY AhbLite;
|
||||
USE AhbLite.ahbLite.all;
|
||||
|
||||
ENTITY ahbUart_tester IS
|
||||
GENERIC(
|
||||
clockFrequency : real
|
||||
);
|
||||
PORT(
|
||||
TxD : IN std_ulogic;
|
||||
hRData : IN std_ulogic_vector (ahbDataBitNb-1 DOWNTO 0);
|
||||
hReady : IN std_uLogic;
|
||||
hResp : IN std_uLogic;
|
||||
RxD : OUT std_ulogic;
|
||||
hAddr : OUT unsigned ( ahbAddressBitNb-1 DOWNTO 0 );
|
||||
hClk : OUT std_uLogic;
|
||||
hReset_n : OUT std_uLogic;
|
||||
hSel : OUT std_uLogic;
|
||||
hTrans : OUT std_ulogic_vector (ahbTransBitNb-1 DOWNTO 0);
|
||||
hWData : OUT std_ulogic_vector (ahbDataBitNb-1 DOWNTO 0);
|
||||
hWrite : OUT std_uLogic
|
||||
);
|
||||
|
||||
-- Declarations
|
||||
|
||||
END ahbUart_tester ;
|
||||
|
||||
Binary file not shown.
@ -1 +1 @@
|
||||
DIALECT atom VHDL_2008
|
||||
DIALECT atom VHDL_ANY
|
||||
|
||||
@ -1 +1 @@
|
||||
DIALECT atom VHDL_2008
|
||||
DIALECT atom VHDL_ANY
|
||||
|
||||
@ -1,12 +0,0 @@
|
||||
DESIGN ahb@gpio_tb
|
||||
VIEW symbol.sb
|
||||
NO_GRAPHIC 0
|
||||
DESIGN ahb@gpio_tb
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 53,0 8 0
|
||||
DESIGN ahb@gpio_tb
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 1,0 11 0
|
||||
DESIGN ahb@gpio_tb
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 1,0 12 0
|
||||
@ -1,228 +0,0 @@
|
||||
DESIGN ahb@gpio_tb
|
||||
VIEW struct.bd
|
||||
NO_GRAPHIC 0
|
||||
DESIGN ahb@gpio_tb
|
||||
VIEW struct.bd
|
||||
GRAPHIC 187,0 9 0
|
||||
DESIGN ahb@gpio_tb
|
||||
VIEW struct.bd
|
||||
NO_GRAPHIC 14
|
||||
DESIGN ahb@gpio_tb
|
||||
VIEW struct.bd
|
||||
GRAPHIC 0,0 18 2
|
||||
DESIGN ahb@gpio_tb
|
||||
VIEW struct.bd
|
||||
GRAPHIC 1,0 21 0
|
||||
DESIGN ahb@gpio_tb
|
||||
VIEW struct.bd
|
||||
NO_GRAPHIC 21
|
||||
DESIGN ahb@gpio_tb
|
||||
VIEW struct.bd
|
||||
GRAPHIC 12627,0 27 0
|
||||
DESIGN ahb@gpio_tb
|
||||
VIEW struct.bd
|
||||
GRAPHIC 12563,0 28 0
|
||||
DESIGN ahb@gpio_tb
|
||||
VIEW struct.bd
|
||||
GRAPHIC 12587,0 29 0
|
||||
DESIGN ahb@gpio_tb
|
||||
VIEW struct.bd
|
||||
GRAPHIC 12579,0 30 0
|
||||
DESIGN ahb@gpio_tb
|
||||
VIEW struct.bd
|
||||
GRAPHIC 12555,0 31 0
|
||||
DESIGN ahb@gpio_tb
|
||||
VIEW struct.bd
|
||||
GRAPHIC 12571,0 32 0
|
||||
DESIGN ahb@gpio_tb
|
||||
VIEW struct.bd
|
||||
GRAPHIC 12595,0 33 0
|
||||
DESIGN ahb@gpio_tb
|
||||
VIEW struct.bd
|
||||
GRAPHIC 12611,0 34 0
|
||||
DESIGN ahb@gpio_tb
|
||||
VIEW struct.bd
|
||||
GRAPHIC 12619,0 35 0
|
||||
DESIGN ahb@gpio_tb
|
||||
VIEW struct.bd
|
||||
GRAPHIC 12603,0 36 0
|
||||
DESIGN ahb@gpio_tb
|
||||
VIEW struct.bd
|
||||
GRAPHIC 13244,0 37 0
|
||||
DESIGN ahb@gpio_tb
|
||||
VIEW struct.bd
|
||||
GRAPHIC 13210,0 38 0
|
||||
DESIGN ahb@gpio_tb
|
||||
VIEW struct.bd
|
||||
GRAPHIC 13226,0 39 0
|
||||
DESIGN ahb@gpio_tb
|
||||
VIEW struct.bd
|
||||
GRAPHIC 13218,0 40 0
|
||||
DESIGN ahb@gpio_tb
|
||||
VIEW struct.bd
|
||||
NO_GRAPHIC 41
|
||||
DESIGN ahb@gpio_tb
|
||||
VIEW struct.bd
|
||||
NO_GRAPHIC 42
|
||||
LIBRARY AhbLiteComponents
|
||||
DESIGN ahb@gpio
|
||||
VIEW student@version
|
||||
GRAPHIC 13194,0 44 0
|
||||
DESIGN ahb@gpio
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 14,0 45 1
|
||||
DESIGN ahb@gpio
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 2452,0 49 0
|
||||
DESIGN ahb@gpio
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 2514,0 50 0
|
||||
DESIGN ahb@gpio
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 2519,0 51 0
|
||||
DESIGN ahb@gpio
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 2692,0 52 0
|
||||
DESIGN ahb@gpio
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 2494,0 53 0
|
||||
DESIGN ahb@gpio
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 2464,0 54 0
|
||||
DESIGN ahb@gpio
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 2474,0 55 0
|
||||
DESIGN ahb@gpio
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 2839,0 56 0
|
||||
DESIGN ahb@gpio
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 2469,0 57 0
|
||||
DESIGN ahb@gpio
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 2504,0 58 0
|
||||
DESIGN ahb@gpio
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 2509,0 59 0
|
||||
DESIGN ahb@gpio
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 2846,0 60 0
|
||||
DESIGN ahb@gpio
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 2651,0 61 0
|
||||
LIBRARY AhbLiteComponents_test
|
||||
DESIGN ahb@gpio_tester
|
||||
VIEW test
|
||||
GRAPHIC 12657,0 64 0
|
||||
DESIGN ahb@gpio_tester
|
||||
VIEW interface
|
||||
GRAPHIC 14,0 65 1
|
||||
DESIGN ahb@gpio_tb
|
||||
VIEW struct.bd
|
||||
GRAPHIC 12589,0 70 0
|
||||
DESIGN ahb@gpio_tb
|
||||
VIEW struct.bd
|
||||
GRAPHIC 12581,0 71 0
|
||||
DESIGN ahb@gpio_tb
|
||||
VIEW struct.bd
|
||||
GRAPHIC 12573,0 72 0
|
||||
DESIGN ahb@gpio_tb
|
||||
VIEW struct.bd
|
||||
GRAPHIC 12629,0 73 0
|
||||
DESIGN ahb@gpio_tb
|
||||
VIEW struct.bd
|
||||
GRAPHIC 12565,0 74 0
|
||||
DESIGN ahb@gpio_tb
|
||||
VIEW struct.bd
|
||||
GRAPHIC 12557,0 75 0
|
||||
DESIGN ahb@gpio_tb
|
||||
VIEW struct.bd
|
||||
GRAPHIC 12597,0 76 0
|
||||
DESIGN ahb@gpio_tb
|
||||
VIEW struct.bd
|
||||
GRAPHIC 12613,0 77 0
|
||||
DESIGN ahb@gpio_tb
|
||||
VIEW struct.bd
|
||||
GRAPHIC 12621,0 78 0
|
||||
DESIGN ahb@gpio_tb
|
||||
VIEW struct.bd
|
||||
GRAPHIC 12605,0 79 0
|
||||
DESIGN ahb@gpio_tb
|
||||
VIEW struct.bd
|
||||
GRAPHIC 13236,0 80 0
|
||||
LIBRARY AhbLiteComponents_test
|
||||
DESIGN ahb@gpio_tb
|
||||
VIEW struct.bd
|
||||
NO_GRAPHIC 83
|
||||
DESIGN ahb@gpio_tb
|
||||
VIEW struct.bd
|
||||
GRAPHIC 13194,0 86 0
|
||||
DESIGN ahb@gpio_tb
|
||||
VIEW struct.bd
|
||||
GRAPHIC 12657,0 87 0
|
||||
DESIGN ahb@gpio_tb
|
||||
VIEW struct.bd
|
||||
NO_GRAPHIC 90
|
||||
DESIGN ahb@gpio_tb
|
||||
VIEW struct.bd
|
||||
GRAPHIC 13204,0 93 0
|
||||
DESIGN ahb@gpio_tb
|
||||
VIEW struct.bd
|
||||
NO_GRAPHIC 106
|
||||
DESIGN ahb@gpio_tb
|
||||
VIEW struct.bd
|
||||
NO_GRAPHIC 107
|
||||
DESIGN ahb@gpio_tb
|
||||
VIEW struct.bd
|
||||
GRAPHIC 13194,0 109 0
|
||||
DESIGN ahb@gpio_tb
|
||||
VIEW struct.bd
|
||||
GRAPHIC 13201,0 110 1
|
||||
DESIGN ahb@gpio_tb
|
||||
VIEW struct.bd
|
||||
GRAPHIC 12629,0 114 0
|
||||
DESIGN ahb@gpio_tb
|
||||
VIEW struct.bd
|
||||
GRAPHIC 12565,0 115 0
|
||||
DESIGN ahb@gpio_tb
|
||||
VIEW struct.bd
|
||||
GRAPHIC 12557,0 116 0
|
||||
DESIGN ahb@gpio_tb
|
||||
VIEW struct.bd
|
||||
GRAPHIC 12597,0 117 0
|
||||
DESIGN ahb@gpio_tb
|
||||
VIEW struct.bd
|
||||
GRAPHIC 12613,0 118 0
|
||||
DESIGN ahb@gpio_tb
|
||||
VIEW struct.bd
|
||||
GRAPHIC 12621,0 119 0
|
||||
DESIGN ahb@gpio_tb
|
||||
VIEW struct.bd
|
||||
GRAPHIC 12605,0 120 0
|
||||
DESIGN ahb@gpio_tb
|
||||
VIEW struct.bd
|
||||
GRAPHIC 13228,0 121 0
|
||||
DESIGN ahb@gpio_tb
|
||||
VIEW struct.bd
|
||||
GRAPHIC 12589,0 122 0
|
||||
DESIGN ahb@gpio_tb
|
||||
VIEW struct.bd
|
||||
GRAPHIC 12581,0 123 0
|
||||
DESIGN ahb@gpio_tb
|
||||
VIEW struct.bd
|
||||
GRAPHIC 12573,0 124 0
|
||||
DESIGN ahb@gpio_tb
|
||||
VIEW struct.bd
|
||||
GRAPHIC 13212,0 125 0
|
||||
DESIGN ahb@gpio_tb
|
||||
VIEW struct.bd
|
||||
GRAPHIC 13220,0 126 0
|
||||
DESIGN ahb@gpio_tb
|
||||
VIEW struct.bd
|
||||
GRAPHIC 12657,0 128 0
|
||||
DESIGN ahb@gpio_tb
|
||||
VIEW struct.bd
|
||||
GRAPHIC 12664,0 129 1
|
||||
DESIGN ahb@gpio_tb
|
||||
VIEW struct.bd
|
||||
NO_GRAPHIC 147
|
||||
@ -1,48 +0,0 @@
|
||||
DESIGN ahb@gpio_tester
|
||||
VIEW interface
|
||||
NO_GRAPHIC 0
|
||||
DESIGN ahb@gpio_tester
|
||||
VIEW interface
|
||||
GRAPHIC 50,0 8 0
|
||||
DESIGN ahb@gpio_tester
|
||||
VIEW interface
|
||||
GRAPHIC 13,0 15 1
|
||||
DESIGN ahb@gpio_tester
|
||||
VIEW interface
|
||||
GRAPHIC 668,0 20 0
|
||||
DESIGN ahb@gpio_tester
|
||||
VIEW interface
|
||||
GRAPHIC 673,0 21 0
|
||||
DESIGN ahb@gpio_tester
|
||||
VIEW interface
|
||||
GRAPHIC 683,0 22 0
|
||||
DESIGN ahb@gpio_tester
|
||||
VIEW interface
|
||||
GRAPHIC 658,0 23 0
|
||||
DESIGN ahb@gpio_tester
|
||||
VIEW interface
|
||||
GRAPHIC 663,0 24 0
|
||||
DESIGN ahb@gpio_tester
|
||||
VIEW interface
|
||||
GRAPHIC 678,0 25 0
|
||||
DESIGN ahb@gpio_tester
|
||||
VIEW interface
|
||||
GRAPHIC 688,0 26 0
|
||||
DESIGN ahb@gpio_tester
|
||||
VIEW interface
|
||||
GRAPHIC 693,0 27 0
|
||||
DESIGN ahb@gpio_tester
|
||||
VIEW interface
|
||||
GRAPHIC 698,0 28 0
|
||||
DESIGN ahb@gpio_tester
|
||||
VIEW interface
|
||||
GRAPHIC 703,0 29 0
|
||||
DESIGN ahb@gpio_tester
|
||||
VIEW interface
|
||||
GRAPHIC 708,0 30 0
|
||||
DESIGN ahb@gpio_tester
|
||||
VIEW interface
|
||||
GRAPHIC 1,0 33 0
|
||||
DESIGN ahb@gpio_tester
|
||||
VIEW interface
|
||||
GRAPHIC 1,0 34 0
|
||||
@ -1,12 +0,0 @@
|
||||
DESIGN ahb@uart_tb
|
||||
VIEW symbol.sb
|
||||
NO_GRAPHIC 0
|
||||
DESIGN ahb@uart_tb
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 53,0 8 0
|
||||
DESIGN ahb@uart_tb
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 1,0 11 0
|
||||
DESIGN ahb@uart_tb
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 1,0 12 0
|
||||
@ -1,213 +0,0 @@
|
||||
DESIGN ahb@uart_tb
|
||||
VIEW struct.bd
|
||||
NO_GRAPHIC 0
|
||||
DESIGN ahb@uart_tb
|
||||
VIEW struct.bd
|
||||
GRAPHIC 187,0 9 0
|
||||
DESIGN ahb@uart_tb
|
||||
VIEW struct.bd
|
||||
NO_GRAPHIC 14
|
||||
DESIGN ahb@uart_tb
|
||||
VIEW struct.bd
|
||||
GRAPHIC 0,0 18 2
|
||||
DESIGN ahb@uart_tb
|
||||
VIEW struct.bd
|
||||
GRAPHIC 1,0 21 0
|
||||
DESIGN ahb@uart_tb
|
||||
VIEW struct.bd
|
||||
NO_GRAPHIC 21
|
||||
DESIGN ahb@uart_tb
|
||||
VIEW struct.bd
|
||||
GRAPHIC 13297,0 28 0
|
||||
DESIGN ahb@uart_tb
|
||||
VIEW struct.bd
|
||||
GRAPHIC 13305,0 29 0
|
||||
DESIGN ahb@uart_tb
|
||||
VIEW struct.bd
|
||||
GRAPHIC 12627,0 30 0
|
||||
DESIGN ahb@uart_tb
|
||||
VIEW struct.bd
|
||||
GRAPHIC 12563,0 31 0
|
||||
DESIGN ahb@uart_tb
|
||||
VIEW struct.bd
|
||||
GRAPHIC 12587,0 32 0
|
||||
DESIGN ahb@uart_tb
|
||||
VIEW struct.bd
|
||||
GRAPHIC 12579,0 33 0
|
||||
DESIGN ahb@uart_tb
|
||||
VIEW struct.bd
|
||||
GRAPHIC 12555,0 34 0
|
||||
DESIGN ahb@uart_tb
|
||||
VIEW struct.bd
|
||||
GRAPHIC 12571,0 35 0
|
||||
DESIGN ahb@uart_tb
|
||||
VIEW struct.bd
|
||||
GRAPHIC 12595,0 36 0
|
||||
DESIGN ahb@uart_tb
|
||||
VIEW struct.bd
|
||||
GRAPHIC 12611,0 37 0
|
||||
DESIGN ahb@uart_tb
|
||||
VIEW struct.bd
|
||||
GRAPHIC 12619,0 38 0
|
||||
DESIGN ahb@uart_tb
|
||||
VIEW struct.bd
|
||||
GRAPHIC 12603,0 39 0
|
||||
DESIGN ahb@uart_tb
|
||||
VIEW struct.bd
|
||||
NO_GRAPHIC 40
|
||||
DESIGN ahb@uart_tb
|
||||
VIEW struct.bd
|
||||
NO_GRAPHIC 41
|
||||
LIBRARY AhbLiteComponents
|
||||
DESIGN ahb@uart
|
||||
VIEW student@version
|
||||
GRAPHIC 13707,0 43 0
|
||||
DESIGN ahb@uart
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 14,0 44 1
|
||||
DESIGN ahb@uart
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 2839,0 49 0
|
||||
DESIGN ahb@uart
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 2452,0 50 0
|
||||
DESIGN ahb@uart
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 2514,0 51 0
|
||||
DESIGN ahb@uart
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 2519,0 52 0
|
||||
DESIGN ahb@uart
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 2692,0 53 0
|
||||
DESIGN ahb@uart
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 2494,0 54 0
|
||||
DESIGN ahb@uart
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 2464,0 55 0
|
||||
DESIGN ahb@uart
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 2474,0 56 0
|
||||
DESIGN ahb@uart
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 2651,0 57 0
|
||||
DESIGN ahb@uart
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 2469,0 58 0
|
||||
DESIGN ahb@uart
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 2504,0 59 0
|
||||
DESIGN ahb@uart
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 2509,0 60 0
|
||||
LIBRARY AhbLiteComponents_test
|
||||
DESIGN ahb@uart_tester
|
||||
VIEW test
|
||||
GRAPHIC 12657,0 63 0
|
||||
DESIGN ahb@uart_tester
|
||||
VIEW interface
|
||||
GRAPHIC 14,0 64 1
|
||||
DESIGN ahb@uart_tb
|
||||
VIEW struct.bd
|
||||
GRAPHIC 13307,0 68 0
|
||||
DESIGN ahb@uart_tb
|
||||
VIEW struct.bd
|
||||
GRAPHIC 12589,0 69 0
|
||||
DESIGN ahb@uart_tb
|
||||
VIEW struct.bd
|
||||
GRAPHIC 12581,0 70 0
|
||||
DESIGN ahb@uart_tb
|
||||
VIEW struct.bd
|
||||
GRAPHIC 12573,0 71 0
|
||||
DESIGN ahb@uart_tb
|
||||
VIEW struct.bd
|
||||
GRAPHIC 13299,0 72 0
|
||||
DESIGN ahb@uart_tb
|
||||
VIEW struct.bd
|
||||
GRAPHIC 12629,0 73 0
|
||||
DESIGN ahb@uart_tb
|
||||
VIEW struct.bd
|
||||
GRAPHIC 12565,0 74 0
|
||||
DESIGN ahb@uart_tb
|
||||
VIEW struct.bd
|
||||
GRAPHIC 12557,0 75 0
|
||||
DESIGN ahb@uart_tb
|
||||
VIEW struct.bd
|
||||
GRAPHIC 12597,0 76 0
|
||||
DESIGN ahb@uart_tb
|
||||
VIEW struct.bd
|
||||
GRAPHIC 12613,0 77 0
|
||||
DESIGN ahb@uart_tb
|
||||
VIEW struct.bd
|
||||
GRAPHIC 12621,0 78 0
|
||||
DESIGN ahb@uart_tb
|
||||
VIEW struct.bd
|
||||
GRAPHIC 12605,0 79 0
|
||||
LIBRARY AhbLiteComponents_test
|
||||
DESIGN ahb@uart_tb
|
||||
VIEW struct.bd
|
||||
NO_GRAPHIC 82
|
||||
DESIGN ahb@uart_tb
|
||||
VIEW struct.bd
|
||||
GRAPHIC 13707,0 85 0
|
||||
DESIGN ahb@uart_tb
|
||||
VIEW struct.bd
|
||||
GRAPHIC 12657,0 86 0
|
||||
DESIGN ahb@uart_tb
|
||||
VIEW struct.bd
|
||||
NO_GRAPHIC 89
|
||||
DESIGN ahb@uart_tb
|
||||
VIEW struct.bd
|
||||
NO_GRAPHIC 91
|
||||
DESIGN ahb@uart_tb
|
||||
VIEW struct.bd
|
||||
GRAPHIC 13707,0 93 0
|
||||
DESIGN ahb@uart_tb
|
||||
VIEW struct.bd
|
||||
GRAPHIC 13714,0 94 1
|
||||
DESIGN ahb@uart_tb
|
||||
VIEW struct.bd
|
||||
GRAPHIC 13299,0 99 0
|
||||
DESIGN ahb@uart_tb
|
||||
VIEW struct.bd
|
||||
GRAPHIC 12629,0 100 0
|
||||
DESIGN ahb@uart_tb
|
||||
VIEW struct.bd
|
||||
GRAPHIC 12565,0 101 0
|
||||
DESIGN ahb@uart_tb
|
||||
VIEW struct.bd
|
||||
GRAPHIC 12557,0 102 0
|
||||
DESIGN ahb@uart_tb
|
||||
VIEW struct.bd
|
||||
GRAPHIC 12597,0 103 0
|
||||
DESIGN ahb@uart_tb
|
||||
VIEW struct.bd
|
||||
GRAPHIC 12613,0 104 0
|
||||
DESIGN ahb@uart_tb
|
||||
VIEW struct.bd
|
||||
GRAPHIC 12621,0 105 0
|
||||
DESIGN ahb@uart_tb
|
||||
VIEW struct.bd
|
||||
GRAPHIC 12605,0 106 0
|
||||
DESIGN ahb@uart_tb
|
||||
VIEW struct.bd
|
||||
GRAPHIC 13307,0 107 0
|
||||
DESIGN ahb@uart_tb
|
||||
VIEW struct.bd
|
||||
GRAPHIC 12589,0 108 0
|
||||
DESIGN ahb@uart_tb
|
||||
VIEW struct.bd
|
||||
GRAPHIC 12581,0 109 0
|
||||
DESIGN ahb@uart_tb
|
||||
VIEW struct.bd
|
||||
GRAPHIC 12573,0 110 0
|
||||
DESIGN ahb@uart_tb
|
||||
VIEW struct.bd
|
||||
GRAPHIC 12657,0 112 0
|
||||
DESIGN ahb@uart_tb
|
||||
VIEW struct.bd
|
||||
GRAPHIC 12664,0 113 1
|
||||
DESIGN ahb@uart_tb
|
||||
VIEW struct.bd
|
||||
NO_GRAPHIC 131
|
||||
@ -1,51 +0,0 @@
|
||||
DESIGN ahb@uart_tester
|
||||
VIEW interface
|
||||
NO_GRAPHIC 0
|
||||
DESIGN ahb@uart_tester
|
||||
VIEW interface
|
||||
GRAPHIC 50,0 8 0
|
||||
DESIGN ahb@uart_tester
|
||||
VIEW interface
|
||||
GRAPHIC 13,0 15 1
|
||||
DESIGN ahb@uart_tester
|
||||
VIEW interface
|
||||
GRAPHIC 1269,0 19 0
|
||||
DESIGN ahb@uart_tester
|
||||
VIEW interface
|
||||
GRAPHIC 1224,0 20 0
|
||||
DESIGN ahb@uart_tester
|
||||
VIEW interface
|
||||
GRAPHIC 1229,0 21 0
|
||||
DESIGN ahb@uart_tester
|
||||
VIEW interface
|
||||
GRAPHIC 1239,0 22 0
|
||||
DESIGN ahb@uart_tester
|
||||
VIEW interface
|
||||
GRAPHIC 1264,0 23 0
|
||||
DESIGN ahb@uart_tester
|
||||
VIEW interface
|
||||
GRAPHIC 1214,0 24 0
|
||||
DESIGN ahb@uart_tester
|
||||
VIEW interface
|
||||
GRAPHIC 1219,0 25 0
|
||||
DESIGN ahb@uart_tester
|
||||
VIEW interface
|
||||
GRAPHIC 1234,0 26 0
|
||||
DESIGN ahb@uart_tester
|
||||
VIEW interface
|
||||
GRAPHIC 1244,0 27 0
|
||||
DESIGN ahb@uart_tester
|
||||
VIEW interface
|
||||
GRAPHIC 1249,0 28 0
|
||||
DESIGN ahb@uart_tester
|
||||
VIEW interface
|
||||
GRAPHIC 1254,0 29 0
|
||||
DESIGN ahb@uart_tester
|
||||
VIEW interface
|
||||
GRAPHIC 1259,0 30 0
|
||||
DESIGN ahb@uart_tester
|
||||
VIEW interface
|
||||
GRAPHIC 1,0 33 0
|
||||
DESIGN ahb@uart_tester
|
||||
VIEW interface
|
||||
GRAPHIC 1,0 34 0
|
||||
@ -74,23 +74,23 @@ value " "
|
||||
)
|
||||
(vvPair
|
||||
variable "HDLDir"
|
||||
value "C:\\Users\\remi.heredero\\GIT\\2024-sem-labs-herederoremi\\06-07-08-09-SystemOnChip\\Prefs\\..\\AhbLiteComponents_test\\hdl"
|
||||
value "C:\\dev\\sem-labs\\06-07-08-09-SystemOnChip\\Prefs\\..\\AhbLiteComponents_test\\hdl"
|
||||
)
|
||||
(vvPair
|
||||
variable "HDSDir"
|
||||
value "C:\\Users\\remi.heredero\\GIT\\2024-sem-labs-herederoremi\\06-07-08-09-SystemOnChip\\Prefs\\..\\AhbLiteComponents_test\\hds"
|
||||
value "C:\\dev\\sem-labs\\06-07-08-09-SystemOnChip\\Prefs\\..\\AhbLiteComponents_test\\hds"
|
||||
)
|
||||
(vvPair
|
||||
variable "SideDataDesignDir"
|
||||
value "C:\\Users\\remi.heredero\\GIT\\2024-sem-labs-herederoremi\\06-07-08-09-SystemOnChip\\Prefs\\..\\AhbLiteComponents_test\\hds\\ahb@gpio_tb\\struct.bd.info"
|
||||
value "C:\\dev\\sem-labs\\06-07-08-09-SystemOnChip\\Prefs\\..\\AhbLiteComponents_test\\hds\\ahb@gpio_tb\\struct.bd.info"
|
||||
)
|
||||
(vvPair
|
||||
variable "SideDataUserDir"
|
||||
value "C:\\Users\\remi.heredero\\GIT\\2024-sem-labs-herederoremi\\06-07-08-09-SystemOnChip\\Prefs\\..\\AhbLiteComponents_test\\hds\\ahb@gpio_tb\\struct.bd.user"
|
||||
value "C:\\dev\\sem-labs\\06-07-08-09-SystemOnChip\\Prefs\\..\\AhbLiteComponents_test\\hds\\ahb@gpio_tb\\struct.bd.user"
|
||||
)
|
||||
(vvPair
|
||||
variable "SourceDir"
|
||||
value "C:\\Users\\remi.heredero\\GIT\\2024-sem-labs-herederoremi\\06-07-08-09-SystemOnChip\\Prefs\\..\\AhbLiteComponents_test\\hds"
|
||||
value "C:\\dev\\sem-labs\\06-07-08-09-SystemOnChip\\Prefs\\..\\AhbLiteComponents_test\\hds"
|
||||
)
|
||||
(vvPair
|
||||
variable "appl"
|
||||
@ -114,15 +114,15 @@ value "%(unit)_%(view)_config"
|
||||
)
|
||||
(vvPair
|
||||
variable "d"
|
||||
value "C:\\Users\\remi.heredero\\GIT\\2024-sem-labs-herederoremi\\06-07-08-09-SystemOnChip\\Prefs\\..\\AhbLiteComponents_test\\hds\\ahb@gpio_tb"
|
||||
value "C:\\dev\\sem-labs\\06-07-08-09-SystemOnChip\\Prefs\\..\\AhbLiteComponents_test\\hds\\ahb@gpio_tb"
|
||||
)
|
||||
(vvPair
|
||||
variable "d_logical"
|
||||
value "C:\\Users\\remi.heredero\\GIT\\2024-sem-labs-herederoremi\\06-07-08-09-SystemOnChip\\Prefs\\..\\AhbLiteComponents_test\\hds\\ahbGpio_tb"
|
||||
value "C:\\dev\\sem-labs\\06-07-08-09-SystemOnChip\\Prefs\\..\\AhbLiteComponents_test\\hds\\ahbGpio_tb"
|
||||
)
|
||||
(vvPair
|
||||
variable "date"
|
||||
value "19.04.2024"
|
||||
value "28.04.2023"
|
||||
)
|
||||
(vvPair
|
||||
variable "day"
|
||||
@ -134,7 +134,7 @@ value "vendredi"
|
||||
)
|
||||
(vvPair
|
||||
variable "dd"
|
||||
value "19"
|
||||
value "28"
|
||||
)
|
||||
(vvPair
|
||||
variable "designName"
|
||||
@ -162,11 +162,11 @@ value "struct"
|
||||
)
|
||||
(vvPair
|
||||
variable "graphical_source_author"
|
||||
value "remi.heredero"
|
||||
value "axel.amand"
|
||||
)
|
||||
(vvPair
|
||||
variable "graphical_source_date"
|
||||
value "19.04.2024"
|
||||
value "28.04.2023"
|
||||
)
|
||||
(vvPair
|
||||
variable "graphical_source_group"
|
||||
@ -174,11 +174,11 @@ value "UNKNOWN"
|
||||
)
|
||||
(vvPair
|
||||
variable "graphical_source_host"
|
||||
value "WE2330808"
|
||||
value "WE7860"
|
||||
)
|
||||
(vvPair
|
||||
variable "graphical_source_time"
|
||||
value "14:16:25"
|
||||
value "15:06:49"
|
||||
)
|
||||
(vvPair
|
||||
variable "group"
|
||||
@ -186,7 +186,7 @@ value "UNKNOWN"
|
||||
)
|
||||
(vvPair
|
||||
variable "host"
|
||||
value "WE2330808"
|
||||
value "WE7860"
|
||||
)
|
||||
(vvPair
|
||||
variable "language"
|
||||
@ -222,11 +222,11 @@ value "avril"
|
||||
)
|
||||
(vvPair
|
||||
variable "p"
|
||||
value "C:\\Users\\remi.heredero\\GIT\\2024-sem-labs-herederoremi\\06-07-08-09-SystemOnChip\\Prefs\\..\\AhbLiteComponents_test\\hds\\ahb@gpio_tb\\struct.bd"
|
||||
value "C:\\dev\\sem-labs\\06-07-08-09-SystemOnChip\\Prefs\\..\\AhbLiteComponents_test\\hds\\ahb@gpio_tb\\struct.bd"
|
||||
)
|
||||
(vvPair
|
||||
variable "p_logical"
|
||||
value "C:\\Users\\remi.heredero\\GIT\\2024-sem-labs-herederoremi\\06-07-08-09-SystemOnChip\\Prefs\\..\\AhbLiteComponents_test\\hds\\ahbGpio_tb\\struct.bd"
|
||||
value "C:\\dev\\sem-labs\\06-07-08-09-SystemOnChip\\Prefs\\..\\AhbLiteComponents_test\\hds\\ahbGpio_tb\\struct.bd"
|
||||
)
|
||||
(vvPair
|
||||
variable "package_name"
|
||||
@ -306,7 +306,7 @@ value "struct"
|
||||
)
|
||||
(vvPair
|
||||
variable "time"
|
||||
value "14:16:25"
|
||||
value "15:06:49"
|
||||
)
|
||||
(vvPair
|
||||
variable "unit"
|
||||
@ -314,7 +314,7 @@ value "ahbGpio_tb"
|
||||
)
|
||||
(vvPair
|
||||
variable "user"
|
||||
value "remi.heredero"
|
||||
value "axel.amand"
|
||||
)
|
||||
(vvPair
|
||||
variable "version"
|
||||
@ -326,11 +326,11 @@ value "struct"
|
||||
)
|
||||
(vvPair
|
||||
variable "year"
|
||||
value "2024"
|
||||
value "2023"
|
||||
)
|
||||
(vvPair
|
||||
variable "yy"
|
||||
value "24"
|
||||
value "23"
|
||||
)
|
||||
]
|
||||
)
|
||||
@ -668,7 +668,8 @@ isHidden 1
|
||||
font "Courier New,9,0"
|
||||
)
|
||||
xt "0,0,15500,1200"
|
||||
st "SIGNAL hReset_n : std_uLogic"
|
||||
st "SIGNAL hReset_n : std_uLogic
|
||||
"
|
||||
)
|
||||
)
|
||||
*13 (Net
|
||||
@ -686,7 +687,8 @@ isHidden 1
|
||||
font "Courier New,9,0"
|
||||
)
|
||||
xt "0,0,15500,1200"
|
||||
st "SIGNAL hClk : std_uLogic"
|
||||
st "SIGNAL hClk : std_uLogic
|
||||
"
|
||||
)
|
||||
)
|
||||
*14 (Net
|
||||
@ -704,7 +706,8 @@ isHidden 1
|
||||
font "Courier New,9,0"
|
||||
)
|
||||
xt "0,0,15500,1200"
|
||||
st "SIGNAL hResp : std_uLogic"
|
||||
st "SIGNAL hResp : std_uLogic
|
||||
"
|
||||
)
|
||||
)
|
||||
*15 (Net
|
||||
@ -722,7 +725,8 @@ isHidden 1
|
||||
font "Courier New,9,0"
|
||||
)
|
||||
xt "0,0,15500,1200"
|
||||
st "SIGNAL hReady : std_uLogic"
|
||||
st "SIGNAL hReady : std_uLogic
|
||||
"
|
||||
)
|
||||
)
|
||||
*16 (Net
|
||||
@ -741,7 +745,8 @@ isHidden 1
|
||||
font "Courier New,9,0"
|
||||
)
|
||||
xt "0,0,32000,1200"
|
||||
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||||
(PageSizeInfo
|
||||
name "Custom Paper Size6(215,9 x 279,4 mm)"
|
||||
type 262
|
||||
width 783
|
||||
height 1013
|
||||
)
|
||||
(PageSizeInfo
|
||||
name "Custom Paper Size7(215,9 x 279,4 mm)"
|
||||
type 263
|
||||
width 783
|
||||
height 1013
|
||||
)
|
||||
(PageSizeInfo
|
||||
name "Custom Paper Size8(215,9 x 279,4 mm)"
|
||||
type 264
|
||||
width 783
|
||||
height 1013
|
||||
)
|
||||
(PageSizeInfo
|
||||
name "Custom Paper Size9(215,9 x 279,4 mm)"
|
||||
type 265
|
||||
width 783
|
||||
height 1013
|
||||
)
|
||||
(PageSizeInfo
|
||||
name "Custom Paper Size10(215,9 x 279,4 mm)"
|
||||
type 266
|
||||
width 783
|
||||
height 1013
|
||||
)
|
||||
]
|
||||
exportPageSetupInfo (PageSetupInfo
|
||||
@ -4149,7 +4292,7 @@ hdsWorkspaceLocation ""
|
||||
relativeLibraryRootDir ""
|
||||
vmLabelLatestDontAskAgain 0
|
||||
vmLabelWorkspaceDontAskAgain 0
|
||||
logWindowGeometry "636x514+308+98"
|
||||
logWindowGeometry "636x406+-823+276"
|
||||
diagramBrowserTabNo 0
|
||||
showInsertPortHint 0
|
||||
showContentFirstTime 0
|
||||
@ -6031,96 +6174,6 @@ disableFilters 1
|
||||
]
|
||||
layoutExpression "V(H(A(C(DesignUnits),C(LogicalObjects)),A(C(Files))),A(C(DesignHierarchy)))"
|
||||
)
|
||||
(Viewpoint_v2
|
||||
name "Parse Errors Report"
|
||||
TreeListVPDatas [
|
||||
(TreeListVPData
|
||||
theList "Hierarchy"
|
||||
columns [
|
||||
(TreeListVPData_Column
|
||||
name "Design Unit Name"
|
||||
displayName ""
|
||||
width 150
|
||||
)
|
||||
(TreeListVPData_Column
|
||||
name "Extends"
|
||||
displayName ""
|
||||
width 100
|
||||
)
|
||||
(TreeListVPData_Column
|
||||
name "Name"
|
||||
displayName ""
|
||||
width 250
|
||||
)
|
||||
(TreeListVPData_Column
|
||||
name "Library"
|
||||
displayName ""
|
||||
width 120
|
||||
)
|
||||
]
|
||||
filterString ""
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||||
accessRights 2
|
||||
)
|
||||
]
|
||||
SmartTableVPDatas [
|
||||
(SmartTableVPData
|
||||
theList "Logical Objects"
|
||||
columns [
|
||||
(SmartTableVPData_Column
|
||||
name "Parse Error"
|
||||
width 22
|
||||
alignment 0
|
||||
)
|
||||
(SmartTableVPData_Column
|
||||
name "File Name"
|
||||
width 150
|
||||
alignment 0
|
||||
)
|
||||
(SmartTableVPData_Column
|
||||
name "Language"
|
||||
width 100
|
||||
alignment 0
|
||||
)
|
||||
(SmartTableVPData_Column
|
||||
name "Library"
|
||||
width 120
|
||||
alignment 0
|
||||
)
|
||||
(SmartTableVPData_Column
|
||||
name "Location"
|
||||
width 200
|
||||
alignment 0
|
||||
)
|
||||
(SmartTableVPData_Column
|
||||
name "Absolute Path"
|
||||
width 14
|
||||
alignment 1
|
||||
)
|
||||
]
|
||||
filterNames [
|
||||
"Architectures and Modules"
|
||||
"Configurations"
|
||||
"Entities"
|
||||
"Files"
|
||||
"Instances"
|
||||
"Packages"
|
||||
"SV Classes"
|
||||
"SV Interfaces"
|
||||
"SV Packages"
|
||||
"SV Program Blocks"
|
||||
]
|
||||
filterString "1"
|
||||
filterColumn "Parse Error"
|
||||
matchCase 0
|
||||
matchWholeWordOnly 0
|
||||
regularExpression 1
|
||||
groupNames [
|
||||
]
|
||||
disableFilters 1
|
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)
|
||||
]
|
||||
layoutExpression "V(A(C(LogicalObjects)))"
|
||||
)
|
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]
|
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WorkTabs [
|
||||
(WorkTab
|
||||
@ -6316,7 +6369,6 @@ activeViewpointIdx 0
|
||||
)
|
||||
]
|
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ViewpointsOnOutlookBar [
|
||||
"Parse Errors Report"
|
||||
]
|
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lastActiveViewpoint "Default Viewpoint"
|
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expandedTemplateNodes [
|
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@ -6332,11 +6384,11 @@ size 180
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]
|
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displayHierarchy 0
|
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xPos 0
|
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yPos 9
|
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width 974
|
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height 1047
|
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yPos 0
|
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width 1936
|
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height 1056
|
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activeSidePanelTab 2
|
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activeLibraryTab 5
|
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activeLibraryTab 1
|
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sidePanelSize 278
|
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showUnixHiddenFiles 0
|
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componentBrowserXpos 569
|
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|
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File diff suppressed because it is too large
Load Diff
@ -46,7 +46,7 @@ settingsMap [
|
||||
"GlitchGeneration"
|
||||
"1"
|
||||
"InitCmd"
|
||||
"C:/Users/remi.heredero/GIT/2024-sem-labs-herederoremi/06-07-08-09-SystemOnChip/Simulation/ahbUart.do"
|
||||
"$SIMULATION_DIR/beamerSoc.do"
|
||||
"LogFile"
|
||||
""
|
||||
"RemoteHost"
|
||||
|
||||
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Loading…
Reference in New Issue
Block a user