some file i don't know if needed

06-07-08-09-SystemOnChip/AhbLiteComponents/hdl/ahbGpio_studentVersion.vhd

@@ -18,16 +18,123 @@
 -- 00, data register provides the values detected on the lines.
 --
 ARCHITECTURE studentVersion OF ahbGpio IS
+
+signal addresses: unsigned(hAddr'range);
+signal bRead: std_ulogic;
+signal bWrite: std_ulogic;
+signal bDone: std_ulogic;
+
+
 BEGIN
 
+  process(hReset_n, hClk) begin
+    if hReset_n = '0' then
       -- AHB-Lite
+      --hRData  <=  (OTHERS => 'Z');
       hRData  <=  (OTHERS => '0');
-  hReady  <=	'0';	
+      hReady  <=  '1';  
       hResp   <=  '0';  
 
       -- Out
       ioOut <= (OTHERS => '0');
       ioEn  <= (OTHERS => '0');
 
+      addresses  <=  (OTHERS => '0');
+      bRead <= '0';
+      bWrite <= '0';
+      bDone <= '0';
+    elsif rising_edge(hClk) then
+      if hSel = '1' then
+        bWrite <= hWrite;
+        bRead <= not hWrite;
+        addresses <= hAddr;
+        hReady <= '0';
+        bDone <= '0';
+      else
+        bWrite <= '0';
+        bRead <= '0';
+      end if;
+
+      if bRead = '1' and bWrite = '0' then
+        -------------------------------------------------------------------------
+        -- READ
+        -------------------------------------------------------------------------
+        
+        if addresses = "00" then
+          -- ##### Read data register #####
+          --hRData <= unsigned(resize(ioIn, ioNb));
+          for i in 0 to ioNb-1 loop
+            hRData(i) <= ioIn(i);
+          end loop;
+          bDone <= '1';
+
+        elsif addresses = "01" then
+          report "@@@@@@@@@@ Not possible to change output in READ mode @@@@@@@@@@" severity error;
+
+        end if;
+
+      elsif bRead = '0' and bWrite = '1' then
+        -------------------------------------------------------------------------
+        -- WRITE
+        -------------------------------------------------------------------------
+        
+        if addresses = "00" then
+          -- ##### Write data register #####
+          --ioOut <= resize(std_ulogic_vector(hWData), ioNb);
+          for i in 0 to ioNb-1 loop
+            ioOut(i) <= hWData(i);
+          end loop;
+          bDone <= '1';
+
+        elsif addresses = "01" then
+          -- ##### Write direction register #####
+          --ioEn <= hWData;
+          for i in 0 to ioNb-1 loop
+            ioEn(i) <= hWData(i);
+          end loop;
+          bDone <= '1';
+          
+        end if;
+
+      elsif bRead = '1' and bWrite = '1' then
+        -------------------------------------------------------------------------
+        -- SHOULD NEVER HAPPEN
+        -------------------------------------------------------------------------
+        report "@@@@@@@@@@ READ and WRITE can't happened in same time @@@@@@@@@@" severity error;
+
+      end if;
+
+      if (ioIn and ioEn) = (ioEn and ioOut) then
+        hResp <= '0';
+      else
+        hResp <= '1';
+      end if;
+
+      if bDone = '1' then
+        --hRData  <=  (OTHERS => 'Z');
+        bDone <= '0';
+        hReady <= '1';
+      end if;
+
+    end if;
+
+    for i in (ioNb-1) downto 0 loop
+      if (ioEn(i) and ioIn(i)) /= (ioEn(i) and ioOut(i)) then
+        --ioEn(i) <= '0';
+        report "an output was in conflict" severity note;
+      end if;
+    end loop;
+
+  end process;
+
+  -- AHB-Lite
+--  hRData  <=	(OTHERS => '0');
+--  hReady  <=	'0';	
+--  hResp	  <=	'0';	
+
+  -- Out
+--  ioOut <= (OTHERS => '0');
+--  ioEn  <= (OTHERS => '0');
+
 END ARCHITECTURE studentVersion;
 

06-07-08-09-SystemOnChip/AhbLiteComponents/hdl/ahbgpio_entity.vhg

@@ -0,0 +1,38 @@
+-- VHDL Entity AhbLiteComponents.ahbGpio.symbol
+--
+-- Created:
+--          by - remi.heredero.UNKNOWN (WE2330808)
+--          at - 15:08:33 23.02.2024
+--
+-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5)
+--
+LIBRARY ieee;
+  USE ieee.std_logic_1164.all;
+  USE ieee.numeric_std.all;
+LIBRARY AhbLite;
+  USE AhbLite.ahbLite.all;
+
+ENTITY ahbGpio IS
+    GENERIC( 
+        ioNb : positive := 8
+    );
+    PORT( 
+        hAddr    : IN     unsigned ( ahbAddressBitNb-1 DOWNTO 0 );
+        hClk     : IN     std_uLogic;
+        hReset_n : IN     std_uLogic;
+        hSel     : IN     std_uLogic;
+        hTrans   : IN     std_ulogic_vector (ahbTransBitNb-1 DOWNTO 0);
+        hWData   : IN     std_ulogic_vector (ahbDataBitNb-1 DOWNTO 0);
+        hWrite   : IN     std_uLogic;
+        ioIn     : IN     std_ulogic_vector (ioNb-1 DOWNTO 0);
+        hRData   : OUT    std_ulogic_vector (ahbDataBitNb-1 DOWNTO 0);
+        hReady   : OUT    std_uLogic;
+        hResp    : OUT    std_uLogic;
+        ioEn     : OUT    std_ulogic_vector (ioNb-1 DOWNTO 0);
+        ioOut    : OUT    std_ulogic_vector (ioNb-1 DOWNTO 0)
+    );
+
+-- Declarations
+
+END ahbGpio ;
+

06-07-08-09-SystemOnChip/AhbLiteComponents/hdl/ahbuart_entity.vhg

@@ -0,0 +1,38 @@
+-- VHDL Entity AhbLiteComponents.ahbUart.symbol
+--
+-- Created:
+--          by - remi.heredero.UNKNOWN (WE2330808)
+--          at - 15:08:33 23.02.2024
+--
+-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5)
+--
+LIBRARY ieee;
+  USE ieee.std_logic_1164.all;
+  USE ieee.numeric_std.all;
+LIBRARY AhbLite;
+  USE AhbLite.ahbLite.all;
+
+ENTITY ahbUart IS
+    GENERIC( 
+        txFifoDepth : positive := 8;
+        rxFifoDepth : positive := 1
+    );
+    PORT( 
+        RxD      : IN     std_ulogic;
+        hAddr    : IN     unsigned ( ahbAddressBitNb-1 DOWNTO 0 );
+        hClk     : IN     std_uLogic;
+        hReset_n : IN     std_uLogic;
+        hSel     : IN     std_uLogic;
+        hTrans   : IN     std_ulogic_vector (ahbTransBitNb-1 DOWNTO 0);
+        hWData   : IN     std_ulogic_vector (ahbDataBitNb-1 DOWNTO 0);
+        hWrite   : IN     std_uLogic;
+        TxD      : OUT    std_ulogic;
+        hRData   : OUT    std_ulogic_vector (ahbDataBitNb-1 DOWNTO 0);
+        hReady   : OUT    std_uLogic;
+        hResp    : OUT    std_uLogic
+    );
+
+-- Declarations
+
+END ahbUart ;
+

06-07-08-09-SystemOnChip/AhbLiteComponents/hds/.xrf/ahbgpio_entity.xrf

@@ -0,0 +1,54 @@
+DESIGN ahb@gpio
+VIEW symbol.sb
+NO_GRAPHIC 0
+DESIGN ahb@gpio
+VIEW symbol.sb
+GRAPHIC 104,0 8 0 
+DESIGN ahb@gpio
+VIEW symbol.sb
+GRAPHIC 13,0 15 1 
+DESIGN ahb@gpio
+VIEW symbol.sb
+GRAPHIC 2452,0 19 0 
+DESIGN ahb@gpio
+VIEW symbol.sb
+GRAPHIC 2514,0 20 0 
+DESIGN ahb@gpio
+VIEW symbol.sb
+GRAPHIC 2519,0 21 0 
+DESIGN ahb@gpio
+VIEW symbol.sb
+GRAPHIC 2692,0 22 0 
+DESIGN ahb@gpio
+VIEW symbol.sb
+GRAPHIC 2494,0 23 0 
+DESIGN ahb@gpio
+VIEW symbol.sb
+GRAPHIC 2464,0 24 0 
+DESIGN ahb@gpio
+VIEW symbol.sb
+GRAPHIC 2474,0 25 0 
+DESIGN ahb@gpio
+VIEW symbol.sb
+GRAPHIC 2839,0 26 0 
+DESIGN ahb@gpio
+VIEW symbol.sb
+GRAPHIC 2469,0 27 0 
+DESIGN ahb@gpio
+VIEW symbol.sb
+GRAPHIC 2504,0 28 0 
+DESIGN ahb@gpio
+VIEW symbol.sb
+GRAPHIC 2509,0 29 0 
+DESIGN ahb@gpio
+VIEW symbol.sb
+GRAPHIC 2846,0 30 0 
+DESIGN ahb@gpio
+VIEW symbol.sb
+GRAPHIC 2651,0 31 0 
+DESIGN ahb@gpio
+VIEW symbol.sb
+GRAPHIC 1,0 34 0 
+DESIGN ahb@gpio
+VIEW symbol.sb
+GRAPHIC 1,0 35 0 

06-07-08-09-SystemOnChip/AhbLiteComponents/hds/.xrf/ahbuart_entity.xrf

@@ -0,0 +1,51 @@
+DESIGN ahb@uart
+VIEW symbol.sb
+NO_GRAPHIC 0
+DESIGN ahb@uart
+VIEW symbol.sb
+GRAPHIC 104,0 8 0 
+DESIGN ahb@uart
+VIEW symbol.sb
+GRAPHIC 13,0 15 1 
+DESIGN ahb@uart
+VIEW symbol.sb
+GRAPHIC 2839,0 20 0 
+DESIGN ahb@uart
+VIEW symbol.sb
+GRAPHIC 2452,0 21 0 
+DESIGN ahb@uart
+VIEW symbol.sb
+GRAPHIC 2514,0 22 0 
+DESIGN ahb@uart
+VIEW symbol.sb
+GRAPHIC 2519,0 23 0 
+DESIGN ahb@uart
+VIEW symbol.sb
+GRAPHIC 2692,0 24 0 
+DESIGN ahb@uart
+VIEW symbol.sb
+GRAPHIC 2494,0 25 0 
+DESIGN ahb@uart
+VIEW symbol.sb
+GRAPHIC 2464,0 26 0 
+DESIGN ahb@uart
+VIEW symbol.sb
+GRAPHIC 2474,0 27 0 
+DESIGN ahb@uart
+VIEW symbol.sb
+GRAPHIC 2651,0 28 0 
+DESIGN ahb@uart
+VIEW symbol.sb
+GRAPHIC 2469,0 29 0 
+DESIGN ahb@uart
+VIEW symbol.sb
+GRAPHIC 2504,0 30 0 
+DESIGN ahb@uart
+VIEW symbol.sb
+GRAPHIC 2509,0 31 0 
+DESIGN ahb@uart
+VIEW symbol.sb
+GRAPHIC 1,0 34 0 
+DESIGN ahb@uart
+VIEW symbol.sb
+GRAPHIC 1,0 35 0 

06-07-08-09-SystemOnChip/AhbLiteComponents_test/hdl/ahbgpio_tb_entity.vhg

@@ -0,0 +1,15 @@
+-- VHDL Entity AhbLiteComponents_test.ahbGpio_tb.symbol
+--
+-- Created:
+--          by - axel.amand.UNKNOWN (WE7860)
+--          at - 14:51:39 28.04.2023
+--
+-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5)
+--
+
+
+ENTITY ahbGpio_tb IS
+-- Declarations
+
+END ahbGpio_tb ;
+

06-07-08-09-SystemOnChip/AhbLiteComponents_test/hdl/ahbgpio_tb_struct.vhg

@@ -0,0 +1,148 @@
+--
+-- VHDL Architecture AhbLiteComponents_test.ahbGpio_tb.struct
+--
+-- Created:
+--          by - remi.heredero.UNKNOWN (WE2330808)
+--          at - 14:16:25 19.04.2024
+--
+-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5)
+--
+LIBRARY ieee;
+  USE ieee.std_logic_1164.all;
+  USE ieee.numeric_std.all;
+LIBRARY AhbLite;
+  USE AhbLite.ahbLite.all;
+
+LIBRARY AhbLiteComponents;
+LIBRARY AhbLiteComponents_test;
+
+ARCHITECTURE struct OF ahbGpio_tb IS
+
+    -- Architecture declarations
+    constant ioNb: positive := 8;
+    
+    constant clockFrequency : real := 60.0E6;
+    --constant clockFrequency : real := 66.0E6;
+
+    -- Internal signal declarations
+    SIGNAL hAddr    : unsigned( ahbAddressBitNb-1 DOWNTO 0 );
+    SIGNAL hClk     : std_uLogic;
+    SIGNAL hRData   : std_ulogic_vector(ahbDataBitNb-1 DOWNTO 0);
+    SIGNAL hReady   : std_uLogic;
+    SIGNAL hReset_n : std_uLogic;
+    SIGNAL hResp    : std_uLogic;
+    SIGNAL hSel     : std_uLogic;
+    SIGNAL hTrans   : std_ulogic_vector(ahbTransBitNb-1 DOWNTO 0);
+    SIGNAL hWData   : std_ulogic_vector(ahbDataBitNb-1 DOWNTO 0);
+    SIGNAL hWrite   : std_uLogic;
+    SIGNAL io       : std_logic_vector(ioNb-1 DOWNTO 0);
+    SIGNAL ioEn     : std_ulogic_vector(ioNb-1 DOWNTO 0);
+    SIGNAL ioIn     : std_ulogic_vector(ioNb-1 DOWNTO 0);
+    SIGNAL ioOut    : std_ulogic_vector(ioNb-1 DOWNTO 0);
+
+
+    -- Component Declarations
+    COMPONENT ahbGpio
+    GENERIC (
+        ioNb : positive := 8
+    );
+    PORT (
+        hAddr    : IN     unsigned ( ahbAddressBitNb-1 DOWNTO 0 );
+        hClk     : IN     std_uLogic ;
+        hReset_n : IN     std_uLogic ;
+        hSel     : IN     std_uLogic ;
+        hTrans   : IN     std_ulogic_vector (ahbTransBitNb-1 DOWNTO 0);
+        hWData   : IN     std_ulogic_vector (ahbDataBitNb-1 DOWNTO 0);
+        hWrite   : IN     std_uLogic ;
+        ioIn     : IN     std_ulogic_vector (ioNb-1 DOWNTO 0);
+        hRData   : OUT    std_ulogic_vector (ahbDataBitNb-1 DOWNTO 0);
+        hReady   : OUT    std_uLogic ;
+        hResp    : OUT    std_uLogic ;
+        ioEn     : OUT    std_ulogic_vector (ioNb-1 DOWNTO 0);
+        ioOut    : OUT    std_ulogic_vector (ioNb-1 DOWNTO 0)
+    );
+    END COMPONENT;
+    COMPONENT ahbGpio_tester
+    GENERIC (
+        ioNb           : positive;
+        clockFrequency : real
+    );
+    PORT (
+        hRData   : IN     std_ulogic_vector (ahbDataBitNb-1 DOWNTO 0);
+        hReady   : IN     std_uLogic ;
+        hResp    : IN     std_uLogic ;
+        hAddr    : OUT    unsigned ( ahbAddressBitNb-1 DOWNTO 0 );
+        hClk     : OUT    std_uLogic ;
+        hReset_n : OUT    std_uLogic ;
+        hSel     : OUT    std_uLogic ;
+        hTrans   : OUT    std_ulogic_vector (ahbTransBitNb-1 DOWNTO 0);
+        hWData   : OUT    std_ulogic_vector (ahbDataBitNb-1 DOWNTO 0);
+        hWrite   : OUT    std_uLogic ;
+        io       : INOUT  std_logic_vector (ioNb-1 DOWNTO 0)
+    );
+    END COMPONENT;
+
+    -- Optional embedded configurations
+    -- pragma synthesis_off
+    FOR ALL : ahbGpio USE ENTITY AhbLiteComponents.ahbGpio;
+    FOR ALL : ahbGpio_tester USE ENTITY AhbLiteComponents_test.ahbGpio_tester;
+    -- pragma synthesis_on
+
+
+BEGIN
+    -- Architecture concurrent statements
+    -- HDL Embedded Text Block 1 eb1
+    tristate: process(ioEn, ioOut)
+    begin
+      for index in io'range loop
+        if ioEn(index) = '1' then
+          io(index) <= ioOut(index);
+        else
+          io(index) <= 'Z';
+        end if;
+      end loop;
+    end process tristate;
+    
+    ioIn <= std_ulogic_vector(io);
+
+
+    -- Instance port mappings.
+    I_DUT : ahbGpio
+        GENERIC MAP (
+            ioNb => ioNb
+        )
+        PORT MAP (
+            hAddr    => hAddr,
+            hClk     => hClk,
+            hReset_n => hReset_n,
+            hSel     => hSel,
+            hTrans   => hTrans,
+            hWData   => hWData,
+            hWrite   => hWrite,
+            ioIn     => ioIn,
+            hRData   => hRData,
+            hReady   => hReady,
+            hResp    => hResp,
+            ioEn     => ioEn,
+            ioOut    => ioOut
+        );
+    I_tester : ahbGpio_tester
+        GENERIC MAP (
+            ioNb           => ioNb,
+            clockFrequency => clockFrequency
+        )
+        PORT MAP (
+            hRData   => hRData,
+            hReady   => hReady,
+            hResp    => hResp,
+            hAddr    => hAddr,
+            hClk     => hClk,
+            hReset_n => hReset_n,
+            hSel     => hSel,
+            hTrans   => hTrans,
+            hWData   => hWData,
+            hWrite   => hWrite,
+            io       => io
+        );
+
+END struct;

06-07-08-09-SystemOnChip/AhbLiteComponents_test/hdl/ahbgpio_tester_entity.vhg

@@ -0,0 +1,37 @@
+-- VHDL Entity AhbLiteComponents_test.ahbGpio_tester.interface
+--
+-- Created:
+--          by - axel.amand.UNKNOWN (WE7860)
+--          at - 14:51:40 28.04.2023
+--
+-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5)
+--
+LIBRARY ieee;
+  USE ieee.std_logic_1164.all;
+  USE ieee.numeric_std.all;
+LIBRARY AhbLite;
+  USE AhbLite.ahbLite.all;
+
+ENTITY ahbGpio_tester IS
+    GENERIC( 
+        ioNb           : positive;
+        clockFrequency : real
+    );
+    PORT( 
+        hRData   : IN     std_ulogic_vector (ahbDataBitNb-1 DOWNTO 0);
+        hReady   : IN     std_uLogic;
+        hResp    : IN     std_uLogic;
+        hAddr    : OUT    unsigned ( ahbAddressBitNb-1 DOWNTO 0 );
+        hClk     : OUT    std_uLogic;
+        hReset_n : OUT    std_uLogic;
+        hSel     : OUT    std_uLogic;
+        hTrans   : OUT    std_ulogic_vector (ahbTransBitNb-1 DOWNTO 0);
+        hWData   : OUT    std_ulogic_vector (ahbDataBitNb-1 DOWNTO 0);
+        hWrite   : OUT    std_uLogic;
+        io       : INOUT  std_logic_vector (ioNb-1 DOWNTO 0)
+    );
+
+-- Declarations
+
+END ahbGpio_tester ;
+

06-07-08-09-SystemOnChip/AhbLiteComponents_test/hdl/ahbuart_tb_entity.vhg

@@ -0,0 +1,15 @@
+-- VHDL Entity AhbLiteComponents_test.ahbUart_tb.symbol
+--
+-- Created:
+--          by - zas.UNKNOWN (ZELL)
+--          at - 17:08:42 02/17/2020
+--
+-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5)
+--
+
+
+ENTITY ahbUart_tb IS
+-- Declarations
+
+END ahbUart_tb ;
+

06-07-08-09-SystemOnChip/AhbLiteComponents_test/hdl/ahbuart_tb_struct.vhg

@@ -0,0 +1,132 @@
+--
+-- VHDL Architecture AhbLiteComponents_test.ahbUart_tb.struct
+--
+-- Created:
+--          by - axel.amand.UNKNOWN (WE7860)
+--          at - 15:07:00 28.04.2023
+--
+-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5)
+--
+LIBRARY ieee;
+  USE ieee.std_logic_1164.all;
+  USE ieee.numeric_std.all;
+LIBRARY AhbLite;
+  USE AhbLite.ahbLite.all;
+
+LIBRARY AhbLiteComponents;
+LIBRARY AhbLiteComponents_test;
+
+ARCHITECTURE struct OF ahbUart_tb IS
+
+    -- Architecture declarations
+    constant txFifoDepth: positive := 1;
+    constant rxFifoDepth: positive := 1;
+    
+    constant clockFrequency : real := 60.0E6;
+    --constant clockFrequency : real := 66.0E6;
+
+    -- Internal signal declarations
+    SIGNAL RxD      : std_ulogic;
+    SIGNAL TxD      : std_ulogic;
+    SIGNAL hAddr    : unsigned( ahbAddressBitNb-1 DOWNTO 0 );
+    SIGNAL hClk     : std_uLogic;
+    SIGNAL hRData   : std_ulogic_vector(ahbDataBitNb-1 DOWNTO 0);
+    SIGNAL hReady   : std_uLogic;
+    SIGNAL hReset_n : std_uLogic;
+    SIGNAL hResp    : std_uLogic;
+    SIGNAL hSel     : std_uLogic;
+    SIGNAL hTrans   : std_ulogic_vector(ahbTransBitNb-1 DOWNTO 0);
+    SIGNAL hWData   : std_ulogic_vector(ahbDataBitNb-1 DOWNTO 0);
+    SIGNAL hWrite   : std_uLogic;
+
+
+    -- Component Declarations
+    COMPONENT ahbUart
+    GENERIC (
+        txFifoDepth : positive := 8;
+        rxFifoDepth : positive := 1
+    );
+    PORT (
+        RxD      : IN     std_ulogic ;
+        hAddr    : IN     unsigned ( ahbAddressBitNb-1 DOWNTO 0 );
+        hClk     : IN     std_uLogic ;
+        hReset_n : IN     std_uLogic ;
+        hSel     : IN     std_uLogic ;
+        hTrans   : IN     std_ulogic_vector (ahbTransBitNb-1 DOWNTO 0);
+        hWData   : IN     std_ulogic_vector (ahbDataBitNb-1 DOWNTO 0);
+        hWrite   : IN     std_uLogic ;
+        TxD      : OUT    std_ulogic ;
+        hRData   : OUT    std_ulogic_vector (ahbDataBitNb-1 DOWNTO 0);
+        hReady   : OUT    std_uLogic ;
+        hResp    : OUT    std_uLogic 
+    );
+    END COMPONENT;
+    COMPONENT ahbUart_tester
+    GENERIC (
+        clockFrequency : real
+    );
+    PORT (
+        TxD      : IN     std_ulogic ;
+        hRData   : IN     std_ulogic_vector (ahbDataBitNb-1 DOWNTO 0);
+        hReady   : IN     std_uLogic ;
+        hResp    : IN     std_uLogic ;
+        RxD      : OUT    std_ulogic ;
+        hAddr    : OUT    unsigned ( ahbAddressBitNb-1 DOWNTO 0 );
+        hClk     : OUT    std_uLogic ;
+        hReset_n : OUT    std_uLogic ;
+        hSel     : OUT    std_uLogic ;
+        hTrans   : OUT    std_ulogic_vector (ahbTransBitNb-1 DOWNTO 0);
+        hWData   : OUT    std_ulogic_vector (ahbDataBitNb-1 DOWNTO 0);
+        hWrite   : OUT    std_uLogic 
+    );
+    END COMPONENT;
+
+    -- Optional embedded configurations
+    -- pragma synthesis_off
+    FOR ALL : ahbUart USE ENTITY AhbLiteComponents.ahbUart;
+    FOR ALL : ahbUart_tester USE ENTITY AhbLiteComponents_test.ahbUart_tester;
+    -- pragma synthesis_on
+
+
+BEGIN
+
+    -- Instance port mappings.
+    I_DUT : ahbUart
+        GENERIC MAP (
+            txFifoDepth => txFifoDepth,
+            rxFifoDepth => rxFifoDepth
+        )
+        PORT MAP (
+            RxD      => RxD,
+            hAddr    => hAddr,
+            hClk     => hClk,
+            hReset_n => hReset_n,
+            hSel     => hSel,
+            hTrans   => hTrans,
+            hWData   => hWData,
+            hWrite   => hWrite,
+            TxD      => TxD,
+            hRData   => hRData,
+            hReady   => hReady,
+            hResp    => hResp
+        );
+    I_tester : ahbUart_tester
+        GENERIC MAP (
+            clockFrequency => clockFrequency
+        )
+        PORT MAP (
+            TxD      => TxD,
+            hRData   => hRData,
+            hReady   => hReady,
+            hResp    => hResp,
+            RxD      => RxD,
+            hAddr    => hAddr,
+            hClk     => hClk,
+            hReset_n => hReset_n,
+            hSel     => hSel,
+            hTrans   => hTrans,
+            hWData   => hWData,
+            hWrite   => hWrite
+        );
+
+END struct;

06-07-08-09-SystemOnChip/AhbLiteComponents_test/hdl/ahbuart_tester_entity.vhg

@@ -0,0 +1,37 @@
+-- VHDL Entity AhbLiteComponents_test.ahbUart_tester.interface
+--
+-- Created:
+--          by - zas.UNKNOWN (ZELL)
+--          at - 17:08:42 02/17/2020
+--
+-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5)
+--
+LIBRARY ieee;
+  USE ieee.std_logic_1164.all;
+  USE ieee.numeric_std.all;
+LIBRARY AhbLite;
+  USE AhbLite.ahbLite.all;
+
+ENTITY ahbUart_tester IS
+    GENERIC( 
+        clockFrequency : real
+    );
+    PORT( 
+        TxD      : IN     std_ulogic;
+        hRData   : IN     std_ulogic_vector (ahbDataBitNb-1 DOWNTO 0);
+        hReady   : IN     std_uLogic;
+        hResp    : IN     std_uLogic;
+        RxD      : OUT    std_ulogic;
+        hAddr    : OUT    unsigned ( ahbAddressBitNb-1 DOWNTO 0 );
+        hClk     : OUT    std_uLogic;
+        hReset_n : OUT    std_uLogic;
+        hSel     : OUT    std_uLogic;
+        hTrans   : OUT    std_ulogic_vector (ahbTransBitNb-1 DOWNTO 0);
+        hWData   : OUT    std_ulogic_vector (ahbDataBitNb-1 DOWNTO 0);
+        hWrite   : OUT    std_uLogic
+    );
+
+-- Declarations
+
+END ahbUart_tester ;
+

06-07-08-09-SystemOnChip/AhbLiteComponents_test/hds/.hdlsidedata/_ahbgpio_tb_entity.vhg._fpf

@@ -1 +1 @@
-DIALECT atom VHDL_ANY
+DIALECT atom VHDL_2008

06-07-08-09-SystemOnChip/AhbLiteComponents_test/hds/.hdlsidedata/_ahbgpio_tb_struct.vhg._fpf

@@ -1 +1 @@
-DIALECT atom VHDL_ANY
+DIALECT atom VHDL_2008

06-07-08-09-SystemOnChip/AhbLiteComponents_test/hds/.xrf/ahbgpio_tb_entity.xrf

@@ -0,0 +1,12 @@
+DESIGN ahb@gpio_tb
+VIEW symbol.sb
+NO_GRAPHIC 0
+DESIGN ahb@gpio_tb
+VIEW symbol.sb
+GRAPHIC 53,0 8 0 
+DESIGN ahb@gpio_tb
+VIEW symbol.sb
+GRAPHIC 1,0 11 0 
+DESIGN ahb@gpio_tb
+VIEW symbol.sb
+GRAPHIC 1,0 12 0 

06-07-08-09-SystemOnChip/AhbLiteComponents_test/hds/.xrf/ahbgpio_tb_struct.xrf

@@ -0,0 +1,228 @@
+DESIGN ahb@gpio_tb
+VIEW struct.bd
+NO_GRAPHIC 0
+DESIGN ahb@gpio_tb
+VIEW struct.bd
+GRAPHIC 187,0 9 0 
+DESIGN ahb@gpio_tb
+VIEW struct.bd
+NO_GRAPHIC 14
+DESIGN ahb@gpio_tb
+VIEW struct.bd
+GRAPHIC 0,0 18 2 
+DESIGN ahb@gpio_tb
+VIEW struct.bd
+GRAPHIC 1,0 21 0 
+DESIGN ahb@gpio_tb
+VIEW struct.bd
+NO_GRAPHIC 21
+DESIGN ahb@gpio_tb
+VIEW struct.bd
+GRAPHIC 12627,0 27 0 
+DESIGN ahb@gpio_tb
+VIEW struct.bd
+GRAPHIC 12563,0 28 0 
+DESIGN ahb@gpio_tb
+VIEW struct.bd
+GRAPHIC 12587,0 29 0 
+DESIGN ahb@gpio_tb
+VIEW struct.bd
+GRAPHIC 12579,0 30 0 
+DESIGN ahb@gpio_tb
+VIEW struct.bd
+GRAPHIC 12555,0 31 0 
+DESIGN ahb@gpio_tb
+VIEW struct.bd
+GRAPHIC 12571,0 32 0 
+DESIGN ahb@gpio_tb
+VIEW struct.bd
+GRAPHIC 12595,0 33 0 
+DESIGN ahb@gpio_tb
+VIEW struct.bd
+GRAPHIC 12611,0 34 0 
+DESIGN ahb@gpio_tb
+VIEW struct.bd
+GRAPHIC 12619,0 35 0 
+DESIGN ahb@gpio_tb
+VIEW struct.bd
+GRAPHIC 12603,0 36 0 
+DESIGN ahb@gpio_tb
+VIEW struct.bd
+GRAPHIC 13244,0 37 0 
+DESIGN ahb@gpio_tb
+VIEW struct.bd
+GRAPHIC 13210,0 38 0 
+DESIGN ahb@gpio_tb
+VIEW struct.bd
+GRAPHIC 13226,0 39 0 
+DESIGN ahb@gpio_tb
+VIEW struct.bd
+GRAPHIC 13218,0 40 0 
+DESIGN ahb@gpio_tb
+VIEW struct.bd
+NO_GRAPHIC 41
+DESIGN ahb@gpio_tb
+VIEW struct.bd
+NO_GRAPHIC 42
+LIBRARY AhbLiteComponents
+DESIGN ahb@gpio
+VIEW student@version
+GRAPHIC 13194,0 44 0 
+DESIGN ahb@gpio
+VIEW symbol.sb
+GRAPHIC 14,0 45 1 
+DESIGN ahb@gpio
+VIEW symbol.sb
+GRAPHIC 2452,0 49 0 
+DESIGN ahb@gpio
+VIEW symbol.sb
+GRAPHIC 2514,0 50 0 
+DESIGN ahb@gpio
+VIEW symbol.sb
+GRAPHIC 2519,0 51 0 
+DESIGN ahb@gpio
+VIEW symbol.sb
+GRAPHIC 2692,0 52 0 
+DESIGN ahb@gpio
+VIEW symbol.sb
+GRAPHIC 2494,0 53 0 
+DESIGN ahb@gpio
+VIEW symbol.sb
+GRAPHIC 2464,0 54 0 
+DESIGN ahb@gpio
+VIEW symbol.sb
+GRAPHIC 2474,0 55 0 
+DESIGN ahb@gpio
+VIEW symbol.sb
+GRAPHIC 2839,0 56 0 
+DESIGN ahb@gpio
+VIEW symbol.sb
+GRAPHIC 2469,0 57 0 
+DESIGN ahb@gpio
+VIEW symbol.sb
+GRAPHIC 2504,0 58 0 
+DESIGN ahb@gpio
+VIEW symbol.sb
+GRAPHIC 2509,0 59 0 
+DESIGN ahb@gpio
+VIEW symbol.sb
+GRAPHIC 2846,0 60 0 
+DESIGN ahb@gpio
+VIEW symbol.sb
+GRAPHIC 2651,0 61 0 
+LIBRARY AhbLiteComponents_test
+DESIGN ahb@gpio_tester
+VIEW test
+GRAPHIC 12657,0 64 0 
+DESIGN ahb@gpio_tester
+VIEW interface
+GRAPHIC 14,0 65 1 
+DESIGN ahb@gpio_tb
+VIEW struct.bd
+GRAPHIC 12589,0 70 0 
+DESIGN ahb@gpio_tb
+VIEW struct.bd
+GRAPHIC 12581,0 71 0 
+DESIGN ahb@gpio_tb
+VIEW struct.bd
+GRAPHIC 12573,0 72 0 
+DESIGN ahb@gpio_tb
+VIEW struct.bd
+GRAPHIC 12629,0 73 0 
+DESIGN ahb@gpio_tb
+VIEW struct.bd
+GRAPHIC 12565,0 74 0 
+DESIGN ahb@gpio_tb
+VIEW struct.bd
+GRAPHIC 12557,0 75 0 
+DESIGN ahb@gpio_tb
+VIEW struct.bd
+GRAPHIC 12597,0 76 0 
+DESIGN ahb@gpio_tb
+VIEW struct.bd
+GRAPHIC 12613,0 77 0 
+DESIGN ahb@gpio_tb
+VIEW struct.bd
+GRAPHIC 12621,0 78 0 
+DESIGN ahb@gpio_tb
+VIEW struct.bd
+GRAPHIC 12605,0 79 0 
+DESIGN ahb@gpio_tb
+VIEW struct.bd
+GRAPHIC 13236,0 80 0 
+LIBRARY AhbLiteComponents_test
+DESIGN ahb@gpio_tb
+VIEW struct.bd
+NO_GRAPHIC 83
+DESIGN ahb@gpio_tb
+VIEW struct.bd
+GRAPHIC 13194,0 86 0 
+DESIGN ahb@gpio_tb
+VIEW struct.bd
+GRAPHIC 12657,0 87 0 
+DESIGN ahb@gpio_tb
+VIEW struct.bd
+NO_GRAPHIC 90
+DESIGN ahb@gpio_tb
+VIEW struct.bd
+GRAPHIC 13204,0 93 0 
+DESIGN ahb@gpio_tb
+VIEW struct.bd
+NO_GRAPHIC 106
+DESIGN ahb@gpio_tb
+VIEW struct.bd
+NO_GRAPHIC 107
+DESIGN ahb@gpio_tb
+VIEW struct.bd
+GRAPHIC 13194,0 109 0 
+DESIGN ahb@gpio_tb
+VIEW struct.bd
+GRAPHIC 13201,0 110 1 
+DESIGN ahb@gpio_tb
+VIEW struct.bd
+GRAPHIC 12629,0 114 0 
+DESIGN ahb@gpio_tb
+VIEW struct.bd
+GRAPHIC 12565,0 115 0 
+DESIGN ahb@gpio_tb
+VIEW struct.bd
+GRAPHIC 12557,0 116 0 
+DESIGN ahb@gpio_tb
+VIEW struct.bd
+GRAPHIC 12597,0 117 0 
+DESIGN ahb@gpio_tb
+VIEW struct.bd
+GRAPHIC 12613,0 118 0 
+DESIGN ahb@gpio_tb
+VIEW struct.bd
+GRAPHIC 12621,0 119 0 
+DESIGN ahb@gpio_tb
+VIEW struct.bd
+GRAPHIC 12605,0 120 0 
+DESIGN ahb@gpio_tb
+VIEW struct.bd
+GRAPHIC 13228,0 121 0 
+DESIGN ahb@gpio_tb
+VIEW struct.bd
+GRAPHIC 12589,0 122 0 
+DESIGN ahb@gpio_tb
+VIEW struct.bd
+GRAPHIC 12581,0 123 0 
+DESIGN ahb@gpio_tb
+VIEW struct.bd
+GRAPHIC 12573,0 124 0 
+DESIGN ahb@gpio_tb
+VIEW struct.bd
+GRAPHIC 13212,0 125 0 
+DESIGN ahb@gpio_tb
+VIEW struct.bd
+GRAPHIC 13220,0 126 0 
+DESIGN ahb@gpio_tb
+VIEW struct.bd
+GRAPHIC 12657,0 128 0 
+DESIGN ahb@gpio_tb
+VIEW struct.bd
+GRAPHIC 12664,0 129 1 
+DESIGN ahb@gpio_tb
+VIEW struct.bd
+NO_GRAPHIC 147

06-07-08-09-SystemOnChip/AhbLiteComponents_test/hds/.xrf/ahbgpio_tester_entity.xrf

@@ -0,0 +1,48 @@
+DESIGN ahb@gpio_tester
+VIEW interface
+NO_GRAPHIC 0
+DESIGN ahb@gpio_tester
+VIEW interface
+GRAPHIC 50,0 8 0 
+DESIGN ahb@gpio_tester
+VIEW interface
+GRAPHIC 13,0 15 1 
+DESIGN ahb@gpio_tester
+VIEW interface
+GRAPHIC 668,0 20 0 
+DESIGN ahb@gpio_tester
+VIEW interface
+GRAPHIC 673,0 21 0 
+DESIGN ahb@gpio_tester
+VIEW interface
+GRAPHIC 683,0 22 0 
+DESIGN ahb@gpio_tester
+VIEW interface
+GRAPHIC 658,0 23 0 
+DESIGN ahb@gpio_tester
+VIEW interface
+GRAPHIC 663,0 24 0 
+DESIGN ahb@gpio_tester
+VIEW interface
+GRAPHIC 678,0 25 0 
+DESIGN ahb@gpio_tester
+VIEW interface
+GRAPHIC 688,0 26 0 
+DESIGN ahb@gpio_tester
+VIEW interface
+GRAPHIC 693,0 27 0 
+DESIGN ahb@gpio_tester
+VIEW interface
+GRAPHIC 698,0 28 0 
+DESIGN ahb@gpio_tester
+VIEW interface
+GRAPHIC 703,0 29 0 
+DESIGN ahb@gpio_tester
+VIEW interface
+GRAPHIC 708,0 30 0 
+DESIGN ahb@gpio_tester
+VIEW interface
+GRAPHIC 1,0 33 0 
+DESIGN ahb@gpio_tester
+VIEW interface
+GRAPHIC 1,0 34 0 

06-07-08-09-SystemOnChip/AhbLiteComponents_test/hds/.xrf/ahbuart_tb_entity.xrf

@@ -0,0 +1,12 @@
+DESIGN ahb@uart_tb
+VIEW symbol.sb
+NO_GRAPHIC 0
+DESIGN ahb@uart_tb
+VIEW symbol.sb
+GRAPHIC 53,0 8 0 
+DESIGN ahb@uart_tb
+VIEW symbol.sb
+GRAPHIC 1,0 11 0 
+DESIGN ahb@uart_tb
+VIEW symbol.sb
+GRAPHIC 1,0 12 0 

06-07-08-09-SystemOnChip/AhbLiteComponents_test/hds/.xrf/ahbuart_tb_struct.xrf

@@ -0,0 +1,213 @@
+DESIGN ahb@uart_tb
+VIEW struct.bd
+NO_GRAPHIC 0
+DESIGN ahb@uart_tb
+VIEW struct.bd
+GRAPHIC 187,0 9 0 
+DESIGN ahb@uart_tb
+VIEW struct.bd
+NO_GRAPHIC 14
+DESIGN ahb@uart_tb
+VIEW struct.bd
+GRAPHIC 0,0 18 2 
+DESIGN ahb@uart_tb
+VIEW struct.bd
+GRAPHIC 1,0 21 0 
+DESIGN ahb@uart_tb
+VIEW struct.bd
+NO_GRAPHIC 21
+DESIGN ahb@uart_tb
+VIEW struct.bd
+GRAPHIC 13297,0 28 0 
+DESIGN ahb@uart_tb
+VIEW struct.bd
+GRAPHIC 13305,0 29 0 
+DESIGN ahb@uart_tb
+VIEW struct.bd
+GRAPHIC 12627,0 30 0 
+DESIGN ahb@uart_tb
+VIEW struct.bd
+GRAPHIC 12563,0 31 0 
+DESIGN ahb@uart_tb
+VIEW struct.bd
+GRAPHIC 12587,0 32 0 
+DESIGN ahb@uart_tb
+VIEW struct.bd
+GRAPHIC 12579,0 33 0 
+DESIGN ahb@uart_tb
+VIEW struct.bd
+GRAPHIC 12555,0 34 0 
+DESIGN ahb@uart_tb
+VIEW struct.bd
+GRAPHIC 12571,0 35 0 
+DESIGN ahb@uart_tb
+VIEW struct.bd
+GRAPHIC 12595,0 36 0 
+DESIGN ahb@uart_tb
+VIEW struct.bd
+GRAPHIC 12611,0 37 0 
+DESIGN ahb@uart_tb
+VIEW struct.bd
+GRAPHIC 12619,0 38 0 
+DESIGN ahb@uart_tb
+VIEW struct.bd
+GRAPHIC 12603,0 39 0 
+DESIGN ahb@uart_tb
+VIEW struct.bd
+NO_GRAPHIC 40
+DESIGN ahb@uart_tb
+VIEW struct.bd
+NO_GRAPHIC 41
+LIBRARY AhbLiteComponents
+DESIGN ahb@uart
+VIEW student@version
+GRAPHIC 13707,0 43 0 
+DESIGN ahb@uart
+VIEW symbol.sb
+GRAPHIC 14,0 44 1 
+DESIGN ahb@uart
+VIEW symbol.sb
+GRAPHIC 2839,0 49 0 
+DESIGN ahb@uart
+VIEW symbol.sb
+GRAPHIC 2452,0 50 0 
+DESIGN ahb@uart
+VIEW symbol.sb
+GRAPHIC 2514,0 51 0 
+DESIGN ahb@uart
+VIEW symbol.sb
+GRAPHIC 2519,0 52 0 
+DESIGN ahb@uart
+VIEW symbol.sb
+GRAPHIC 2692,0 53 0 
+DESIGN ahb@uart
+VIEW symbol.sb
+GRAPHIC 2494,0 54 0 
+DESIGN ahb@uart
+VIEW symbol.sb
+GRAPHIC 2464,0 55 0 
+DESIGN ahb@uart
+VIEW symbol.sb
+GRAPHIC 2474,0 56 0 
+DESIGN ahb@uart
+VIEW symbol.sb
+GRAPHIC 2651,0 57 0 
+DESIGN ahb@uart
+VIEW symbol.sb
+GRAPHIC 2469,0 58 0 
+DESIGN ahb@uart
+VIEW symbol.sb
+GRAPHIC 2504,0 59 0 
+DESIGN ahb@uart
+VIEW symbol.sb
+GRAPHIC 2509,0 60 0 
+LIBRARY AhbLiteComponents_test
+DESIGN ahb@uart_tester
+VIEW test
+GRAPHIC 12657,0 63 0 
+DESIGN ahb@uart_tester
+VIEW interface
+GRAPHIC 14,0 64 1 
+DESIGN ahb@uart_tb
+VIEW struct.bd
+GRAPHIC 13307,0 68 0 
+DESIGN ahb@uart_tb
+VIEW struct.bd
+GRAPHIC 12589,0 69 0 
+DESIGN ahb@uart_tb
+VIEW struct.bd
+GRAPHIC 12581,0 70 0 
+DESIGN ahb@uart_tb
+VIEW struct.bd
+GRAPHIC 12573,0 71 0 
+DESIGN ahb@uart_tb
+VIEW struct.bd
+GRAPHIC 13299,0 72 0 
+DESIGN ahb@uart_tb
+VIEW struct.bd
+GRAPHIC 12629,0 73 0 
+DESIGN ahb@uart_tb
+VIEW struct.bd
+GRAPHIC 12565,0 74 0 
+DESIGN ahb@uart_tb
+VIEW struct.bd
+GRAPHIC 12557,0 75 0 
+DESIGN ahb@uart_tb
+VIEW struct.bd
+GRAPHIC 12597,0 76 0 
+DESIGN ahb@uart_tb
+VIEW struct.bd
+GRAPHIC 12613,0 77 0 
+DESIGN ahb@uart_tb
+VIEW struct.bd
+GRAPHIC 12621,0 78 0 
+DESIGN ahb@uart_tb
+VIEW struct.bd
+GRAPHIC 12605,0 79 0 
+LIBRARY AhbLiteComponents_test
+DESIGN ahb@uart_tb
+VIEW struct.bd
+NO_GRAPHIC 82
+DESIGN ahb@uart_tb
+VIEW struct.bd
+GRAPHIC 13707,0 85 0 
+DESIGN ahb@uart_tb
+VIEW struct.bd
+GRAPHIC 12657,0 86 0 
+DESIGN ahb@uart_tb
+VIEW struct.bd
+NO_GRAPHIC 89
+DESIGN ahb@uart_tb
+VIEW struct.bd
+NO_GRAPHIC 91
+DESIGN ahb@uart_tb
+VIEW struct.bd
+GRAPHIC 13707,0 93 0 
+DESIGN ahb@uart_tb
+VIEW struct.bd
+GRAPHIC 13714,0 94 1 
+DESIGN ahb@uart_tb
+VIEW struct.bd
+GRAPHIC 13299,0 99 0 
+DESIGN ahb@uart_tb
+VIEW struct.bd
+GRAPHIC 12629,0 100 0 
+DESIGN ahb@uart_tb
+VIEW struct.bd
+GRAPHIC 12565,0 101 0 
+DESIGN ahb@uart_tb
+VIEW struct.bd
+GRAPHIC 12557,0 102 0 
+DESIGN ahb@uart_tb
+VIEW struct.bd
+GRAPHIC 12597,0 103 0 
+DESIGN ahb@uart_tb
+VIEW struct.bd
+GRAPHIC 12613,0 104 0 
+DESIGN ahb@uart_tb
+VIEW struct.bd
+GRAPHIC 12621,0 105 0 
+DESIGN ahb@uart_tb
+VIEW struct.bd
+GRAPHIC 12605,0 106 0 
+DESIGN ahb@uart_tb
+VIEW struct.bd
+GRAPHIC 13307,0 107 0 
+DESIGN ahb@uart_tb
+VIEW struct.bd
+GRAPHIC 12589,0 108 0 
+DESIGN ahb@uart_tb
+VIEW struct.bd
+GRAPHIC 12581,0 109 0 
+DESIGN ahb@uart_tb
+VIEW struct.bd
+GRAPHIC 12573,0 110 0 
+DESIGN ahb@uart_tb
+VIEW struct.bd
+GRAPHIC 12657,0 112 0 
+DESIGN ahb@uart_tb
+VIEW struct.bd
+GRAPHIC 12664,0 113 1 
+DESIGN ahb@uart_tb
+VIEW struct.bd
+NO_GRAPHIC 131

06-07-08-09-SystemOnChip/AhbLiteComponents_test/hds/.xrf/ahbuart_tester_entity.xrf

@@ -0,0 +1,51 @@
+DESIGN ahb@uart_tester
+VIEW interface
+NO_GRAPHIC 0
+DESIGN ahb@uart_tester
+VIEW interface
+GRAPHIC 50,0 8 0 
+DESIGN ahb@uart_tester
+VIEW interface
+GRAPHIC 13,0 15 1 
+DESIGN ahb@uart_tester
+VIEW interface
+GRAPHIC 1269,0 19 0 
+DESIGN ahb@uart_tester
+VIEW interface
+GRAPHIC 1224,0 20 0 
+DESIGN ahb@uart_tester
+VIEW interface
+GRAPHIC 1229,0 21 0 
+DESIGN ahb@uart_tester
+VIEW interface
+GRAPHIC 1239,0 22 0 
+DESIGN ahb@uart_tester
+VIEW interface
+GRAPHIC 1264,0 23 0 
+DESIGN ahb@uart_tester
+VIEW interface
+GRAPHIC 1214,0 24 0 
+DESIGN ahb@uart_tester
+VIEW interface
+GRAPHIC 1219,0 25 0 
+DESIGN ahb@uart_tester
+VIEW interface
+GRAPHIC 1234,0 26 0 
+DESIGN ahb@uart_tester
+VIEW interface
+GRAPHIC 1244,0 27 0 
+DESIGN ahb@uart_tester
+VIEW interface
+GRAPHIC 1249,0 28 0 
+DESIGN ahb@uart_tester
+VIEW interface
+GRAPHIC 1254,0 29 0 
+DESIGN ahb@uart_tester
+VIEW interface
+GRAPHIC 1259,0 30 0 
+DESIGN ahb@uart_tester
+VIEW interface
+GRAPHIC 1,0 33 0 
+DESIGN ahb@uart_tester
+VIEW interface
+GRAPHIC 1,0 34 0 

06-07-08-09-SystemOnChip/AhbLiteComponents_test/hds/ahb@gpio_tb/struct.bd

@@ -74,23 +74,23 @@ value " "
 )
 (vvPair
 variable "HDLDir"
-value "C:\\dev\\sem-labs\\06-07-08-09-SystemOnChip\\Prefs\\..\\AhbLiteComponents_test\\hdl"
+value "C:\\Users\\remi.heredero\\GIT\\2024-sem-labs-herederoremi\\06-07-08-09-SystemOnChip\\Prefs\\..\\AhbLiteComponents_test\\hdl"
 )
 (vvPair
 variable "HDSDir"
-value "C:\\dev\\sem-labs\\06-07-08-09-SystemOnChip\\Prefs\\..\\AhbLiteComponents_test\\hds"
+value "C:\\Users\\remi.heredero\\GIT\\2024-sem-labs-herederoremi\\06-07-08-09-SystemOnChip\\Prefs\\..\\AhbLiteComponents_test\\hds"
 )
 (vvPair
 variable "SideDataDesignDir"
-value "C:\\dev\\sem-labs\\06-07-08-09-SystemOnChip\\Prefs\\..\\AhbLiteComponents_test\\hds\\ahb@gpio_tb\\struct.bd.info"
+value "C:\\Users\\remi.heredero\\GIT\\2024-sem-labs-herederoremi\\06-07-08-09-SystemOnChip\\Prefs\\..\\AhbLiteComponents_test\\hds\\ahb@gpio_tb\\struct.bd.info"
 )
 (vvPair
 variable "SideDataUserDir"
-value "C:\\dev\\sem-labs\\06-07-08-09-SystemOnChip\\Prefs\\..\\AhbLiteComponents_test\\hds\\ahb@gpio_tb\\struct.bd.user"
+value "C:\\Users\\remi.heredero\\GIT\\2024-sem-labs-herederoremi\\06-07-08-09-SystemOnChip\\Prefs\\..\\AhbLiteComponents_test\\hds\\ahb@gpio_tb\\struct.bd.user"
 )
 (vvPair
 variable "SourceDir"
-value "C:\\dev\\sem-labs\\06-07-08-09-SystemOnChip\\Prefs\\..\\AhbLiteComponents_test\\hds"
+value "C:\\Users\\remi.heredero\\GIT\\2024-sem-labs-herederoremi\\06-07-08-09-SystemOnChip\\Prefs\\..\\AhbLiteComponents_test\\hds"
 )
 (vvPair
 variable "appl"
@@ -114,15 +114,15 @@ value "%(unit)_%(view)_config"
 )
 (vvPair
 variable "d"
-value "C:\\dev\\sem-labs\\06-07-08-09-SystemOnChip\\Prefs\\..\\AhbLiteComponents_test\\hds\\ahb@gpio_tb"
+value "C:\\Users\\remi.heredero\\GIT\\2024-sem-labs-herederoremi\\06-07-08-09-SystemOnChip\\Prefs\\..\\AhbLiteComponents_test\\hds\\ahb@gpio_tb"
 )
 (vvPair
 variable "d_logical"
-value "C:\\dev\\sem-labs\\06-07-08-09-SystemOnChip\\Prefs\\..\\AhbLiteComponents_test\\hds\\ahbGpio_tb"
+value "C:\\Users\\remi.heredero\\GIT\\2024-sem-labs-herederoremi\\06-07-08-09-SystemOnChip\\Prefs\\..\\AhbLiteComponents_test\\hds\\ahbGpio_tb"
 )
 (vvPair
 variable "date"
-value "28.04.2023"
+value "19.04.2024"
 )
 (vvPair
 variable "day"
@@ -134,7 +134,7 @@ value "vendredi"
 )
 (vvPair
 variable "dd"
-value "28"
+value "19"
 )
 (vvPair
 variable "designName"
@@ -162,11 +162,11 @@ value "struct"
 )
 (vvPair
 variable "graphical_source_author"
-value "axel.amand"
+value "remi.heredero"
 )
 (vvPair
 variable "graphical_source_date"
-value "28.04.2023"
+value "19.04.2024"
 )
 (vvPair
 variable "graphical_source_group"
@@ -174,11 +174,11 @@ value "UNKNOWN"
 )
 (vvPair
 variable "graphical_source_host"
-value "WE7860"
+value "WE2330808"
 )
 (vvPair
 variable "graphical_source_time"
-value "15:06:49"
+value "14:16:25"
 )
 (vvPair
 variable "group"
@@ -186,7 +186,7 @@ value "UNKNOWN"
 )
 (vvPair
 variable "host"
-value "WE7860"
+value "WE2330808"
 )
 (vvPair
 variable "language"
@@ -222,11 +222,11 @@ value "avril"
 )
 (vvPair
 variable "p"
-value "C:\\dev\\sem-labs\\06-07-08-09-SystemOnChip\\Prefs\\..\\AhbLiteComponents_test\\hds\\ahb@gpio_tb\\struct.bd"
+value "C:\\Users\\remi.heredero\\GIT\\2024-sem-labs-herederoremi\\06-07-08-09-SystemOnChip\\Prefs\\..\\AhbLiteComponents_test\\hds\\ahb@gpio_tb\\struct.bd"
 )
 (vvPair
 variable "p_logical"
-value "C:\\dev\\sem-labs\\06-07-08-09-SystemOnChip\\Prefs\\..\\AhbLiteComponents_test\\hds\\ahbGpio_tb\\struct.bd"
+value "C:\\Users\\remi.heredero\\GIT\\2024-sem-labs-herederoremi\\06-07-08-09-SystemOnChip\\Prefs\\..\\AhbLiteComponents_test\\hds\\ahbGpio_tb\\struct.bd"
 )
 (vvPair
 variable "package_name"
@@ -306,7 +306,7 @@ value "struct"
 )
 (vvPair
 variable "time"
-value "15:06:49"
+value "14:16:25"
 )
 (vvPair
 variable "unit"
@@ -314,7 +314,7 @@ value "ahbGpio_tb"
 )
 (vvPair
 variable "user"
-value "axel.amand"
+value "remi.heredero"
 )
 (vvPair
 variable "version"
@@ -326,11 +326,11 @@ value "struct"
 )
 (vvPair
 variable "year"
-value "2023"
+value "2024"
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 (vvPair
 variable "yy"
-value "23"
+value "24"
 )
 ]
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@@ -668,8 +668,7 @@ isHidden 1
 font "Courier New,9,0"
 )
 xt "0,0,15500,1200"
-st "SIGNAL hReset_n : std_uLogic
-"
+st "SIGNAL hReset_n : std_uLogic"
 )
 )
 *13 (Net
@@ -687,8 +686,7 @@ isHidden 1
 font "Courier New,9,0"
 )
 xt "0,0,15500,1200"
-st "SIGNAL hClk     : std_uLogic
-"
+st "SIGNAL hClk     : std_uLogic"
 )
 )
 *14 (Net
@@ -706,8 +704,7 @@ isHidden 1
 font "Courier New,9,0"
 )
 xt "0,0,15500,1200"
-st "SIGNAL hResp    : std_uLogic
-"
+st "SIGNAL hResp    : std_uLogic"
 )
 )
 *15 (Net
@@ -725,8 +722,7 @@ isHidden 1
 font "Courier New,9,0"
 )
 xt "0,0,15500,1200"
-st "SIGNAL hReady   : std_uLogic
-"
+st "SIGNAL hReady   : std_uLogic"
 )
 )
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@@ -745,8 +741,7 @@ isHidden 1
 font "Courier New,9,0"
 )
 xt "0,0,32000,1200"
-st "SIGNAL hRData   : std_ulogic_vector(ahbDataBitNb-1 DOWNTO 0)
-"
+st "SIGNAL hRData   : std_ulogic_vector(ahbDataBitNb-1 DOWNTO 0)"
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 )
 *17 (Net
@@ -764,8 +759,7 @@ isHidden 1
 font "Courier New,9,0"
 )
 xt "0,0,15500,1200"
-st "SIGNAL hSel     : std_uLogic
-"
+st "SIGNAL hSel     : std_uLogic"
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 )
 *18 (Net
@@ -783,8 +777,7 @@ isHidden 1
 font "Courier New,9,0"
 )
 xt "0,0,15500,1200"
-st "SIGNAL hWrite   : std_uLogic
-"
+st "SIGNAL hWrite   : std_uLogic"
 )
 )
 *19 (Net
@@ -803,8 +796,7 @@ isHidden 1
 font "Courier New,9,0"
 )
 xt "0,0,32500,1200"
-st "SIGNAL hTrans   : std_ulogic_vector(ahbTransBitNb-1 DOWNTO 0)
-"
+st "SIGNAL hTrans   : std_ulogic_vector(ahbTransBitNb-1 DOWNTO 0)"
 )
 )
 *20 (Net
@@ -823,8 +815,7 @@ isHidden 1
 font "Courier New,9,0"
 )
 xt "0,0,32000,1200"
-st "SIGNAL hWData   : std_ulogic_vector(ahbDataBitNb-1 DOWNTO 0)
-"
+st "SIGNAL hWData   : std_ulogic_vector(ahbDataBitNb-1 DOWNTO 0)"
 )
 )
 *21 (Net
@@ -843,8 +834,7 @@ isHidden 1
 font "Courier New,9,0"
 )
 xt "0,0,30000,1200"
-st "SIGNAL hAddr    : unsigned( ahbAddressBitNb-1 DOWNTO 0 )
-"
+st "SIGNAL hAddr    : unsigned( ahbAddressBitNb-1 DOWNTO 0 )"
 )
 )
 *22 (Blk
@@ -1616,8 +1606,7 @@ isHidden 1
 font "Courier New,9,0"
 )
 xt "0,0,28000,1200"
-st "SIGNAL ioEn     : std_ulogic_vector(ioNb-1 DOWNTO 0)
-"
+st "SIGNAL ioEn     : std_ulogic_vector(ioNb-1 DOWNTO 0)"
 )
 )
 *48 (Net
@@ -1636,8 +1625,7 @@ isHidden 1
 font "Courier New,9,0"
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 xt "0,0,28000,1200"
-st "SIGNAL ioOut    : std_ulogic_vector(ioNb-1 DOWNTO 0)
-"
+st "SIGNAL ioOut    : std_ulogic_vector(ioNb-1 DOWNTO 0)"
 )
 )
 *49 (Net
@@ -1656,8 +1644,7 @@ isHidden 1
 font "Courier New,9,0"
 )
 xt "0,0,28000,1200"
-st "SIGNAL ioIn     : std_ulogic_vector(ioNb-1 DOWNTO 0)
-"
+st "SIGNAL ioIn     : std_ulogic_vector(ioNb-1 DOWNTO 0)"
 )
 )
 *50 (Net
@@ -1676,8 +1663,7 @@ isHidden 1
 font "Courier New,9,0"
 )
 xt "0,0,27500,1200"
-st "SIGNAL io       : std_logic_vector(ioNb-1 DOWNTO 0)
-"
+st "SIGNAL io       : std_logic_vector(ioNb-1 DOWNTO 0)"
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 )
 *51 (Wire
@@ -2351,8 +2337,8 @@ tm "BdCompilerDirectivesTextMgr"
 ]
 associable 1
 )
-windowSize "-8,-8,1928,1048"
-viewArea "27426,17402,170102,94921"
+windowSize "164,195,1039,926"
+viewArea "49240,25632,103588,71748"
 cachedDiagramExtent "0,0,138000,93000"
 pageSetupInfo (PageSetupInfo
 ptrCmd "\\\\SUN\\PREA309_HPLJ3005DN.PRINTERS.SYSTEM.SION.HEVs,winspool,"
@@ -2376,7 +2362,7 @@ boundaryWidth 0
 )
 hasePageBreakOrigin 1
 pageBreakOrigin "29000,19000"
-lastUid 13522,0
+lastUid 13575,0
 defaultCommentText (CommentText
 shape (Rectangle
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06-07-08-09-SystemOnChip/Prefs/hds_team/v2019.2/hds_team_prefs.bak

@@ -0,0 +1,55 @@
+version "8.0"
+RenoirTeamPreferences [
+(BaseTeamPreferences
+version "1.1"
+verConcat 0
+ttDGProps [
+]
+fcDGProps [
+]
+smDGProps [
+]
+asmDGProps [
+]
+bdDGProps [
+]
+syDGProps [
+]
+)
+(VersionControlTeamPreferences
+version "1.1"
+VMPlugin ""
+VMRepository "$HDS_HOME/examples/hds_scratch/hds_repository"
+VMRcsHdsRepository "$HDS_HOME/examples/hds_scratch/hds_repository/%(library)/hds_vm"
+VMRcsHdlRepository "$HDS_HOME/examples/hds_scratch/hds_repository/%(library)/hdl_vm"
+VMCvsHdsRepository "$HDS_HOME/examples/hds_scratch/hds_repository/hds_vm"
+VMCvsHdlRepository "$HDS_HOME/examples/hds_scratch/hds_repository/hdl_vm"
+VMCVSmkIIHdsRepository "$HDS_HOME/examples/hds_scratch/hds_repository/hds_vm"
+VMCVSmkIIHdlRepository "$HDS_HOME/examples/hds_scratch/hds_repository"
+VMVssHdsRepository "$/hds_scratch/hds_repository/%(library)/hds_vm"
+VMVssHdlRepository "$/hds_scratch/hds_repository/%(library)/hdl_vm"
+VMDsHdsRepository "sync://<host_name>:<port>/hds_scratch/hds_repository/hds_vm"
+VMDsHdlRepository "sync://<host_name>:<port>/hds_scratch/hds_repository/hdl_vm"
+VMPvcsHdsRepository "$HDS_HOME/examples/hds_scratch/hds_repository/hds_vm"
+VMPvcsHdlRepository "$HDS_HOME/examples/hds_scratch/hds_repository/hdl_vm"
+VMSvnHdlRepository ""
+VMDefaultView 1
+VMCurrentDesignHierarchyOnly 0
+VMUserData 1
+VMGeneratedHDL 0
+VMVerboseMode 0
+VMAlwaysEmpty 0
+VMSetTZ 1
+VMSymbol 1
+VMCurrentDesignHierarchy 0
+VMMultipleRepositoryMode 0
+VMSnapshotViewMode 0
+backupNameClashes 1
+clearCaseMaster 0
+)
+(CustomizeTeamPreferences
+version "1.1"
+FileTypes [
+]
+)
+]

06-07-08-09-SystemOnChip/Prefs/hds_user/v2019.2/hds_user_prefs

@@ -1280,6 +1280,7 @@ projectPaths [
 "C:\\work\\repo\\edu\\sem\\labo\\solution\\sem_labs\\06-07-08-09-SystemOnChip\\Prefs\\hds.hdp"
 "C:\\work\\edu\\sem\\labo\\sem_labs\\06-07-08-09-SystemOnChip\\Prefs\\hds.hdp"
 "C:\\dev\\sem-labs\\06-07-08-09-SystemOnChip\\Prefs\\hds.hdp"
+"C:\\Users\\remi.heredero\\GIT\\2024-sem-labs-herederoremi\\06-07-08-09-SystemOnChip\\Prefs\\hds.hdp"
 ]
 libMappingsRootDir ""
 teamLibMappingsRootDir ""
@@ -1300,288 +1301,144 @@ exportedDirectories [
 exportStdIncludeRefs 1
 exportStdPackageRefs 1
 )
-printerName "\\\\vmenpprint1.hevs.ch\\VS-FOLLOWME-PRN"
+printerName "\\\\vmenpprint1\\VS-ENP.23.N308-PRN"
 pageSizes [
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-name "12\" x 18\""
-type 512
-width 1106
-height 1658
+name "Letter"
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+height 1013
 )
 (PageSizeInfo
-name "11\" x 17\""
-type 17
-width 1013
-height 1566
-)
-(PageSizeInfo
-name "Legal (8,5\" x 14\")"
+name "Legal"
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 height 1290
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 (PageSizeInfo
-name "Letter (8,5\" x 11\")"
-width 783
-height 1013
-)
-(PageSizeInfo
-name "Executive (7,25\"x10,5\")"
-type 7
-width 667
-height 967
-)
-(PageSizeInfo
-name "5,5\" x 8,5\""
+name "Statement"
 type 6
 width 506
 height 783
 )
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-name "A3 (297 x 420 mm)"
+name "Executive"
+type 7
+width 667
+height 967
+)
+(PageSizeInfo
+name "A3"
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-name "A4 (210 x 297 mm)"
+name "A4"
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-name "A5 (148 x 210 mm)"
+name "A5"
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-width 538
+width 536
 height 761
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 (PageSizeInfo
-name "A6 (105 x 148 mm)"
-type 70
-width 380
-height 538
-)
-(PageSizeInfo
-name "B4 JIS (257 x 364 mm)"
+name "B4 (JIS)"
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 height 1320
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-name "B5 JIS (182 x 257 mm)"
+name "B5 (JIS)"
 type 13
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 height 932
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 (PageSizeInfo
-name "B6 JIS (128 x 182 mm)"
-type 88
-width 464
-height 660
+name "11×17"
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+height 1566
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-name "8\" x 13\""
-type 518
-width 737
-height 1198
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-name "8.5\" x 13.4\""
-type 551
-width 783
-height 1235
-)
-(PageSizeInfo
-name "Com10 Env.(4,125\"x9,5\")"
+name "Envelope #10"
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-width 380
+width 379
 height 875
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-name "Env.Monar.(3,875\"x7,5\")"
-type 37
-width 357
-height 691
-)
-(PageSizeInfo
-name "Env. DL (110 x 220 mm)"
+name "Envelope DL"
 type 27
 width 399
 height 798
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 (PageSizeInfo
-name "Env. C6 (114 x 162 mm)"
-type 31
-width 413
-height 587
-)
-(PageSizeInfo
-name "Env. C5 (162 x 229 mm)"
+name "Envelope C5"
 type 28
 width 587
 height 830
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 (PageSizeInfo
-name "8K (267 x 390 mm)"
-type 520
-width 968
-height 1415
+name "Envelope B5"
+type 34
+width 638
+height 907
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 (PageSizeInfo
-name "16K (195 x 267 mm)"
-type 521
-width 707
-height 968
+name "Envelope Monarch"
+type 37
+width 357
+height 691
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 (PageSizeInfo
-name "8,25\" x 14\""
-type 522
-width 760
-height 1290
+name "Japanese Postcard"
+type 43
+width 362
+height 536
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 (PageSizeInfo
-name "11\" x 14\""
-type 524
-width 1013
-height 1290
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+type 70
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+height 536
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 (PageSizeInfo
-name "13\" x 19,2\""
-type 525
-width 1198
-height 1769
+name "Double Japan Postcard Rotated"
+type 82
+width 536
+height 725
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 (PageSizeInfo
-name "13\" x 19\""
-type 526
-width 1198
-height 1751
+name "Executive (JIS)"
+type 119
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+height 1196
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 (PageSizeInfo
-name "12,6\" x 19,2\""
-type 527
-width 1161
-height 1769
+name "Oficio 8.5x13"
+type 120
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+height 1198
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-name "12,6\" x 18,5\""
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-width 1161
-height 1704
-)
-(PageSizeInfo
-name "13\" x 18\""
-type 529
-width 1198
+name "12x18"
+type 121
+width 1105
 height 1658
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-type 16
-width 921
-height 1290
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-name "10\" x 15\""
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-name "11\" x 15\""
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-name "SRA3 (320 x 450 mm)"
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-(PageSizeInfo
-name "Format papier personnalisé"
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-height 1013
-)
-(PageSizeInfo
-name "Custom Paper Size1(215,9 x 279,4 mm)"
-type 257
-width 783
-height 1013
-)
-(PageSizeInfo
-name "Custom Paper Size2(215,9 x 279,4 mm)"
-type 258
-width 783
-height 1013
-)
-(PageSizeInfo
-name "Custom Paper Size3(215,9 x 279,4 mm)"
-type 259
-width 783
-height 1013
-)
-(PageSizeInfo
-name "Custom Paper Size4(215,9 x 279,4 mm)"
-type 260
-width 783
-height 1013
-)
-(PageSizeInfo
-name "Custom Paper Size5(215,9 x 279,4 mm)"
-type 261
-width 783
-height 1013
-)
-(PageSizeInfo
-name "Custom Paper Size6(215,9 x 279,4 mm)"
-type 262
-width 783
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-)
-(PageSizeInfo
-name "Custom Paper Size7(215,9 x 279,4 mm)"
-type 263
-width 783
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-)
-(PageSizeInfo
-name "Custom Paper Size8(215,9 x 279,4 mm)"
-type 264
-width 783
-height 1013
-)
-(PageSizeInfo
-name "Custom Paper Size9(215,9 x 279,4 mm)"
-type 265
-width 783
-height 1013
-)
-(PageSizeInfo
-name "Custom Paper Size10(215,9 x 279,4 mm)"
-type 266
-width 783
-height 1013
+name "16K 197x273 mm"
+type 140
+width 714
+height 990
 )
 ]
 exportPageSetupInfo (PageSetupInfo
@@ -4292,7 +4149,7 @@ hdsWorkspaceLocation ""
 relativeLibraryRootDir ""
 vmLabelLatestDontAskAgain 0
 vmLabelWorkspaceDontAskAgain 0
-logWindowGeometry "636x406+-823+276"
+logWindowGeometry "636x514+308+98"
 diagramBrowserTabNo 0
 showInsertPortHint 0
 showContentFirstTime 0
@@ -6174,6 +6031,96 @@ disableFilters 1
 ]
 layoutExpression "V(H(A(C(DesignUnits),C(LogicalObjects)),A(C(Files))),A(C(DesignHierarchy)))"
 )
+(Viewpoint_v2
+name "Parse Errors Report"
+TreeListVPDatas [
+(TreeListVPData
+theList "Hierarchy"
+columns [
+(TreeListVPData_Column
+name "Design Unit Name"
+displayName ""
+width 150
+)
+(TreeListVPData_Column
+name "Extends"
+displayName ""
+width 100
+)
+(TreeListVPData_Column
+name "Name"
+displayName ""
+width 250
+)
+(TreeListVPData_Column
+name "Library"
+displayName ""
+width 120
+)
+]
+filterString ""
+accessRights 2
+)
+]
+SmartTableVPDatas [
+(SmartTableVPData
+theList "Logical Objects"
+columns [
+(SmartTableVPData_Column
+name "Parse Error"
+width 22
+alignment 0
+)
+(SmartTableVPData_Column
+name "File Name"
+width 150
+alignment 0
+)
+(SmartTableVPData_Column
+name "Language"
+width 100
+alignment 0
+)
+(SmartTableVPData_Column
+name "Library"
+width 120
+alignment 0
+)
+(SmartTableVPData_Column
+name "Location"
+width 200
+alignment 0
+)
+(SmartTableVPData_Column
+name "Absolute Path"
+width 14
+alignment 1
+)
+]
+filterNames [
+"Architectures and Modules"
+"Configurations"
+"Entities"
+"Files"
+"Instances"
+"Packages"
+"SV Classes"
+"SV Interfaces"
+"SV Packages"
+"SV Program Blocks"
+]
+filterString "1"
+filterColumn "Parse Error"
+matchCase 0
+matchWholeWordOnly 0
+regularExpression 1
+groupNames [
+]
+disableFilters 1
+)
+]
+layoutExpression "V(A(C(LogicalObjects)))"
+)
 ]
 WorkTabs [
 (WorkTab
@@ -6369,6 +6316,7 @@ activeViewpointIdx 0
 )
 ]
 ViewpointsOnOutlookBar [
+"Parse Errors Report"
 ]
 lastActiveViewpoint "Default Viewpoint"
 expandedTemplateNodes [
@@ -6384,11 +6332,11 @@ size 180
 ]
 displayHierarchy 0
 xPos 0
-yPos 0
-width 1936
-height 1056
+yPos 9
+width 974
+height 1047
 activeSidePanelTab 2
-activeLibraryTab 1
+activeLibraryTab 5
 sidePanelSize 278
 showUnixHiddenFiles 0
 componentBrowserXpos 569

06-07-08-09-SystemOnChip/Prefs/hds_user/v2019.2/tasks/modelsim_simulate.tsk

@@ -46,7 +46,7 @@ settingsMap [
 "GlitchGeneration"
 "1"
 "InitCmd"
-"$SIMULATION_DIR/beamerSoc.do"
+"C:/Users/remi.heredero/GIT/2024-sem-labs-herederoremi/06-07-08-09-SystemOnChip/Simulation/ahbUart.do"
 "LogFile"
 ""
 "RemoteHost"