65 lines
1.9 KiB
VHDL
65 lines
1.9 KiB
VHDL
ARCHITECTURE studentVersion OF interpolatorCalculatePolynom IS
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subtype sample_type is signed(coeffBitNb-1+oversamplingBitNb+10 DOWNTO 0);
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type order0 is array (0 to 0) of sample_type;
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type order1 is array (0 to 1) of sample_type;
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type order2 is array (0 to 2) of sample_type;
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type order3 is array (0 to 3) of sample_type;
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signal cA: order3;
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signal cB: order2;
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signal cC: order1;
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signal cD: order0;
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signal bufferSine: sample_type;
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BEGIN
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process(clock, reset) begin
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if reset = '1' then
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cA <= (others => (others => '0'));
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cB <= (others => (others => '0'));
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cC <= (others => (others => '0'));
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cD <= (others => (others => '0'));
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bufferSine <= (others => '0');
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elsif rising_edge(clock) then
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if restartPolynom = '1' then
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cA(3) <= (others => '0');
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cA(2) <= (others => '0');
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cA(1) <= (others => '0');
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cA(0) <= resize(a,sample_type'high+1);
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cB(2) <= (others => '0');
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cB(1) <= (others => '0');
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cB(0) <= resize(b,sample_type'high+1);
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cC(1) <= (others => '0');
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cC(0) <= resize(c,sample_type'high+1);
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cD(0) <= resize(d,sample_type'high+1);
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else
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cC(1) <= cC(0) + cC(1);
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cB(2) <= cB(2) + resize(2*cB(1),sample_type'high+1) + cB(0);
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cB(1) <= resize(b,sample_type'high+1) + cB(1);
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cA(3) <= cA(3) + resize(3*cA(2),sample_type'high+1) + resize(3*cA(1),sample_type'high+1) + cA(0);
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cA(2) <= cA(2) + resize(2*cA(1),sample_type'high+1) + cA(0);
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cA(1) <= resize(A,sample_type'high+1) + cA(1);
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end if;
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bufferSine <= bufferSine + shift_right(cA(3)+cB(2)+cC(1)+cD(0),0);
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end if;
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end process;
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process(cA, cB, cC, cD) begin
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--bufferSine <= bufferSine + cA(3)+cB(2)+cC(1)+cD(0);
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end process;
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--sampleOut <= resize(shift_right(cA(3)+cB(2)+cC(1)+cD(0),oversamplingBitNb),signalBitNb);
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sampleOut <= resize(bufferSine,signalBitNb);
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END ARCHITECTURE studentVersion;
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