1654 lines
21 KiB
Plaintext
1654 lines
21 KiB
Plaintext
DocumentHdrVersion "1.1"
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Header (DocumentHdr
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version 2
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dialect 11
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dmPackageRefs [
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(DmPackageRef
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library "ieee"
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unitName "std_logic_1164"
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)
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(DmPackageRef
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library "ieee"
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unitName "numeric_std"
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itemName "ALL"
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)
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]
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libraryRefs [
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"ieee"
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]
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)
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version "27.1"
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appVersion "2019.2 (Build 5)"
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model (Symbol
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commonDM (CommonDM
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ldm (LogicalDM
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suid 20,0
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usingSuid 1
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emptyRow *1 (LEmptyRow
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)
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uid 88,0
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optionalChildren [
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*2 (RefLabelRowHdr
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)
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*3 (TitleRowHdr
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)
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|
*4 (FilterRowHdr
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)
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|
*5 (RefLabelColHdr
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tm "RefLabelColHdrMgr"
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)
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|
*6 (RowExpandColHdr
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tm "RowExpandColHdrMgr"
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)
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|
*7 (GroupColHdr
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tm "GroupColHdrMgr"
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)
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*8 (NameColHdr
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tm "NameColHdrMgr"
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)
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*9 (ModeColHdr
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tm "ModeColHdrMgr"
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)
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*10 (TypeColHdr
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tm "TypeColHdrMgr"
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)
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|
*11 (BoundsColHdr
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tm "BoundsColHdrMgr"
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)
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|
*12 (InitColHdr
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|
tm "InitColHdrMgr"
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)
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|
*13 (EolColHdr
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tm "EolColHdrMgr"
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)
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|
*14 (LogPort
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port (LogicalPort
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m 1
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decl (Decl
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n "clock"
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t "std_ulogic"
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o 1
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suid 16,0
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)
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)
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uid 380,0
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)
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*15 (LogPort
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port (LogicalPort
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decl (Decl
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n "lowpassOut"
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t "unsigned"
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b "(signalBitNb-1 DOWNTO 0)"
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o 3
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suid 17,0
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)
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)
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uid 382,0
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)
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*16 (LogPort
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port (LogicalPort
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m 1
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decl (Decl
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n "parallelIn"
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t "unsigned"
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b "(signalBitNb-1 DOWNTO 0)"
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o 4
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suid 18,0
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)
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)
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uid 384,0
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)
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*17 (LogPort
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port (LogicalPort
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m 1
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decl (Decl
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n "reset"
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t "std_ulogic"
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o 5
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suid 19,0
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)
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)
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uid 386,0
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)
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*18 (LogPort
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port (LogicalPort
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decl (Decl
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n "serialOut"
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t "std_ulogic"
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o 6
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suid 20,0
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)
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)
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uid 388,0
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)
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]
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)
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pdm (PhysicalDM
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|
displayShortBounds 1
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|
editShortBounds 1
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|
uid 101,0
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|
optionalChildren [
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|
*19 (Sheet
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sheetRow (SheetRow
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headerVa (MVa
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|
cellColor "49152,49152,49152"
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fontColor "0,0,0"
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font "Tahoma,10,0"
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)
|
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cellVa (MVa
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cellColor "65535,65535,65535"
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|
fontColor "0,0,0"
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font "Tahoma,10,0"
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)
|
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groupVa (MVa
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cellColor "39936,56832,65280"
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fontColor "0,0,0"
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font "Tahoma,10,0"
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)
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emptyMRCItem *20 (MRCItem
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litem &1
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pos 5
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dimension 20
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)
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uid 103,0
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optionalChildren [
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*21 (MRCItem
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litem &2
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pos 0
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dimension 20
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uid 104,0
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)
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*22 (MRCItem
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litem &3
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pos 1
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dimension 23
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uid 105,0
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)
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*23 (MRCItem
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litem &4
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pos 2
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hidden 1
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dimension 20
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uid 106,0
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)
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*24 (MRCItem
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litem &14
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pos 0
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dimension 20
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uid 381,0
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)
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*25 (MRCItem
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litem &15
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pos 1
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dimension 20
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uid 383,0
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)
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*26 (MRCItem
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litem &16
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pos 2
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dimension 20
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uid 385,0
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)
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*27 (MRCItem
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litem &17
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pos 3
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dimension 20
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uid 387,0
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)
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*28 (MRCItem
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litem &18
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pos 4
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dimension 20
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uid 389,0
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)
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]
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)
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sheetCol (SheetCol
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propVa (MVa
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cellColor "0,49152,49152"
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fontColor "0,0,0"
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font "Tahoma,10,0"
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textAngle 90
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)
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uid 107,0
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optionalChildren [
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*29 (MRCItem
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litem &5
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pos 0
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dimension 20
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uid 108,0
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)
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*30 (MRCItem
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litem &7
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pos 1
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dimension 50
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uid 109,0
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)
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*31 (MRCItem
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litem &8
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pos 2
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dimension 100
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uid 110,0
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)
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*32 (MRCItem
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litem &9
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pos 3
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dimension 50
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uid 111,0
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)
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*33 (MRCItem
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litem &10
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pos 4
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dimension 100
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uid 112,0
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)
|
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*34 (MRCItem
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litem &11
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pos 5
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dimension 100
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|
uid 113,0
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)
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*35 (MRCItem
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litem &12
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pos 6
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dimension 50
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|
uid 114,0
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)
|
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*36 (MRCItem
|
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litem &13
|
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pos 7
|
|
dimension 80
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|
uid 115,0
|
|
)
|
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]
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)
|
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fixedCol 4
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|
fixedRow 2
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|
name "Ports"
|
|
uid 102,0
|
|
vaOverrides [
|
|
]
|
|
)
|
|
]
|
|
)
|
|
uid 87,0
|
|
)
|
|
genericsCommonDM (CommonDM
|
|
ldm (LogicalDM
|
|
emptyRow *37 (LEmptyRow
|
|
)
|
|
uid 117,0
|
|
optionalChildren [
|
|
*38 (RefLabelRowHdr
|
|
)
|
|
*39 (TitleRowHdr
|
|
)
|
|
*40 (FilterRowHdr
|
|
)
|
|
*41 (RefLabelColHdr
|
|
tm "RefLabelColHdrMgr"
|
|
)
|
|
*42 (RowExpandColHdr
|
|
tm "RowExpandColHdrMgr"
|
|
)
|
|
*43 (GroupColHdr
|
|
tm "GroupColHdrMgr"
|
|
)
|
|
*44 (NameColHdr
|
|
tm "GenericNameColHdrMgr"
|
|
)
|
|
*45 (TypeColHdr
|
|
tm "GenericTypeColHdrMgr"
|
|
)
|
|
*46 (InitColHdr
|
|
tm "GenericValueColHdrMgr"
|
|
)
|
|
*47 (PragmaColHdr
|
|
tm "GenericPragmaColHdrMgr"
|
|
)
|
|
*48 (EolColHdr
|
|
tm "GenericEolColHdrMgr"
|
|
)
|
|
*49 (LogGeneric
|
|
generic (GiElement
|
|
name "signalBitNb"
|
|
type "positive"
|
|
value "16"
|
|
)
|
|
uid 166,0
|
|
)
|
|
*50 (LogGeneric
|
|
generic (GiElement
|
|
name "clockFrequency"
|
|
type "real"
|
|
value "60.0E6"
|
|
)
|
|
uid 330,0
|
|
)
|
|
]
|
|
)
|
|
pdm (PhysicalDM
|
|
displayShortBounds 1
|
|
editShortBounds 1
|
|
uid 129,0
|
|
optionalChildren [
|
|
*51 (Sheet
|
|
sheetRow (SheetRow
|
|
headerVa (MVa
|
|
cellColor "49152,49152,49152"
|
|
fontColor "0,0,0"
|
|
font "Tahoma,10,0"
|
|
)
|
|
cellVa (MVa
|
|
cellColor "65535,65535,65535"
|
|
fontColor "0,0,0"
|
|
font "Tahoma,10,0"
|
|
)
|
|
groupVa (MVa
|
|
cellColor "39936,56832,65280"
|
|
fontColor "0,0,0"
|
|
font "Tahoma,10,0"
|
|
)
|
|
emptyMRCItem *52 (MRCItem
|
|
litem &37
|
|
pos 2
|
|
dimension 20
|
|
)
|
|
uid 131,0
|
|
optionalChildren [
|
|
*53 (MRCItem
|
|
litem &38
|
|
pos 0
|
|
dimension 20
|
|
uid 132,0
|
|
)
|
|
*54 (MRCItem
|
|
litem &39
|
|
pos 1
|
|
dimension 23
|
|
uid 133,0
|
|
)
|
|
*55 (MRCItem
|
|
litem &40
|
|
pos 2
|
|
hidden 1
|
|
dimension 20
|
|
uid 134,0
|
|
)
|
|
*56 (MRCItem
|
|
litem &49
|
|
pos 0
|
|
dimension 20
|
|
uid 167,0
|
|
)
|
|
*57 (MRCItem
|
|
litem &50
|
|
pos 1
|
|
dimension 20
|
|
uid 331,0
|
|
)
|
|
]
|
|
)
|
|
sheetCol (SheetCol
|
|
propVa (MVa
|
|
cellColor "0,49152,49152"
|
|
fontColor "0,0,0"
|
|
font "Tahoma,10,0"
|
|
textAngle 90
|
|
)
|
|
uid 135,0
|
|
optionalChildren [
|
|
*58 (MRCItem
|
|
litem &41
|
|
pos 0
|
|
dimension 20
|
|
uid 136,0
|
|
)
|
|
*59 (MRCItem
|
|
litem &43
|
|
pos 1
|
|
dimension 50
|
|
uid 137,0
|
|
)
|
|
*60 (MRCItem
|
|
litem &44
|
|
pos 2
|
|
dimension 100
|
|
uid 138,0
|
|
)
|
|
*61 (MRCItem
|
|
litem &45
|
|
pos 3
|
|
dimension 100
|
|
uid 139,0
|
|
)
|
|
*62 (MRCItem
|
|
litem &46
|
|
pos 4
|
|
dimension 50
|
|
uid 140,0
|
|
)
|
|
*63 (MRCItem
|
|
litem &47
|
|
pos 5
|
|
dimension 50
|
|
uid 141,0
|
|
)
|
|
*64 (MRCItem
|
|
litem &48
|
|
pos 6
|
|
dimension 80
|
|
uid 142,0
|
|
)
|
|
]
|
|
)
|
|
fixedCol 3
|
|
fixedRow 2
|
|
name "Ports"
|
|
uid 130,0
|
|
vaOverrides [
|
|
]
|
|
)
|
|
]
|
|
)
|
|
uid 116,0
|
|
type 1
|
|
)
|
|
VExpander (VariableExpander
|
|
vvMap [
|
|
(vvPair
|
|
variable "HDLDir"
|
|
value "C:\\dev\\sem-labs\\03-DigitalToAnalogConverter\\Prefs\\..\\DigitalToAnalogConverter_test\\hdl"
|
|
)
|
|
(vvPair
|
|
variable "HDSDir"
|
|
value "C:\\dev\\sem-labs\\03-DigitalToAnalogConverter\\Prefs\\..\\DigitalToAnalogConverter_test\\hds"
|
|
)
|
|
(vvPair
|
|
variable "SideDataDesignDir"
|
|
value "C:\\dev\\sem-labs\\03-DigitalToAnalogConverter\\Prefs\\..\\DigitalToAnalogConverter_test\\hds\\@d@a@c_tester\\interface.info"
|
|
)
|
|
(vvPair
|
|
variable "SideDataUserDir"
|
|
value "C:\\dev\\sem-labs\\03-DigitalToAnalogConverter\\Prefs\\..\\DigitalToAnalogConverter_test\\hds\\@d@a@c_tester\\interface.user"
|
|
)
|
|
(vvPair
|
|
variable "SourceDir"
|
|
value "C:\\dev\\sem-labs\\03-DigitalToAnalogConverter\\Prefs\\..\\DigitalToAnalogConverter_test\\hds"
|
|
)
|
|
(vvPair
|
|
variable "appl"
|
|
value "HDL Designer"
|
|
)
|
|
(vvPair
|
|
variable "arch_name"
|
|
value "interface"
|
|
)
|
|
(vvPair
|
|
variable "asm_file"
|
|
value "beamer.asm"
|
|
)
|
|
(vvPair
|
|
variable "concat_file"
|
|
value "concatenated"
|
|
)
|
|
(vvPair
|
|
variable "config"
|
|
value "%(unit)_%(view)_config"
|
|
)
|
|
(vvPair
|
|
variable "d"
|
|
value "C:\\dev\\sem-labs\\03-DigitalToAnalogConverter\\Prefs\\..\\DigitalToAnalogConverter_test\\hds\\@d@a@c_tester"
|
|
)
|
|
(vvPair
|
|
variable "d_logical"
|
|
value "C:\\dev\\sem-labs\\03-DigitalToAnalogConverter\\Prefs\\..\\DigitalToAnalogConverter_test\\hds\\DAC_tester"
|
|
)
|
|
(vvPair
|
|
variable "date"
|
|
value "28.04.2023"
|
|
)
|
|
(vvPair
|
|
variable "day"
|
|
value "ven."
|
|
)
|
|
(vvPair
|
|
variable "day_long"
|
|
value "vendredi"
|
|
)
|
|
(vvPair
|
|
variable "dd"
|
|
value "28"
|
|
)
|
|
(vvPair
|
|
variable "designName"
|
|
value "$DESIGN_NAME"
|
|
)
|
|
(vvPair
|
|
variable "entity_name"
|
|
value "DAC_tester"
|
|
)
|
|
(vvPair
|
|
variable "ext"
|
|
value "<TBD>"
|
|
)
|
|
(vvPair
|
|
variable "f"
|
|
value "interface"
|
|
)
|
|
(vvPair
|
|
variable "f_logical"
|
|
value "interface"
|
|
)
|
|
(vvPair
|
|
variable "f_noext"
|
|
value "interface"
|
|
)
|
|
(vvPair
|
|
variable "graphical_source_author"
|
|
value "axel.amand"
|
|
)
|
|
(vvPair
|
|
variable "graphical_source_date"
|
|
value "28.04.2023"
|
|
)
|
|
(vvPair
|
|
variable "graphical_source_group"
|
|
value "UNKNOWN"
|
|
)
|
|
(vvPair
|
|
variable "graphical_source_host"
|
|
value "WE7860"
|
|
)
|
|
(vvPair
|
|
variable "graphical_source_time"
|
|
value "14:43:18"
|
|
)
|
|
(vvPair
|
|
variable "group"
|
|
value "UNKNOWN"
|
|
)
|
|
(vvPair
|
|
variable "host"
|
|
value "WE7860"
|
|
)
|
|
(vvPair
|
|
variable "language"
|
|
value "VHDL"
|
|
)
|
|
(vvPair
|
|
variable "library"
|
|
value "DigitalToAnalogConverter_test"
|
|
)
|
|
(vvPair
|
|
variable "library_downstream_ModelSimCompiler"
|
|
value "$SCRATCH_DIR/DigitalToAnalogConverter_test"
|
|
)
|
|
(vvPair
|
|
variable "mm"
|
|
value "04"
|
|
)
|
|
(vvPair
|
|
variable "module_name"
|
|
value "DAC_tester"
|
|
)
|
|
(vvPair
|
|
variable "month"
|
|
value "avr."
|
|
)
|
|
(vvPair
|
|
variable "month_long"
|
|
value "avril"
|
|
)
|
|
(vvPair
|
|
variable "p"
|
|
value "C:\\dev\\sem-labs\\03-DigitalToAnalogConverter\\Prefs\\..\\DigitalToAnalogConverter_test\\hds\\@d@a@c_tester\\interface"
|
|
)
|
|
(vvPair
|
|
variable "p_logical"
|
|
value "C:\\dev\\sem-labs\\03-DigitalToAnalogConverter\\Prefs\\..\\DigitalToAnalogConverter_test\\hds\\DAC_tester\\interface"
|
|
)
|
|
(vvPair
|
|
variable "package_name"
|
|
value "<Undefined Variable>"
|
|
)
|
|
(vvPair
|
|
variable "project_name"
|
|
value "hds"
|
|
)
|
|
(vvPair
|
|
variable "series"
|
|
value "HDL Designer Series"
|
|
)
|
|
(vvPair
|
|
variable "task_AsmPath"
|
|
value "$HEI_LIBS_DIR/NanoBlaze/hdl"
|
|
)
|
|
(vvPair
|
|
variable "task_HDSPath"
|
|
value "$HDS_HOME"
|
|
)
|
|
(vvPair
|
|
variable "task_ISEBinPath"
|
|
value "$ISE_HOME"
|
|
)
|
|
(vvPair
|
|
variable "task_ISEPath"
|
|
value "$ISE_WORK_DIR"
|
|
)
|
|
(vvPair
|
|
variable "task_ModelSimPath"
|
|
value "$MODELSIM_HOME/modeltech/bin"
|
|
)
|
|
(vvPair
|
|
variable "this_ext"
|
|
value "<TBD>"
|
|
)
|
|
(vvPair
|
|
variable "this_file"
|
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