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SEm-Labos/10-PipelinedOperators/PipelinedOperators/hdl/parallelAdder_studentVersion.vhd
github-classroom[bot] d212040c30
Initial commit
2024-02-23 13:01:05 +00:00

8 lines
130 B
VHDL

ARCHITECTURE studentVersion OF parallelAdder IS
BEGIN
sum <= (others => '0');
cOut <= '0';
END ARCHITECTURE studentVersion;