Klagarge/SEm-Labos
1
0
Fork 0
Code
main
SEm-Labos/Libs/Memory/hds
History
Klagarge 8a64f5c04b add encoding SM --not finish yet
2024-04-10 14:22:10 +02:00
..
.hdlsidedata Initial commit 2024-02-23 13:01:05 +00:00
.xrf add encoding SM --not finish yet 2024-04-10 14:22:10 +02:00
@f@i@f@o Initial commit 2024-02-23 13:01:05 +00:00
@f@i@f@o_bram Initial commit 2024-02-23 13:01:05 +00:00
@f@i@f@o_one@register Initial commit 2024-02-23 13:01:05 +00:00
bram Initial commit 2024-02-23 13:01:05 +00:00
bram@Bin@ASCII@Init Initial commit 2024-02-23 13:01:05 +00:00
bram@dualport Initial commit 2024-02-23 13:01:05 +00:00
bram@dualport@writefirst Initial commit 2024-02-23 13:01:05 +00:00
bram@Hex@ASCII@Init Initial commit 2024-02-23 13:01:05 +00:00
fifo@bridge Initial commit 2024-02-23 13:01:05 +00:00
fifo@bridge@bus@width@adaption Initial commit 2024-02-23 13:01:05 +00:00
fifo@bridge@rx@to@tx Initial commit 2024-02-23 13:01:05 +00:00
fifo@bridge@rx@to@tx@bus@width@adaption@rx@bigger Initial commit 2024-02-23 13:01:05 +00:00
fifo@bridge@rx@to@tx@bus@width@adaption@txbigger Initial commit 2024-02-23 13:01:05 +00:00
flash@controller Initial commit 2024-02-23 13:01:05 +00:00
sdram@controller Initial commit 2024-02-23 13:01:05 +00:00
sdram@controller@build@address Initial commit 2024-02-23 13:01:05 +00:00
sdram@controller@fsm Initial commit 2024-02-23 13:01:05 +00:00
sdram@controller@refresh@counter Initial commit 2024-02-23 13:01:05 +00:00
sdram@controller@s@r Initial commit 2024-02-23 13:01:05 +00:00
sdram@controller@sample@data@in Initial commit 2024-02-23 13:01:05 +00:00
sdram@controller@store@data Initial commit 2024-02-23 13:01:05 +00:00
sdram@controller@timings@shift@register Initial commit 2024-02-23 13:01:05 +00:00
_bram._epf Initial commit 2024-02-23 13:01:05 +00:00
_bramBinASCIIInit._epf Initial commit 2024-02-23 13:01:05 +00:00
_bramdualport._epf Initial commit 2024-02-23 13:01:05 +00:00
_bramdualportwritefirst._epf Initial commit 2024-02-23 13:01:05 +00:00
_bramHexASCIIInit._epf Initial commit 2024-02-23 13:01:05 +00:00
_fifo_bram._epf Initial commit 2024-02-23 13:01:05 +00:00
_fifo_oneregister._epf Initial commit 2024-02-23 13:01:05 +00:00
_fifo._epf Initial commit 2024-02-23 13:01:05 +00:00
_fifobridge._epf Initial commit 2024-02-23 13:01:05 +00:00
_fifobridgebuswidthadaption._epf Initial commit 2024-02-23 13:01:05 +00:00
_fifobridgerxtotx._epf Initial commit 2024-02-23 13:01:05 +00:00
_fifobridgerxtotxbuswidthadaptionrxbigger._epf Initial commit 2024-02-23 13:01:05 +00:00
_fifobridgerxtotxbuswidthadaptiontxbigger._epf Initial commit 2024-02-23 13:01:05 +00:00
_flashcontroller._epf Initial commit 2024-02-23 13:01:05 +00:00
_sdramcontroller._epf Initial commit 2024-02-23 13:01:05 +00:00
_sdramcontrollerbuildaddress._epf Initial commit 2024-02-23 13:01:05 +00:00
_sdramcontrollerfsm._epf Initial commit 2024-02-23 13:01:05 +00:00
_sdramcontrollerrefreshcounter._epf Initial commit 2024-02-23 13:01:05 +00:00
_sdramcontrollersampledatain._epf Initial commit 2024-02-23 13:01:05 +00:00
_sdramcontrollersr._epf Initial commit 2024-02-23 13:01:05 +00:00
_sdramcontrollerstoredata._epf Initial commit 2024-02-23 13:01:05 +00:00
_sdramcontrollertimingsshiftregister._epf Initial commit 2024-02-23 13:01:05 +00:00
.cache.dat add encoding SM --not finish yet 2024-04-10 14:22:10 +02:00