143 lines
3.7 KiB
Plaintext
143 lines
3.7 KiB
Plaintext
--
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-- VHDL Architecture Board.lissajousGenerator_circuit_EBS3.masterVersion
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--
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-- Created:
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-- by - axel.amand.UNKNOWN (WE7860)
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-- at - 17:45:49 01.05.2023
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--
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-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5)
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--
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LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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USE ieee.numeric_std.all;
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LIBRARY Board;
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LIBRARY Lattice;
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LIBRARY Lissajous;
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ARCHITECTURE masterVersion OF lissajousGenerator_circuit_EBS3 IS
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-- Architecture declarations
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constant signalBitNb: positive := 16;
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constant phaseBitNb: positive := 17;
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constant stepX: positive := 3;
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constant stepY: positive := 4;
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-- Internal signal declarations
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SIGNAL clkSys : std_ulogic;
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SIGNAL logic0 : std_ulogic;
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SIGNAL logic1 : std_uLogic;
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SIGNAL reset : std_ulogic;
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SIGNAL resetSynch : std_ulogic;
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SIGNAL resetSynch_N : std_ulogic;
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-- Component Declarations
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COMPONENT DFF
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PORT (
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CLK : IN std_uLogic ;
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CLR : IN std_uLogic ;
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D : IN std_uLogic ;
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Q : OUT std_uLogic
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);
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END COMPONENT;
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COMPONENT inverterIn
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PORT (
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in1 : IN std_uLogic ;
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out1 : OUT std_uLogic
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);
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END COMPONENT;
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COMPONENT pll
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PORT (
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clkIn100M : IN std_ulogic;
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en10M : IN std_ulogic;
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en50M : IN std_ulogic;
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en75M : IN std_ulogic;
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clk10MHz : OUT std_ulogic;
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clk50MHz : OUT std_ulogic;
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clk60MHz : OUT std_ulogic;
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clk75MHz : OUT std_ulogic;
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pllLocked : OUT std_ulogic
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);
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END COMPONENT;
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COMPONENT lissajousGenerator
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GENERIC (
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signalBitNb : positive := 16;
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phaseBitNb : positive := 16;
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stepX : positive := 1;
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stepY : positive := 1
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);
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PORT (
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clock : IN std_ulogic ;
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reset : IN std_ulogic ;
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triggerOut : OUT std_ulogic ;
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xOut : OUT std_ulogic ;
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yOut : OUT std_ulogic
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);
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END COMPONENT;
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-- Optional embedded configurations
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-- pragma synthesis_off
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FOR ALL : DFF USE ENTITY Board.DFF;
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FOR ALL : inverterIn USE ENTITY Board.inverterIn;
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FOR ALL : lissajousGenerator USE ENTITY Lissajous.lissajousGenerator;
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FOR ALL : pll USE ENTITY Lattice.pll;
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-- pragma synthesis_on
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BEGIN
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-- Architecture concurrent statements
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-- HDL Embedded Text Block 5 eb5
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logic1 <= '1';
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-- HDL Embedded Text Block 6 eb6
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logic0 <= '0';
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-- Instance port mappings.
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I_dff : DFF
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PORT MAP (
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CLK => clock,
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CLR => reset,
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D => logic1,
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Q => resetSynch_N
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);
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I_inv1 : inverterIn
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PORT MAP (
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in1 => reset_N,
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out1 => reset
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);
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I_inv2 : inverterIn
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PORT MAP (
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in1 => resetSynch_N,
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out1 => resetSynch
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);
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U_pll : pll
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PORT MAP (
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clkIn100M => clock,
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en75M => logic0,
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en50M => logic0,
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en10M => logic0,
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clk60MHz => clkSys,
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clk75MHz => OPEN,
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clk50MHz => OPEN,
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clk10MHz => OPEN,
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pllLocked => OPEN
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);
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I_main : lissajousGenerator
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GENERIC MAP (
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signalBitNb => signalBitNb,
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phaseBitNb => phaseBitNb,
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stepX => stepX,
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stepY => stepY
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)
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PORT MAP (
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clock => clkSys,
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reset => resetSynch,
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triggerOut => triggerOut,
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xOut => xOut,
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yOut => yOut
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);
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END masterVersion;
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