15 lines
298 B
VHDL
15 lines
298 B
VHDL
ARCHITECTURE RTL OF ahbMuxConnector IS
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BEGIN
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hSel <= hSelV(index);
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hRDataV(index) <= std_logic_vector(hRData);
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hReadyV(index) <= hReady;
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hRespV(index) <= hResp;
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hRDataV <= (others => (others => 'Z'));
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hReadyV <= (others => 'Z');
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hRespV <= (others => 'Z');
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END ARCHITECTURE RTL;
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