63 lines
1.4 KiB
VHDL
63 lines
1.4 KiB
VHDL
--==============================================================================
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--
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-- AHB general purpose input/outputs
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--
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-- Provides "ioNb" input/output signals .
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--
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--------------------------------------------------------------------------------
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--
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-- Write registers
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--
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-- 00, data register receives the values to drive the output lines.
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-- 01, output enable register defines the signal direction:
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-- when '1', the direction is "out".
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--
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--------------------------------------------------------------------------------
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--
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-- Read registers
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-- 00, data register provides the values detected on the lines.
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--
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signal addresses is unsigned(32 downto 0);
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signal bRead is std_ulogic;
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signal bWrite is std_ulogic;
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ARCHITECTURE studentVersion OF ahbGpio IS
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BEGIN
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process(hReset_n, hClk) begin
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if hReset_n = '1' then
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-- AHB-Lite
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hRData <= (OTHERS => '0');
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hReady <= '0';
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hResp <= '0';
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-- Out
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ioOut <= (OTHERS => '0');
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ioEn <= (OTHERS => '0');
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addresses <= (OTHERS => '0');
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bRead <= '0';
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bWrite <= '1';
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elsif rising_edge(hClk) then
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if hSel = '1' then
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CASE hAddr is
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WHEN 00 =>
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WHEN 01 =>
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WHEN OTHERS
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end CASE;
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end if;
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end if;
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end process;
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-- AHB-Lite
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-- hRData <= (OTHERS => '0');
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-- hReady <= '0';
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-- hResp <= '0';
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-- Out
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-- ioOut <= (OTHERS => '0');
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-- ioEn <= (OTHERS => '0');
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END ARCHITECTURE studentVersion;
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