1347 lines
17 KiB
Plaintext
1347 lines
17 KiB
Plaintext
DocumentHdrVersion "1.1"
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Header (DocumentHdr
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version 2
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dmPackageRefs [
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(DmPackageRef
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library "ieee"
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unitName "std_logic_1164"
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)
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(DmPackageRef
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library "ieee"
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unitName "numeric_std"
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itemName "ALL"
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)
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]
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libraryRefs [
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"ieee"
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]
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)
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version "27.1"
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appVersion "2019.2 (Build 5)"
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model (Symbol
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commonDM (CommonDM
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ldm (LogicalDM
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suid 25,0
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usingSuid 1
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emptyRow *1 (LEmptyRow
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)
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uid 56,0
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optionalChildren [
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*2 (RefLabelRowHdr
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*3 (TitleRowHdr
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)
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*4 (FilterRowHdr
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)
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*5 (RefLabelColHdr
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tm "RefLabelColHdrMgr"
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)
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*6 (RowExpandColHdr
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tm "RowExpandColHdrMgr"
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)
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*7 (GroupColHdr
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tm "GroupColHdrMgr"
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)
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*8 (NameColHdr
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tm "NameColHdrMgr"
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)
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*9 (ModeColHdr
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tm "ModeColHdrMgr"
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)
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*10 (TypeColHdr
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tm "TypeColHdrMgr"
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)
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*11 (BoundsColHdr
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tm "BoundsColHdrMgr"
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)
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*12 (InitColHdr
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tm "InitColHdrMgr"
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)
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*13 (EolColHdr
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tm "EolColHdrMgr"
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)
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*14 (LogPort
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port (LogicalPort
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m 1
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decl (Decl
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n "a"
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t "signed"
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b "(adderBitNb-1 DOWNTO 0)"
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o 1
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suid 21,0
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)
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)
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uid 383,0
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)
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*15 (LogPort
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port (LogicalPort
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m 1
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|
decl (Decl
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n "b"
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t "signed"
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b "(adderBitNb-1 DOWNTO 0)"
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o 2
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suid 22,0
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)
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)
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|
uid 385,0
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)
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*16 (LogPort
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port (LogicalPort
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m 1
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decl (Decl
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n "cIn"
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t "std_ulogic"
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o 3
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suid 23,0
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)
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)
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uid 387,0
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)
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*17 (LogPort
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port (LogicalPort
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decl (Decl
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n "cOut"
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t "std_ulogic"
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o 4
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suid 24,0
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)
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)
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uid 389,0
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)
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*18 (LogPort
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port (LogicalPort
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decl (Decl
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n "sum"
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t "signed"
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b "(adderBitNb-1 DOWNTO 0)"
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o 5
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suid 25,0
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)
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)
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uid 391,0
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)
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]
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)
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pdm (PhysicalDM
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displayShortBounds 1
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editShortBounds 1
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uid 69,0
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optionalChildren [
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*19 (Sheet
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sheetRow (SheetRow
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headerVa (MVa
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cellColor "49152,49152,49152"
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fontColor "0,0,0"
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font "Tahoma,10,0"
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)
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cellVa (MVa
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cellColor "65535,65535,65535"
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fontColor "0,0,0"
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font "Tahoma,10,0"
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)
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groupVa (MVa
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cellColor "39936,56832,65280"
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fontColor "0,0,0"
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font "Tahoma,10,0"
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)
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emptyMRCItem *20 (MRCItem
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litem &1
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pos 5
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dimension 20
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)
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uid 71,0
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optionalChildren [
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*21 (MRCItem
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litem &2
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pos 0
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dimension 20
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uid 72,0
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)
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*22 (MRCItem
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litem &3
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pos 1
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dimension 23
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uid 73,0
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)
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*23 (MRCItem
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litem &4
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pos 2
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hidden 1
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dimension 20
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uid 74,0
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)
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*24 (MRCItem
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litem &14
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pos 0
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dimension 20
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uid 384,0
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)
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*25 (MRCItem
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litem &15
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pos 1
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dimension 20
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uid 386,0
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)
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*26 (MRCItem
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litem &16
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pos 2
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dimension 20
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uid 388,0
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)
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*27 (MRCItem
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litem &17
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pos 3
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dimension 20
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uid 390,0
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)
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*28 (MRCItem
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litem &18
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pos 4
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dimension 20
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uid 392,0
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)
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]
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)
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sheetCol (SheetCol
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propVa (MVa
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cellColor "0,49152,49152"
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fontColor "0,0,0"
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font "Tahoma,10,0"
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textAngle 90
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)
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uid 75,0
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optionalChildren [
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*29 (MRCItem
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litem &5
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pos 0
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dimension 20
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uid 76,0
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)
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*30 (MRCItem
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litem &7
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pos 1
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dimension 50
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uid 77,0
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)
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*31 (MRCItem
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litem &8
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pos 2
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dimension 100
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uid 78,0
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)
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*32 (MRCItem
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litem &9
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pos 3
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dimension 50
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uid 79,0
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)
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*33 (MRCItem
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litem &10
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pos 4
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dimension 100
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uid 80,0
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)
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*34 (MRCItem
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litem &11
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pos 5
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dimension 100
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uid 81,0
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)
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*35 (MRCItem
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litem &12
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pos 6
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dimension 50
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uid 82,0
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)
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*36 (MRCItem
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litem &13
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pos 7
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dimension 80
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uid 83,0
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)
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]
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)
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fixedCol 4
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fixedRow 2
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name "Ports"
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uid 70,0
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vaOverrides [
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]
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)
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]
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)
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uid 55,0
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)
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genericsCommonDM (CommonDM
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ldm (LogicalDM
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emptyRow *37 (LEmptyRow
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)
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uid 85,0
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optionalChildren [
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*38 (RefLabelRowHdr
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)
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*39 (TitleRowHdr
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)
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*40 (FilterRowHdr
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)
|
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*41 (RefLabelColHdr
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tm "RefLabelColHdrMgr"
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)
|
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*42 (RowExpandColHdr
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tm "RowExpandColHdrMgr"
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)
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*43 (GroupColHdr
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tm "GroupColHdrMgr"
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)
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*44 (NameColHdr
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tm "GenericNameColHdrMgr"
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)
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*45 (TypeColHdr
|
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tm "GenericTypeColHdrMgr"
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)
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*46 (InitColHdr
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tm "GenericValueColHdrMgr"
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)
|
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*47 (PragmaColHdr
|
|
tm "GenericPragmaColHdrMgr"
|
|
)
|
|
*48 (EolColHdr
|
|
tm "GenericEolColHdrMgr"
|
|
)
|
|
*49 (LogGeneric
|
|
generic (GiElement
|
|
name "adderBitNb"
|
|
type "positive"
|
|
value "32"
|
|
)
|
|
uid 134,0
|
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)
|
|
*50 (LogGeneric
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generic (GiElement
|
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name "clockFrequency"
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type "real"
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value "60.0E6"
|
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)
|
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uid 333,0
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)
|
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]
|
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)
|
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pdm (PhysicalDM
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displayShortBounds 1
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editShortBounds 1
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uid 97,0
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optionalChildren [
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*51 (Sheet
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sheetRow (SheetRow
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headerVa (MVa
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cellColor "49152,49152,49152"
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fontColor "0,0,0"
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font "Tahoma,10,0"
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)
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cellVa (MVa
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cellColor "65535,65535,65535"
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fontColor "0,0,0"
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font "Tahoma,10,0"
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)
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groupVa (MVa
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cellColor "39936,56832,65280"
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fontColor "0,0,0"
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font "Tahoma,10,0"
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)
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emptyMRCItem *52 (MRCItem
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litem &37
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pos 2
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dimension 20
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)
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uid 99,0
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optionalChildren [
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*53 (MRCItem
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litem &38
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pos 0
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dimension 20
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uid 100,0
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)
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*54 (MRCItem
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litem &39
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pos 1
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dimension 23
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uid 101,0
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)
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*55 (MRCItem
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litem &40
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pos 2
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hidden 1
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dimension 20
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uid 102,0
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)
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*56 (MRCItem
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litem &49
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pos 0
|
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dimension 20
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uid 135,0
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)
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*57 (MRCItem
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litem &50
|
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pos 1
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dimension 20
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uid 334,0
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)
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]
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)
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sheetCol (SheetCol
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propVa (MVa
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cellColor "0,49152,49152"
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fontColor "0,0,0"
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font "Tahoma,10,0"
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textAngle 90
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)
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uid 103,0
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optionalChildren [
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*58 (MRCItem
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litem &41
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pos 0
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dimension 20
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uid 104,0
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)
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*59 (MRCItem
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litem &43
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pos 1
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dimension 50
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|
uid 105,0
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)
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*60 (MRCItem
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litem &44
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pos 2
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dimension 100
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|
uid 106,0
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)
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*61 (MRCItem
|
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litem &45
|
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pos 3
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dimension 100
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|
uid 107,0
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)
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*62 (MRCItem
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litem &46
|
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pos 4
|
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dimension 50
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|
uid 108,0
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)
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*63 (MRCItem
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litem &47
|
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pos 5
|
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dimension 50
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|
uid 109,0
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)
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*64 (MRCItem
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litem &48
|
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pos 6
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dimension 80
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uid 110,0
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)
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]
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)
|
|
fixedCol 3
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fixedRow 2
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name "Ports"
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uid 98,0
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vaOverrides [
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]
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)
|
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]
|
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)
|
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uid 84,0
|
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type 1
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)
|
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VExpander (VariableExpander
|
|
vvMap [
|
|
(vvPair
|
|
variable " "
|
|
value " "
|
|
)
|
|
(vvPair
|
|
variable "HDLDir"
|
|
value "C:\\dev\\sem-labs\\10-PipelinedOperators\\Prefs\\..\\PipelinedOperators_test\\hdl"
|
|
)
|
|
(vvPair
|
|
variable "HDSDir"
|
|
value "C:\\dev\\sem-labs\\10-PipelinedOperators\\Prefs\\..\\PipelinedOperators_test\\hds"
|
|
)
|
|
(vvPair
|
|
variable "SideDataDesignDir"
|
|
value "C:\\dev\\sem-labs\\10-PipelinedOperators\\Prefs\\..\\PipelinedOperators_test\\hds\\parallel@adder_tester\\interface.info"
|
|
)
|
|
(vvPair
|
|
variable "SideDataUserDir"
|
|
value "C:\\dev\\sem-labs\\10-PipelinedOperators\\Prefs\\..\\PipelinedOperators_test\\hds\\parallel@adder_tester\\interface.user"
|
|
)
|
|
(vvPair
|
|
variable "SourceDir"
|
|
value "C:\\dev\\sem-labs\\10-PipelinedOperators\\Prefs\\..\\PipelinedOperators_test\\hds"
|
|
)
|
|
(vvPair
|
|
variable "appl"
|
|
value "HDL Designer"
|
|
)
|
|
(vvPair
|
|
variable "arch_name"
|
|
value "interface"
|
|
)
|
|
(vvPair
|
|
variable "asm_file"
|
|
value "beamer.asm"
|
|
)
|
|
(vvPair
|
|
variable "concat_file"
|
|
value "concatenated"
|
|
)
|
|
(vvPair
|
|
variable "config"
|
|
value "%(unit)_%(view)_config"
|
|
)
|
|
(vvPair
|
|
variable "d"
|
|
value "C:\\dev\\sem-labs\\10-PipelinedOperators\\Prefs\\..\\PipelinedOperators_test\\hds\\parallel@adder_tester"
|
|
)
|
|
(vvPair
|
|
variable "d_logical"
|
|
value "C:\\dev\\sem-labs\\10-PipelinedOperators\\Prefs\\..\\PipelinedOperators_test\\hds\\parallelAdder_tester"
|
|
)
|
|
(vvPair
|
|
variable "date"
|
|
value "28.04.2023"
|
|
)
|
|
(vvPair
|
|
variable "day"
|
|
value "ven."
|
|
)
|
|
(vvPair
|
|
variable "day_long"
|
|
value "vendredi"
|
|
)
|
|
(vvPair
|
|
variable "dd"
|
|
value "28"
|
|
)
|
|
(vvPair
|
|
variable "designName"
|
|
value "$DESIGN_NAME"
|
|
)
|
|
(vvPair
|
|
variable "entity_name"
|
|
value "parallelAdder_tester"
|
|
)
|
|
(vvPair
|
|
variable "ext"
|
|
value "<TBD>"
|
|
)
|
|
(vvPair
|
|
variable "f"
|
|
value "interface"
|
|
)
|
|
(vvPair
|
|
variable "f_logical"
|
|
value "interface"
|
|
)
|
|
(vvPair
|
|
variable "f_noext"
|
|
value "interface"
|
|
)
|
|
(vvPair
|
|
variable "graphical_source_author"
|
|
value "axel.amand"
|
|
)
|
|
(vvPair
|
|
variable "graphical_source_date"
|
|
value "28.04.2023"
|
|
)
|
|
(vvPair
|
|
variable "graphical_source_group"
|
|
value "UNKNOWN"
|
|
)
|
|
(vvPair
|
|
variable "graphical_source_host"
|
|
value "WE7860"
|
|
)
|
|
(vvPair
|
|
variable "graphical_source_time"
|
|
value "15:19:47"
|
|
)
|
|
(vvPair
|
|
variable "group"
|
|
value "UNKNOWN"
|
|
)
|
|
(vvPair
|
|
variable "host"
|
|
value "WE7860"
|
|
)
|
|
(vvPair
|
|
variable "language"
|
|
value "VHDL"
|
|
)
|
|
(vvPair
|
|
variable "library"
|
|
value "pipelinedOperators_test"
|
|
)
|
|
(vvPair
|
|
variable "library_downstream_ModelSimCompiler"
|
|
value "$SCRATCH_DIR/PipelinedOperators_test"
|
|
)
|
|
(vvPair
|
|
variable "mm"
|
|
value "04"
|
|
)
|
|
(vvPair
|
|
variable "module_name"
|
|
value "parallelAdder_tester"
|
|
)
|
|
(vvPair
|
|
variable "month"
|
|
value "avr."
|
|
)
|
|
(vvPair
|
|
variable "month_long"
|
|
value "avril"
|
|
)
|
|
(vvPair
|
|
variable "p"
|
|
value "C:\\dev\\sem-labs\\10-PipelinedOperators\\Prefs\\..\\PipelinedOperators_test\\hds\\parallel@adder_tester\\interface"
|
|
)
|
|
(vvPair
|
|
variable "p_logical"
|
|
value "C:\\dev\\sem-labs\\10-PipelinedOperators\\Prefs\\..\\PipelinedOperators_test\\hds\\parallelAdder_tester\\interface"
|
|
)
|
|
(vvPair
|
|
variable "package_name"
|
|
value "<Undefined Variable>"
|
|
)
|
|
(vvPair
|
|
variable "project_name"
|
|
value "hds"
|
|
)
|
|
(vvPair
|
|
variable "series"
|
|
value "HDL Designer Series"
|
|
)
|
|
(vvPair
|
|
variable "task_ADMS"
|
|
value "<TBD>"
|
|
)
|
|
(vvPair
|
|
variable "task_AsmPath"
|
|
value "$HEI_LIBS_DIR/NanoBlaze/hdl"
|
|
)
|
|
(vvPair
|
|
variable "task_DesignCompilerPath"
|
|
value "<TBD>"
|
|
)
|
|
(vvPair
|
|
variable "task_HDSPath"
|
|
value "$HDS_HOME"
|
|
)
|
|
(vvPair
|
|
variable "task_ISEBinPath"
|
|
value "$ISE_HOME"
|
|
)
|
|
(vvPair
|
|
variable "task_ISEPath"
|
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value "$ISE_WORK_DIR"
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)
|
|
)
|
|
)
|
|
DeclarativeBlock *76 (SymDeclBlock
|
|
uid 1,0
|
|
stg "SymDeclLayoutStrategy"
|
|
declLabel (Text
|
|
uid 2,0
|
|
va (VaSet
|
|
font "Verdana,8,1"
|
|
)
|
|
xt "42000,0,48500,900"
|
|
st "Declarations"
|
|
blo "42000,700"
|
|
)
|
|
portLabel (Text
|
|
uid 3,0
|
|
va (VaSet
|
|
font "Verdana,8,1"
|
|
)
|
|
xt "42000,900,45000,1800"
|
|
st "Ports:"
|
|
blo "42000,1600"
|
|
)
|
|
externalLabel (Text
|
|
uid 4,0
|
|
va (VaSet
|
|
font "Verdana,8,1"
|
|
)
|
|
xt "42000,5800,44500,6700"
|
|
st "User:"
|
|
blo "42000,6500"
|
|
)
|
|
internalLabel (Text
|
|
uid 6,0
|
|
va (VaSet
|
|
isHidden 1
|
|
font "Verdana,8,1"
|
|
)
|
|
xt "42000,0,49500,900"
|
|
st "Internal User:"
|
|
blo "42000,700"
|
|
)
|
|
externalText (MLText
|
|
uid 5,0
|
|
va (VaSet
|
|
font "Verdana,8,0"
|
|
)
|
|
xt "44000,6700,44000,6700"
|
|
tm "SyDeclarativeTextMgr"
|
|
)
|
|
internalText (MLText
|
|
uid 7,0
|
|
va (VaSet
|
|
isHidden 1
|
|
font "Verdana,8,0"
|
|
)
|
|
xt "42000,0,42000,0"
|
|
tm "SyDeclarativeTextMgr"
|
|
)
|
|
)
|
|
lastUid 392,0
|
|
activeModelName "Symbol:GEN"
|
|
)
|