1498 lines
19 KiB
Plaintext
1498 lines
19 KiB
Plaintext
DocumentHdrVersion "1.1"
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Header (DocumentHdr
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version 2
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dmPackageRefs [
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(DmPackageRef
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library "ieee"
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unitName "std_logic_1164"
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)
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(DmPackageRef
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library "ieee"
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unitName "numeric_std"
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itemName "ALL"
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)
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]
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libraryRefs [
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"ieee"
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]
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)
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version "27.1"
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appVersion "2019.2 (Build 5)"
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model (Symbol
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commonDM (CommonDM
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ldm (LogicalDM
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suid 55,0
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usingSuid 1
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emptyRow *1 (LEmptyRow
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uid 21,0
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optionalChildren [
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*3 (TitleRowHdr
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*4 (FilterRowHdr
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tm "RefLabelColHdrMgr"
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)
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tm "RowExpandColHdrMgr"
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)
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*7 (GroupColHdr
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tm "GroupColHdrMgr"
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)
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tm "NameColHdrMgr"
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)
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tm "ModeColHdrMgr"
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)
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tm "TypeColHdrMgr"
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tm "BoundsColHdrMgr"
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)
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tm "InitColHdrMgr"
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)
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*13 (EolColHdr
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tm "EolColHdrMgr"
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)
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port (LogicalPort
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m 1
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decl (Decl
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n "a"
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t "signed"
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b "(adderBitNb-1 DOWNTO 0)"
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o 1
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suid 49,0
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)
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)
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uid 706,0
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*15 (LogPort
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port (LogicalPort
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m 1
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decl (Decl
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n "b"
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t "signed"
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b "(adderBitNb-1 DOWNTO 0)"
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o 2
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suid 50,0
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)
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)
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uid 708,0
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)
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*16 (LogPort
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port (LogicalPort
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m 1
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decl (Decl
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n "cIn"
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t "std_ulogic"
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o 3
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suid 51,0
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)
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)
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uid 710,0
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)
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*17 (LogPort
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port (LogicalPort
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m 1
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decl (Decl
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n "clock"
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t "std_ulogic"
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o 5
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suid 52,0
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)
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)
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uid 712,0
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)
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*18 (LogPort
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port (LogicalPort
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decl (Decl
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n "cOut"
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t "std_ulogic"
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o 4
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suid 53,0
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)
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)
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uid 714,0
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)
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*19 (LogPort
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port (LogicalPort
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m 1
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decl (Decl
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n "reset"
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t "std_ulogic"
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o 6
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suid 54,0
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)
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)
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uid 716,0
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)
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*20 (LogPort
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port (LogicalPort
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decl (Decl
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n "sum"
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t "signed"
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b "(adderBitNb-1 DOWNTO 0)"
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o 7
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suid 55,0
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)
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)
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uid 718,0
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)
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pdm (PhysicalDM
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displayShortBounds 1
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editShortBounds 1
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uid 34,0
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optionalChildren [
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sheetRow (SheetRow
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headerVa (MVa
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cellColor "49152,49152,49152"
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fontColor "0,0,0"
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font "Tahoma,10,0"
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cellVa (MVa
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cellColor "65535,65535,65535"
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fontColor "0,0,0"
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font "Tahoma,10,0"
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groupVa (MVa
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cellColor "39936,56832,65280"
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emptyMRCItem *22 (MRCItem
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litem &1
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pos 7
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dimension 20
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uid 36,0
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optionalChildren [
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*23 (MRCItem
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litem &2
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pos 0
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dimension 20
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uid 37,0
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*24 (MRCItem
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litem &3
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pos 1
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dimension 23
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uid 38,0
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*25 (MRCItem
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litem &4
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pos 2
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hidden 1
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dimension 20
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uid 39,0
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*26 (MRCItem
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litem &14
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dimension 20
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uid 707,0
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*27 (MRCItem
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litem &15
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pos 1
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dimension 20
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uid 709,0
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)
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*28 (MRCItem
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litem &16
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pos 2
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dimension 20
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uid 711,0
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*29 (MRCItem
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litem &17
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pos 3
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dimension 20
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uid 713,0
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)
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*30 (MRCItem
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litem &18
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pos 4
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dimension 20
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uid 715,0
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)
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*31 (MRCItem
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litem &19
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pos 5
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dimension 20
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uid 717,0
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)
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*32 (MRCItem
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litem &20
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pos 6
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dimension 20
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uid 719,0
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)
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]
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)
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sheetCol (SheetCol
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propVa (MVa
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cellColor "0,49152,49152"
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fontColor "0,0,0"
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font "Tahoma,10,0"
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textAngle 90
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)
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uid 40,0
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optionalChildren [
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*33 (MRCItem
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litem &5
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pos 0
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dimension 20
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uid 41,0
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*34 (MRCItem
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litem &7
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pos 1
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dimension 50
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uid 42,0
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*35 (MRCItem
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litem &8
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pos 2
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dimension 100
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uid 43,0
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*36 (MRCItem
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litem &9
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pos 3
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dimension 50
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uid 44,0
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*37 (MRCItem
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litem &10
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pos 4
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dimension 100
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uid 45,0
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)
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*38 (MRCItem
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litem &11
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pos 5
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dimension 100
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uid 46,0
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)
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*39 (MRCItem
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litem &12
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pos 6
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dimension 50
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uid 47,0
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)
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*40 (MRCItem
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litem &13
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pos 7
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dimension 80
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uid 48,0
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]
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)
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fixedCol 4
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fixedRow 2
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name "Ports"
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uid 35,0
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vaOverrides [
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]
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)
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]
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)
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uid 20,0
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)
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genericsCommonDM (CommonDM
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ldm (LogicalDM
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emptyRow *41 (LEmptyRow
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)
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uid 50,0
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optionalChildren [
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*42 (RefLabelRowHdr
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)
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*43 (TitleRowHdr
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)
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*44 (FilterRowHdr
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)
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*45 (RefLabelColHdr
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tm "RefLabelColHdrMgr"
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)
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*46 (RowExpandColHdr
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tm "RowExpandColHdrMgr"
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)
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*47 (GroupColHdr
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tm "GroupColHdrMgr"
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)
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*48 (NameColHdr
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tm "GenericNameColHdrMgr"
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)
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*49 (TypeColHdr
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tm "GenericTypeColHdrMgr"
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*50 (InitColHdr
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tm "GenericValueColHdrMgr"
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)
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*51 (PragmaColHdr
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tm "GenericPragmaColHdrMgr"
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)
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*52 (EolColHdr
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tm "GenericEolColHdrMgr"
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)
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*53 (LogGeneric
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generic (GiElement
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name "adderBitNb"
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type "positive"
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value "32"
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)
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uid 99,0
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)
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*54 (LogGeneric
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generic (GiElement
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name "stageNb"
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type "positive"
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value "4"
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)
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uid 405,0
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)
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*55 (LogGeneric
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generic (GiElement
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name "clockFrequency"
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type "real"
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value "60.0E6"
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)
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uid 646,0
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)
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]
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)
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pdm (PhysicalDM
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displayShortBounds 1
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editShortBounds 1
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uid 62,0
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optionalChildren [
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*56 (Sheet
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sheetRow (SheetRow
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headerVa (MVa
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cellColor "49152,49152,49152"
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fontColor "0,0,0"
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font "Tahoma,10,0"
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)
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cellVa (MVa
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cellColor "65535,65535,65535"
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fontColor "0,0,0"
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font "Tahoma,10,0"
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)
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groupVa (MVa
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cellColor "39936,56832,65280"
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fontColor "0,0,0"
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font "Tahoma,10,0"
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emptyMRCItem *57 (MRCItem
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litem &41
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pos 3
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dimension 20
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)
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uid 64,0
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optionalChildren [
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*58 (MRCItem
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litem &42
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pos 0
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dimension 20
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uid 65,0
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*59 (MRCItem
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litem &43
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pos 1
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dimension 23
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uid 66,0
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)
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*60 (MRCItem
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litem &44
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pos 2
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hidden 1
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dimension 20
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uid 67,0
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)
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*61 (MRCItem
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litem &53
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pos 0
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dimension 20
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uid 100,0
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)
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*62 (MRCItem
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litem &54
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pos 1
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dimension 20
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uid 406,0
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)
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*63 (MRCItem
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litem &55
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pos 2
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dimension 20
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uid 647,0
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]
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)
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sheetCol (SheetCol
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propVa (MVa
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cellColor "0,49152,49152"
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fontColor "0,0,0"
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font "Tahoma,10,0"
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textAngle 90
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uid 68,0
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optionalChildren [
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*64 (MRCItem
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litem &45
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pos 0
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dimension 20
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uid 69,0
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)
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*65 (MRCItem
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litem &47
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pos 1
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dimension 50
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uid 70,0
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)
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*66 (MRCItem
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litem &48
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pos 2
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dimension 100
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uid 71,0
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)
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*67 (MRCItem
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litem &49
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pos 3
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dimension 100
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uid 72,0
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)
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*68 (MRCItem
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litem &50
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pos 4
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dimension 50
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uid 73,0
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)
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*69 (MRCItem
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litem &51
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pos 5
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dimension 50
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uid 74,0
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)
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*70 (MRCItem
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litem &52
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pos 6
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dimension 80
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uid 75,0
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)
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]
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)
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fixedCol 3
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fixedRow 2
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name "Ports"
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uid 63,0
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vaOverrides [
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]
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)
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]
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)
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uid 49,0
|
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type 1
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)
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VExpander (VariableExpander
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vvMap [
|
|
(vvPair
|
|
variable " "
|
|
value " "
|
|
)
|
|
(vvPair
|
|
variable "HDLDir"
|
|
value "C:\\dev\\sem-labs\\10-PipelinedOperators\\Prefs\\..\\PipelinedOperators_test\\hdl"
|
|
)
|
|
(vvPair
|
|
variable "HDSDir"
|
|
value "C:\\dev\\sem-labs\\10-PipelinedOperators\\Prefs\\..\\PipelinedOperators_test\\hds"
|
|
)
|
|
(vvPair
|
|
variable "SideDataDesignDir"
|
|
value "C:\\dev\\sem-labs\\10-PipelinedOperators\\Prefs\\..\\PipelinedOperators_test\\hds\\pipeline@adder_tester\\interface.info"
|
|
)
|
|
(vvPair
|
|
variable "SideDataUserDir"
|
|
value "C:\\dev\\sem-labs\\10-PipelinedOperators\\Prefs\\..\\PipelinedOperators_test\\hds\\pipeline@adder_tester\\interface.user"
|
|
)
|
|
(vvPair
|
|
variable "SourceDir"
|
|
value "C:\\dev\\sem-labs\\10-PipelinedOperators\\Prefs\\..\\PipelinedOperators_test\\hds"
|
|
)
|
|
(vvPair
|
|
variable "appl"
|
|
value "HDL Designer"
|
|
)
|
|
(vvPair
|
|
variable "arch_name"
|
|
value "interface"
|
|
)
|
|
(vvPair
|
|
variable "asm_file"
|
|
value "beamer.asm"
|
|
)
|
|
(vvPair
|
|
variable "concat_file"
|
|
value "concatenated"
|
|
)
|
|
(vvPair
|
|
variable "config"
|
|
value "%(unit)_%(view)_config"
|
|
)
|
|
(vvPair
|
|
variable "d"
|
|
value "C:\\dev\\sem-labs\\10-PipelinedOperators\\Prefs\\..\\PipelinedOperators_test\\hds\\pipeline@adder_tester"
|
|
)
|
|
(vvPair
|
|
variable "d_logical"
|
|
value "C:\\dev\\sem-labs\\10-PipelinedOperators\\Prefs\\..\\PipelinedOperators_test\\hds\\pipelineAdder_tester"
|
|
)
|
|
(vvPair
|
|
variable "date"
|
|
value "28.04.2023"
|
|
)
|
|
(vvPair
|
|
variable "day"
|
|
value "ven."
|
|
)
|
|
(vvPair
|
|
variable "day_long"
|
|
value "vendredi"
|
|
)
|
|
(vvPair
|
|
variable "dd"
|
|
value "28"
|
|
)
|
|
(vvPair
|
|
variable "designName"
|
|
value "$DESIGN_NAME"
|
|
)
|
|
(vvPair
|
|
variable "entity_name"
|
|
value "pipelineAdder_tester"
|
|
)
|
|
(vvPair
|
|
variable "ext"
|
|
value "<TBD>"
|
|
)
|
|
(vvPair
|
|
variable "f"
|
|
value "interface"
|
|
)
|
|
(vvPair
|
|
variable "f_logical"
|
|
value "interface"
|
|
)
|
|
(vvPair
|
|
variable "f_noext"
|
|
value "interface"
|
|
)
|
|
(vvPair
|
|
variable "graphical_source_author"
|
|
value "axel.amand"
|
|
)
|
|
(vvPair
|
|
variable "graphical_source_date"
|
|
value "28.04.2023"
|
|
)
|
|
(vvPair
|
|
variable "graphical_source_group"
|
|
value "UNKNOWN"
|
|
)
|
|
(vvPair
|
|
variable "graphical_source_host"
|
|
value "WE7860"
|
|
)
|
|
(vvPair
|
|
variable "graphical_source_time"
|
|
value "15:20:22"
|
|
)
|
|
(vvPair
|
|
variable "group"
|
|
value "UNKNOWN"
|
|
)
|
|
(vvPair
|
|
variable "host"
|
|
value "WE7860"
|
|
)
|
|
(vvPair
|
|
variable "language"
|
|
value "VHDL"
|
|
)
|
|
(vvPair
|
|
variable "library"
|
|
value "pipelinedOperators_test"
|
|
)
|
|
(vvPair
|
|
variable "library_downstream_ModelSimCompiler"
|
|
value "$SCRATCH_DIR/PipelinedOperators_test"
|
|
)
|
|
(vvPair
|
|
variable "mm"
|
|
value "04"
|
|
)
|
|
(vvPair
|
|
variable "module_name"
|
|
value "pipelineAdder_tester"
|
|
)
|
|
(vvPair
|
|
variable "month"
|
|
value "avr."
|
|
)
|
|
(vvPair
|
|
variable "month_long"
|
|
value "avril"
|
|
)
|
|
(vvPair
|
|
variable "p"
|
|
value "C:\\dev\\sem-labs\\10-PipelinedOperators\\Prefs\\..\\PipelinedOperators_test\\hds\\pipeline@adder_tester\\interface"
|
|
)
|
|
(vvPair
|
|
variable "p_logical"
|
|
value "C:\\dev\\sem-labs\\10-PipelinedOperators\\Prefs\\..\\PipelinedOperators_test\\hds\\pipelineAdder_tester\\interface"
|
|
)
|
|
(vvPair
|
|
variable "package_name"
|
|
value "<Undefined Variable>"
|
|
)
|
|
(vvPair
|
|
variable "project_name"
|
|
value "hds"
|
|
)
|
|
(vvPair
|
|
variable "series"
|
|
value "HDL Designer Series"
|
|
)
|
|
(vvPair
|
|
variable "task_ADMS"
|
|
value "<TBD>"
|
|
)
|
|
(vvPair
|
|
variable "task_AsmPath"
|
|
value "$HEI_LIBS_DIR/NanoBlaze/hdl"
|
|
)
|
|
(vvPair
|
|
variable "task_DesignCompilerPath"
|
|
value "<TBD>"
|
|
)
|
|
(vvPair
|
|
variable "task_HDSPath"
|
|
value "$HDS_HOME"
|
|
)
|
|
(vvPair
|
|
variable "task_ISEBinPath"
|
|
value "$ISE_HOME"
|
|
)
|
|
(vvPair
|
|
variable "task_ISEPath"
|
|
value "$ISE_WORK_DIR"
|
|
)
|
|
(vvPair
|
|
variable "task_LeonardoPath"
|
|
value "<TBD>"
|
|
)
|
|
(vvPair
|
|
variable "task_ModelSimPath"
|
|
value "/usr/opt/Modelsim/modeltech/bin"
|
|
)
|
|
(vvPair
|
|
variable "task_NC"
|
|
value "<TBD>"
|
|
)
|
|
(vvPair
|
|
variable "task_PrecisionRTLPath"
|
|
value "<TBD>"
|
|
)
|
|
(vvPair
|
|
variable "task_QuestaSimPath"
|
|
value "<TBD>"
|
|
)
|
|
(vvPair
|
|
variable "task_VCSPath"
|
|
value "<TBD>"
|
|
)
|
|
(vvPair
|
|
variable "this_ext"
|
|
value "<TBD>"
|
|
)
|
|
(vvPair
|
|
variable "this_file"
|
|
value "interface"
|
|
)
|
|
(vvPair
|
|
variable "this_file_logical"
|
|
value "interface"
|
|
)
|
|
(vvPair
|
|
variable "time"
|
|
value "15:20:22"
|
|
)
|
|
(vvPair
|
|
variable "unit"
|
|
value "pipelineAdder_tester"
|
|
)
|
|
(vvPair
|
|
variable "user"
|
|
value "axel.amand"
|
|
)
|
|
(vvPair
|
|
variable "version"
|
|
value "2019.2 (Build 5)"
|
|
)
|
|
(vvPair
|
|
variable "view"
|
|
value "interface"
|
|
)
|
|
(vvPair
|
|
variable "year"
|
|
value "2023"
|
|
)
|
|
(vvPair
|
|
variable "yy"
|
|
value "23"
|
|
)
|
|
]
|
|
)
|
|
LanguageMgr "VhdlLangMgr"
|
|
uid 19,0
|
|
optionalChildren [
|
|
*71 (SymbolBody
|
|
uid 8,0
|
|
optionalChildren [
|
|
*72 (CptPort
|
|
uid 671,0
|
|
ps "OnEdgeStrategy"
|
|
shape (Triangle
|
|
uid 672,0
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "0,65535,0"
|
|
)
|
|
xt "50625,5250,51375,6000"
|
|
)
|
|
tg (CPTG
|
|
uid 673,0
|
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ps "CptPortTextPlaceStrategy"
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stg "RightVerticalLayoutStrategy"
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f (Text
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uid 674,0
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ro 270
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va (VaSet
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font "Verdana,12,0"
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)
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xt "50300,7000,51700,8600"
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|
st "a"
|
|
ju 2
|
|
blo "51500,7000"
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|
tm "CptPortNameMgr"
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)
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)
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dt (MLText
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|
uid 675,0
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va (VaSet
|
|
font "Courier New,8,0"
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)
|
|
xt "44000,3400,69500,4200"
|
|
st "a : OUT signed (adderBitNb-1 DOWNTO 0) ;
|
|
"
|
|
)
|
|
thePort (LogicalPort
|
|
m 1
|
|
decl (Decl
|
|
n "a"
|
|
t "signed"
|
|
b "(adderBitNb-1 DOWNTO 0)"
|
|
o 1
|
|
suid 49,0
|
|
)
|
|
)
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)
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*73 (CptPort
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uid 676,0
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ps "OnEdgeStrategy"
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shape (Triangle
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uid 677,0
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va (VaSet
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vasetType 1
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fg "0,65535,0"
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)
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xt "48625,5250,49375,6000"
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)
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tg (CPTG
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uid 678,0
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ps "CptPortTextPlaceStrategy"
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stg "RightVerticalLayoutStrategy"
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f (Text
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uid 679,0
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va (VaSet
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font "Verdana,12,0"
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st "b"
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ju 2
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blo "49500,7000"
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tm "CptPortNameMgr"
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dt (MLText
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font "Courier New,8,0"
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st "b : OUT signed (adderBitNb-1 DOWNTO 0) ;
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|
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|
|
)
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thePort (LogicalPort
|
|
m 1
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decl (Decl
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n "b"
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t "signed"
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b "(adderBitNb-1 DOWNTO 0)"
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|
o 2
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|
suid 50,0
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)
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)
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)
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*74 (CptPort
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uid 681,0
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ps "OnEdgeStrategy"
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shape (Triangle
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va (VaSet
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vasetType 1
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fg "0,65535,0"
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)
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xt "46625,5250,47375,6000"
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tg (CPTG
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uid 683,0
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ps "CptPortTextPlaceStrategy"
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stg "RightVerticalLayoutStrategy"
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f (Text
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uid 684,0
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ro 270
|
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va (VaSet
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font "Verdana,12,0"
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)
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xt "46300,7000,47700,9700"
|
|
st "cIn"
|
|
ju 2
|
|
blo "47500,7000"
|
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tm "CptPortNameMgr"
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dt (MLText
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uid 685,0
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va (VaSet
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font "Courier New,8,0"
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)
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xt "44000,5000,59500,5800"
|
|
st "cIn : OUT std_ulogic ;
|
|
"
|
|
)
|
|
thePort (LogicalPort
|
|
m 1
|
|
decl (Decl
|
|
n "cIn"
|
|
t "std_ulogic"
|
|
o 3
|
|
suid 51,0
|
|
)
|
|
)
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)
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*75 (CptPort
|
|
uid 686,0
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ps "OnEdgeStrategy"
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shape (Triangle
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uid 687,0
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va (VaSet
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vasetType 1
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fg "0,65535,0"
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)
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xt "26625,5250,27375,6000"
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)
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tg (CPTG
|
|
uid 688,0
|
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ps "CptPortTextPlaceStrategy"
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stg "RightVerticalLayoutStrategy"
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f (Text
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uid 689,0
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va (VaSet
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font "Verdana,12,0"
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)
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xt "26300,7000,27700,10800"
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|
st "clock"
|
|
ju 2
|
|
blo "27500,7000"
|
|
tm "CptPortNameMgr"
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)
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)
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dt (MLText
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uid 690,0
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va (VaSet
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font "Courier New,8,0"
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)
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xt "44000,5800,59500,6600"
|
|
st "clock : OUT std_ulogic ;
|
|
"
|
|
)
|
|
thePort (LogicalPort
|
|
m 1
|
|
decl (Decl
|
|
n "clock"
|
|
t "std_ulogic"
|
|
o 5
|
|
suid 52,0
|
|
)
|
|
)
|
|
)
|
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*76 (CptPort
|
|
uid 691,0
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ps "OnEdgeStrategy"
|
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shape (Triangle
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uid 692,0
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ro 180
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "0,65535,0"
|
|
)
|
|
xt "22625,5250,23375,6000"
|
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)
|
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tg (CPTG
|
|
uid 693,0
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ps "CptPortTextPlaceStrategy"
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stg "RightVerticalLayoutStrategy"
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f (Text
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uid 694,0
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ro 270
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va (VaSet
|
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font "Verdana,12,0"
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)
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|
xt "22300,7000,23700,10700"
|
|
st "cOut"
|
|
ju 2
|
|
blo "23500,7000"
|
|
tm "CptPortNameMgr"
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|
)
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)
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dt (MLText
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uid 695,0
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va (VaSet
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font "Courier New,8,0"
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)
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xt "44000,1800,59500,2600"
|
|
st "cOut : IN std_ulogic ;
|
|
"
|
|
)
|
|
thePort (LogicalPort
|
|
decl (Decl
|
|
n "cOut"
|
|
t "std_ulogic"
|
|
o 4
|
|
suid 53,0
|
|
)
|
|
)
|
|
)
|
|
*77 (CptPort
|
|
uid 696,0
|
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ps "OnEdgeStrategy"
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shape (Triangle
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uid 697,0
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va (VaSet
|
|
vasetType 1
|
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fg "0,65535,0"
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)
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xt "28625,5250,29375,6000"
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)
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tg (CPTG
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uid 698,0
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ps "CptPortTextPlaceStrategy"
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stg "RightVerticalLayoutStrategy"
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f (Text
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uid 699,0
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va (VaSet
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font "Verdana,12,0"
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)
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st "reset"
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ju 2
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blo "29500,7000"
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tm "CptPortNameMgr"
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dt (MLText
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uid 700,0
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va (VaSet
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font "Courier New,8,0"
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)
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xt "44000,6600,58500,7400"
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st "reset : OUT std_ulogic
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|
"
|
|
)
|
|
thePort (LogicalPort
|
|
m 1
|
|
decl (Decl
|
|
n "reset"
|
|
t "std_ulogic"
|
|
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|
suid 54,0
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|
)
|
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)
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)
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*78 (CptPort
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uid 701,0
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ps "OnEdgeStrategy"
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shape (Triangle
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uid 702,0
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|
va (VaSet
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vasetType 1
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fg "0,65535,0"
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)
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xt "36625,5250,37375,6000"
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)
|
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tg (CPTG
|
|
uid 703,0
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ps "CptPortTextPlaceStrategy"
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stg "RightVerticalLayoutStrategy"
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f (Text
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uid 704,0
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va (VaSet
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font "Verdana,12,0"
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)
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st "sum"
|
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ju 2
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|
blo "37500,7000"
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tm "CptPortNameMgr"
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)
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)
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dt (MLText
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uid 705,0
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va (VaSet
|
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font "Courier New,8,0"
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)
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|
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|
|
st "sum : IN signed (adderBitNb-1 DOWNTO 0) ;
|
|
"
|
|
)
|
|
thePort (LogicalPort
|
|
decl (Decl
|
|
n "sum"
|
|
t "signed"
|
|
b "(adderBitNb-1 DOWNTO 0)"
|
|
o 7
|
|
suid 55,0
|
|
)
|
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)
|
|
)
|
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shape (Rectangle
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uid 9,0
|
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va (VaSet
|
|
vasetType 1
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fg "0,65535,0"
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lineColor "0,32896,0"
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lineWidth 2
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)
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)
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oxt "15000,6000,78000,14000"
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biTextGroup (BiTextGroup
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uid 10,0
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ps "CenterOffsetStrategy"
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stg "VerticalLayoutStrategy"
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first (Text
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va (VaSet
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font "Verdana,8,1"
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)
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blo "30450,9800"
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second (Text
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va (VaSet
|
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font "Verdana,8,1"
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st "pipelineAdder_tester"
|
|
blo "30450,10800"
|
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|
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|
|
gi *79 (GenericInterface
|
|
uid 13,0
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ps "CenterOffsetStrategy"
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matrix (Matrix
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uid 14,0
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text (MLText
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uid 15,0
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va (VaSet
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font "Verdana,8,0"
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st "Generic Declarations
|
|
|
|
adderBitNb positive 32
|
|
stageNb positive 4
|
|
clockFrequency real 60.0E6 "
|
|
)
|
|
header "Generic Declarations"
|
|
showHdrWhenContentsEmpty 1
|
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)
|
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elements [
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|
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name "adderBitNb"
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type "positive"
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value "32"
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)
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(GiElement
|
|
name "stageNb"
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|
type "positive"
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|
value "4"
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)
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(GiElement
|
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name "clockFrequency"
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|
type "real"
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value "60.0E6"
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)
|
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]
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)
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|
portInstanceVisAsIs 1
|
|
portInstanceVis (PortSigDisplay
|
|
sTC 0
|
|
sF 0
|
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)
|
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portVis (PortSigDisplay
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|
sTC 0
|
|
sF 0
|
|
)
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)
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bg "65535,65535,65535"
|
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grid (Grid
|
|
origin "0,0"
|
|
isVisible 1
|
|
isActive 1
|
|
xSpacing 1000
|
|
xySpacing 1000
|
|
xShown 1
|
|
yShown 1
|
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color "26368,26368,26368"
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packageList *80 (PackageList
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uid 16,0
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stg "VerticalLayoutStrategy"
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textVec [
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va (VaSet
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tm "PackageList"
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text (MLText
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tm "CommentText"
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wrapOption 3
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visibleWidth 14600
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defaultRequirementText (RequirementText
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text (MLText
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|
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tm "RequirementText"
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