26 lines
620 B
Plaintext
26 lines
620 B
Plaintext
-- VHDL Entity Board.lissajousGenerator_circuit_EBS3.symbol
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--
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-- Created:
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-- by - axel.amand.UNKNOWN (WE7860)
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-- at - 17:45:49 01.05.2023
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--
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-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5)
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--
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LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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USE ieee.numeric_std.all;
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ENTITY lissajousGenerator_circuit_EBS3 IS
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PORT(
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clock : IN std_ulogic;
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reset_N : IN std_ulogic;
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triggerOut : OUT std_ulogic;
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xOut : OUT std_ulogic;
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yOut : OUT std_ulogic
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);
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-- Declarations
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END lissajousGenerator_circuit_EBS3 ;
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