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github-classroom[bot] d212040c30 Initial commit		2024-02-23 13:01:05 +00:00
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neorv32_dmem.cyclone2.vhd	Initial commit	2024-02-23 13:01:05 +00:00
neorv32_dmem.default.vhd	Initial commit	2024-02-23 13:01:05 +00:00
neorv32_imem.cyclone2.vhd	Initial commit	2024-02-23 13:01:05 +00:00
neorv32_imem.default.vhd	Initial commit	2024-02-23 13:01:05 +00:00
README.md	Initial commit	2024-02-23 13:01:05 +00:00

README.md

Processor Memory Source Files

This folder provides the architecture-only VHDL sources for the processor-internal memories (instruction memory "IMEM", data memory "DMEM"). Different implementations are available - but only one version of each (IMEM and DMEM) has to be added as actual source files.

For the first implementation the *.default.vhd files should be selected. The HDL style for describing memories used by these files has proven platform-independence across several FPGA architectures and toolchains.

If synthesis fails to infer actual block RAM resources from these default files, try the legacy *.cyclone2.vhd files, which provide a different HDL style. These files are intended for legacy support of older Intel/Altera Quartus versions (13.0 and older). However, these files do not use platform-specific macros or primitives - so they might also work for other FPGAs and toolchains.

⚠️ Make sure to add the selected files from this folder also to the neorv32 design library.