1739 lines
22 KiB
Plaintext
1739 lines
22 KiB
Plaintext
DocumentHdrVersion "1.1"
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Header (DocumentHdr
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version 2
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dialect 11
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dmPackageRefs [
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(DmPackageRef
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library "ieee"
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unitName "std_logic_1164"
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)
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(DmPackageRef
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library "ieee"
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unitName "numeric_std"
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itemName "ALL"
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)
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]
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libraryRefs [
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"ieee"
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]
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)
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version "26.1"
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appVersion "2018.1 (Build 12)"
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model (Symbol
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commonDM (CommonDM
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ldm (LogicalDM
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suid 7,0
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usingSuid 1
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emptyRow *1 (LEmptyRow
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)
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uid 102,0
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optionalChildren [
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*2 (RefLabelRowHdr
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)
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*3 (TitleRowHdr
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)
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*4 (FilterRowHdr
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)
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*5 (RefLabelColHdr
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tm "RefLabelColHdrMgr"
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)
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*6 (RowExpandColHdr
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tm "RowExpandColHdrMgr"
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)
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*7 (GroupColHdr
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tm "GroupColHdrMgr"
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)
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*8 (NameColHdr
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tm "NameColHdrMgr"
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)
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*9 (ModeColHdr
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tm "ModeColHdrMgr"
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)
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*10 (TypeColHdr
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tm "TypeColHdrMgr"
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)
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*11 (BoundsColHdr
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tm "BoundsColHdrMgr"
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)
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*12 (InitColHdr
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tm "InitColHdrMgr"
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)
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*13 (EolColHdr
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tm "EolColHdrMgr"
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)
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*14 (LogPort
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port (LogicalPort
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m 1
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decl (Decl
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n "clock"
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t "std_ulogic"
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o 1
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suid 1,0
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)
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)
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uid 86,0
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)
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*15 (LogPort
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port (LogicalPort
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m 1
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decl (Decl
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n "reset"
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t "std_ulogic"
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o 2
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suid 2,0
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)
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)
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uid 88,0
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)
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*16 (LogPort
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port (LogicalPort
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decl (Decl
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n "sawtooth"
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t "unsigned"
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b "(signalBitNb-1 DOWNTO 0)"
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o 3
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suid 3,0
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)
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)
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uid 90,0
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)
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*17 (LogPort
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port (LogicalPort
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decl (Decl
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n "sine"
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t "unsigned"
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b "(signalBitNb-1 DOWNTO 0)"
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o 4
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suid 4,0
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)
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)
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uid 92,0
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)
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*18 (LogPort
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port (LogicalPort
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decl (Decl
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n "square"
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t "unsigned"
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b "(signalBitNb-1 DOWNTO 0)"
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o 5
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suid 5,0
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)
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)
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uid 94,0
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)
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*19 (LogPort
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port (LogicalPort
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m 1
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decl (Decl
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n "step"
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t "unsigned"
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b "(phaseBitNb-1 DOWNTO 0)"
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o 6
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suid 6,0
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)
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)
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uid 96,0
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)
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*20 (LogPort
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port (LogicalPort
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decl (Decl
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n "triangle"
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t "unsigned"
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b "(signalBitNb-1 DOWNTO 0)"
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o 7
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suid 7,0
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)
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)
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uid 98,0
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)
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]
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)
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pdm (PhysicalDM
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displayShortBounds 1
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editShortBounds 1
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uid 115,0
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optionalChildren [
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*21 (Sheet
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sheetRow (SheetRow
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headerVa (MVa
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cellColor "49152,49152,49152"
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fontColor "0,0,0"
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font "courier,10,0"
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)
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cellVa (MVa
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cellColor "65535,65535,65535"
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fontColor "0,0,0"
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font "courier,10,0"
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)
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groupVa (MVa
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cellColor "39936,56832,65280"
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fontColor "0,0,0"
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font "courier,10,0"
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)
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emptyMRCItem *22 (MRCItem
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litem &1
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pos 3
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dimension 20
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)
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uid 117,0
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optionalChildren [
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*23 (MRCItem
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litem &2
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pos 0
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dimension 20
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uid 118,0
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)
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*24 (MRCItem
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litem &3
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pos 1
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dimension 23
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uid 119,0
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)
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*25 (MRCItem
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litem &4
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pos 2
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hidden 1
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dimension 20
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uid 120,0
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)
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*26 (MRCItem
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litem &14
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pos 0
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dimension 20
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uid 87,0
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)
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*27 (MRCItem
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litem &15
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pos 1
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dimension 20
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uid 89,0
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)
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*28 (MRCItem
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litem &16
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pos 2
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dimension 20
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uid 91,0
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)
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*29 (MRCItem
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litem &17
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pos 3
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dimension 20
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uid 93,0
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)
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*30 (MRCItem
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litem &18
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pos 4
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dimension 20
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uid 95,0
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)
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*31 (MRCItem
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litem &19
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pos 5
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dimension 20
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uid 97,0
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)
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*32 (MRCItem
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litem &20
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pos 6
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dimension 20
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uid 99,0
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)
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]
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)
|
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sheetCol (SheetCol
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|
propVa (MVa
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|
cellColor "0,49152,49152"
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fontColor "0,0,0"
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font "courier,10,0"
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textAngle 90
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)
|
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uid 121,0
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optionalChildren [
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*33 (MRCItem
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litem &5
|
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pos 0
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dimension 20
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uid 122,0
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)
|
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*34 (MRCItem
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litem &7
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pos 1
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dimension 50
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uid 123,0
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)
|
|
*35 (MRCItem
|
|
litem &8
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pos 2
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|
dimension 100
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|
uid 124,0
|
|
)
|
|
*36 (MRCItem
|
|
litem &9
|
|
pos 3
|
|
dimension 50
|
|
uid 125,0
|
|
)
|
|
*37 (MRCItem
|
|
litem &10
|
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pos 4
|
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dimension 100
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|
uid 126,0
|
|
)
|
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*38 (MRCItem
|
|
litem &11
|
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pos 5
|
|
dimension 100
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|
uid 127,0
|
|
)
|
|
*39 (MRCItem
|
|
litem &12
|
|
pos 6
|
|
dimension 50
|
|
uid 128,0
|
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)
|
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*40 (MRCItem
|
|
litem &13
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pos 7
|
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dimension 80
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|
uid 129,0
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)
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]
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)
|
|
fixedCol 4
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fixedRow 2
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name "Ports"
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uid 116,0
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vaOverrides [
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]
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)
|
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]
|
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)
|
|
uid 101,0
|
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)
|
|
genericsCommonDM (CommonDM
|
|
ldm (LogicalDM
|
|
emptyRow *41 (LEmptyRow
|
|
)
|
|
uid 131,0
|
|
optionalChildren [
|
|
*42 (RefLabelRowHdr
|
|
)
|
|
*43 (TitleRowHdr
|
|
)
|
|
*44 (FilterRowHdr
|
|
)
|
|
*45 (RefLabelColHdr
|
|
tm "RefLabelColHdrMgr"
|
|
)
|
|
*46 (RowExpandColHdr
|
|
tm "RowExpandColHdrMgr"
|
|
)
|
|
*47 (GroupColHdr
|
|
tm "GroupColHdrMgr"
|
|
)
|
|
*48 (NameColHdr
|
|
tm "GenericNameColHdrMgr"
|
|
)
|
|
*49 (TypeColHdr
|
|
tm "GenericTypeColHdrMgr"
|
|
)
|
|
*50 (InitColHdr
|
|
tm "GenericValueColHdrMgr"
|
|
)
|
|
*51 (PragmaColHdr
|
|
tm "GenericPragmaColHdrMgr"
|
|
)
|
|
*52 (EolColHdr
|
|
tm "GenericEolColHdrMgr"
|
|
)
|
|
]
|
|
)
|
|
pdm (PhysicalDM
|
|
displayShortBounds 1
|
|
editShortBounds 1
|
|
uid 143,0
|
|
optionalChildren [
|
|
*53 (Sheet
|
|
sheetRow (SheetRow
|
|
headerVa (MVa
|
|
cellColor "49152,49152,49152"
|
|
fontColor "0,0,0"
|
|
font "courier,10,0"
|
|
)
|
|
cellVa (MVa
|
|
cellColor "65535,65535,65535"
|
|
fontColor "0,0,0"
|
|
font "courier,10,0"
|
|
)
|
|
groupVa (MVa
|
|
cellColor "39936,56832,65280"
|
|
fontColor "0,0,0"
|
|
font "courier,10,0"
|
|
)
|
|
emptyMRCItem *54 (MRCItem
|
|
litem &41
|
|
pos 3
|
|
dimension 20
|
|
)
|
|
uid 145,0
|
|
optionalChildren [
|
|
*55 (MRCItem
|
|
litem &42
|
|
pos 0
|
|
dimension 20
|
|
uid 146,0
|
|
)
|
|
*56 (MRCItem
|
|
litem &43
|
|
pos 1
|
|
dimension 23
|
|
uid 147,0
|
|
)
|
|
*57 (MRCItem
|
|
litem &44
|
|
pos 2
|
|
hidden 1
|
|
dimension 20
|
|
uid 148,0
|
|
)
|
|
]
|
|
)
|
|
sheetCol (SheetCol
|
|
propVa (MVa
|
|
cellColor "0,49152,49152"
|
|
fontColor "0,0,0"
|
|
font "courier,10,0"
|
|
textAngle 90
|
|
)
|
|
uid 149,0
|
|
optionalChildren [
|
|
*58 (MRCItem
|
|
litem &45
|
|
pos 0
|
|
dimension 20
|
|
uid 150,0
|
|
)
|
|
*59 (MRCItem
|
|
litem &47
|
|
pos 1
|
|
dimension 50
|
|
uid 151,0
|
|
)
|
|
*60 (MRCItem
|
|
litem &48
|
|
pos 2
|
|
dimension 100
|
|
uid 152,0
|
|
)
|
|
*61 (MRCItem
|
|
litem &49
|
|
pos 3
|
|
dimension 100
|
|
uid 153,0
|
|
)
|
|
*62 (MRCItem
|
|
litem &50
|
|
pos 4
|
|
dimension 50
|
|
uid 154,0
|
|
)
|
|
*63 (MRCItem
|
|
litem &51
|
|
pos 5
|
|
dimension 50
|
|
uid 155,0
|
|
)
|
|
*64 (MRCItem
|
|
litem &52
|
|
pos 6
|
|
dimension 80
|
|
uid 156,0
|
|
)
|
|
]
|
|
)
|
|
fixedCol 3
|
|
fixedRow 2
|
|
name "Ports"
|
|
uid 144,0
|
|
vaOverrides [
|
|
]
|
|
)
|
|
]
|
|
)
|
|
uid 130,0
|
|
type 1
|
|
)
|
|
VExpander (VariableExpander
|
|
vvMap [
|
|
(vvPair
|
|
variable "HDLDir"
|
|
value "/home/francois/Documents/HEVs/SEm/SEm_labs/VHDL/SplineInterpolator/Prefs/../SplineInterpolator/hdl"
|
|
)
|
|
(vvPair
|
|
variable "HDSDir"
|
|
value "/home/francois/Documents/HEVs/SEm/SEm_labs/VHDL/SplineInterpolator/Prefs/../SplineInterpolator/hds"
|
|
)
|
|
(vvPair
|
|
variable "SideDataDesignDir"
|
|
value "/home/francois/Documents/HEVs/SEm/SEm_labs/VHDL/SplineInterpolator/Prefs/../SplineInterpolator/hds/sine@gen_tester/interface.info"
|
|
)
|
|
(vvPair
|
|
variable "SideDataUserDir"
|
|
value "/home/francois/Documents/HEVs/SEm/SEm_labs/VHDL/SplineInterpolator/Prefs/../SplineInterpolator/hds/sine@gen_tester/interface.user"
|
|
)
|
|
(vvPair
|
|
variable "SourceDir"
|
|
value "/home/francois/Documents/HEVs/SEm/SEm_labs/VHDL/SplineInterpolator/Prefs/../SplineInterpolator/hds"
|
|
)
|
|
(vvPair
|
|
variable "appl"
|
|
value "HDL Designer"
|
|
)
|
|
(vvPair
|
|
variable "arch_name"
|
|
value "interface"
|
|
)
|
|
(vvPair
|
|
variable "asm_file"
|
|
value "beamer.asm"
|
|
)
|
|
(vvPair
|
|
variable "concat_file"
|
|
value "concatenated"
|
|
)
|
|
(vvPair
|
|
variable "config"
|
|
value "%(unit)_%(view)_config"
|
|
)
|
|
(vvPair
|
|
variable "d"
|
|
value "/home/francois/Documents/HEVs/SEm/SEm_labs/VHDL/SplineInterpolator/Prefs/../SplineInterpolator/hds/sine@gen_tester"
|
|
)
|
|
(vvPair
|
|
variable "d_logical"
|
|
value "/home/francois/Documents/HEVs/SEm/SEm_labs/VHDL/SplineInterpolator/Prefs/../SplineInterpolator/hds/sineGen_tester"
|
|
)
|
|
(vvPair
|
|
variable "date"
|
|
value "01/17/19"
|
|
)
|
|
(vvPair
|
|
variable "day"
|
|
value "Thu"
|
|
)
|
|
(vvPair
|
|
variable "day_long"
|
|
value "Thursday"
|
|
)
|
|
(vvPair
|
|
variable "dd"
|
|
value "17"
|
|
)
|
|
(vvPair
|
|
variable "designName"
|
|
value "$DESIGN_NAME"
|
|
)
|
|
(vvPair
|
|
variable "entity_name"
|
|
value "sineGen_tester"
|
|
)
|
|
(vvPair
|
|
variable "ext"
|
|
value "<TBD>"
|
|
)
|
|
(vvPair
|
|
variable "f"
|
|
value "interface"
|
|
)
|
|
(vvPair
|
|
variable "f_logical"
|
|
value "interface"
|
|
)
|
|
(vvPair
|
|
variable "f_noext"
|
|
value "interface"
|
|
)
|
|
(vvPair
|
|
variable "graphical_source_author"
|
|
value "francois"
|
|
)
|
|
(vvPair
|
|
variable "graphical_source_date"
|
|
value "01/17/19"
|
|
)
|
|
(vvPair
|
|
variable "graphical_source_group"
|
|
value "francois"
|
|
)
|
|
(vvPair
|
|
variable "graphical_source_host"
|
|
value "Aphelia"
|
|
)
|
|
(vvPair
|
|
variable "graphical_source_time"
|
|
value "11:13:06"
|
|
)
|
|
(vvPair
|
|
variable "group"
|
|
value "francois"
|
|
)
|
|
(vvPair
|
|
variable "host"
|
|
value "Aphelia"
|
|
)
|
|
(vvPair
|
|
variable "language"
|
|
value "VHDL"
|
|
)
|
|
(vvPair
|
|
variable "library"
|
|
value "SplineInterpolator"
|
|
)
|
|
(vvPair
|
|
variable "library_downstream_ModelSimCompiler"
|
|
value "$SCRATCH_DIR/SplineInterpolator"
|
|
)
|
|
(vvPair
|
|
variable "mm"
|
|
value "01"
|
|
)
|
|
(vvPair
|
|
variable "module_name"
|
|
value "sineGen_tester"
|
|
)
|
|
(vvPair
|
|
variable "month"
|
|
value "Jan"
|
|
)
|
|
(vvPair
|
|
variable "month_long"
|
|
value "January"
|
|
)
|
|
(vvPair
|
|
variable "p"
|
|
value "/home/francois/Documents/HEVs/SEm/SEm_labs/VHDL/SplineInterpolator/Prefs/../SplineInterpolator/hds/sine@gen_tester/interface"
|
|
)
|
|
(vvPair
|
|
variable "p_logical"
|
|
value "/home/francois/Documents/HEVs/SEm/SEm_labs/VHDL/SplineInterpolator/Prefs/../SplineInterpolator/hds/sineGen_tester/interface"
|
|
)
|
|
(vvPair
|
|
variable "package_name"
|
|
value "<Undefined Variable>"
|
|
)
|
|
(vvPair
|
|
variable "project_name"
|
|
value "splineInterpolator"
|
|
)
|
|
(vvPair
|
|
variable "series"
|
|
value "HDL Designer Series"
|
|
)
|
|
(vvPair
|
|
variable "task_AsmPath"
|
|
value "$HEI_LIBS_DIR/NanoBlaze/hdl"
|
|
)
|
|
(vvPair
|
|
variable "task_HDSPath"
|
|
value "$HDS_HOME"
|
|
)
|
|
(vvPair
|
|
variable "task_ISEBinPath"
|
|
value "$ISE_HOME"
|
|
)
|
|
(vvPair
|
|
variable "task_ISEPath"
|
|
value "$ISE_WORK_DIR"
|
|
)
|
|
(vvPair
|
|
variable "task_ModelSimPath"
|
|
value "$MODELSIM_HOME/modeltech/bin"
|
|
)
|
|
(vvPair
|
|
variable "this_ext"
|
|
value "<TBD>"
|
|
)
|
|
(vvPair
|
|
variable "this_file"
|
|
value "interface"
|
|
)
|
|
(vvPair
|
|
variable "this_file_logical"
|
|
value "interface"
|
|
)
|
|
(vvPair
|
|
variable "time"
|
|
value "11:13:06"
|
|
)
|
|
(vvPair
|
|
variable "unit"
|
|
value "sineGen_tester"
|
|
)
|
|
(vvPair
|
|
variable "user"
|
|
value "francois"
|
|
)
|
|
(vvPair
|
|
variable "version"
|
|
value "2018.1 (Build 12)"
|
|
)
|
|
(vvPair
|
|
variable "view"
|
|
value "interface"
|
|
)
|
|
(vvPair
|
|
variable "year"
|
|
value "2019"
|
|
)
|
|
(vvPair
|
|
variable "yy"
|
|
value "19"
|
|
)
|
|
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|
|
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|
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LanguageMgr "Vhdl2008LangMgr"
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uid 100,0
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uid 8,0
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optionalChildren [
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uid 51,0
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tg (CPTG
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tg (CPTG
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uid 58,0
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ps "CptPortTextPlaceStrategy"
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blo "31250,7000"
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tm "CptPortNameMgr"
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decl (Decl
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ps "CptPortTextPlaceStrategy"
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blo "61250,7000"
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tm "CptPortNameMgr"
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decl (Decl
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n "sawtooth"
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t "unsigned"
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b "(signalBitNb-1 DOWNTO 0)"
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suid 3,0
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)
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)
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)
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*69 (CptPort
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uid 66,0
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ps "OnEdgeStrategy"
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shape (Triangle
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uid 67,0
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ro 180
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va (VaSet
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vasetType 1
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fg "0,65535,0"
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)
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xt "54625,5250,55375,6000"
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)
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tg (CPTG
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uid 68,0
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ps "CptPortTextPlaceStrategy"
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stg "RightVerticalLayoutStrategy"
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f (Text
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uid 69,0
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ro 270
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va (VaSet
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font "courier,8,0"
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xt "54550,7000,55450,9000"
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st "sine"
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ju 2
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|
blo "55250,7000"
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tm "CptPortNameMgr"
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)
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)
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dt (MLText
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uid 70,0
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va (VaSet
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font "courier,8,0"
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)
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st "sine : IN unsigned (signalBitNb-1 DOWNTO 0) ;"
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|
)
|
|
thePort (LogicalPort
|
|
decl (Decl
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|
n "sine"
|
|
t "unsigned"
|
|
b "(signalBitNb-1 DOWNTO 0)"
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|
o 4
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|
suid 4,0
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)
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)
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)
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*70 (CptPort
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uid 71,0
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ps "OnEdgeStrategy"
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shape (Triangle
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ro 180
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va (VaSet
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tg (CPTG
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uid 73,0
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ps "CptPortTextPlaceStrategy"
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f (Text
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uid 74,0
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va (VaSet
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font "courier,8,0"
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blo "59250,7000"
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tm "CptPortNameMgr"
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font "courier,8,0"
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)
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thePort (LogicalPort
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decl (Decl
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|
n "square"
|
|
t "unsigned"
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b "(signalBitNb-1 DOWNTO 0)"
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|
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|
suid 5,0
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|
)
|
|
)
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|
)
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*71 (CptPort
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uid 76,0
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ps "OnEdgeStrategy"
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shape (Triangle
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uid 77,0
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va (VaSet
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vasetType 1
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fg "0,65535,0"
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)
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|
)
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tg (CPTG
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uid 78,0
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ps "CptPortTextPlaceStrategy"
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stg "RightVerticalLayoutStrategy"
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uid 79,0
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va (VaSet
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font "courier,8,0"
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)
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|
st "step"
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|
ju 2
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|
blo "23250,7000"
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tm "CptPortNameMgr"
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)
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|
)
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dt (MLText
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|
uid 80,0
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va (VaSet
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|
font "courier,8,0"
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)
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|
st "step : OUT unsigned (phaseBitNb-1 DOWNTO 0)"
|
|
)
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thePort (LogicalPort
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|
m 1
|
|
decl (Decl
|
|
n "step"
|
|
t "unsigned"
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b "(phaseBitNb-1 DOWNTO 0)"
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|
o 6
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|
suid 6,0
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)
|
|
)
|
|
)
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*72 (CptPort
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uid 81,0
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ps "OnEdgeStrategy"
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shape (Triangle
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uid 82,0
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ro 180
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va (VaSet
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vasetType 1
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fg "0,65535,0"
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)
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|
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|
)
|
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tg (CPTG
|
|
uid 83,0
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ps "CptPortTextPlaceStrategy"
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stg "RightVerticalLayoutStrategy"
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f (Text
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uid 84,0
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ro 270
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va (VaSet
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font "courier,8,0"
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ju 2
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blo "57250,7000"
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tm "CptPortNameMgr"
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dt (MLText
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va (VaSet
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font "courier,8,0"
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decl (Decl
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n "triangle"
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t "unsigned"
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b "(signalBitNb-1 DOWNTO 0)"
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suid 7,0
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va (VaSet
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lineColor "0,32896,0"
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biTextGroup (BiTextGroup
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uid 10,0
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va (VaSet
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elements [
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portVis (PortSigDisplay
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