1572 lines
19 KiB
Plaintext
1572 lines
19 KiB
Plaintext
DocumentHdrVersion "1.1"
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Header (DocumentHdr
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version 2
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dmPackageRefs [
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(DmPackageRef
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library "ieee"
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unitName "std_logic_1164"
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)
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(DmPackageRef
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library "ieee"
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unitName "numeric_std"
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itemName "ALL"
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)
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]
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libraryRefs [
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"ieee"
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]
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)
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version "24.1"
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appVersion "2007.1a (Build 13)"
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model (Symbol
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commonDM (CommonDM
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ldm (LogicalDM
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suid 2009,0
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usingSuid 1
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emptyRow *1 (LEmptyRow
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)
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uid 151,0
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optionalChildren [
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*2 (RefLabelRowHdr
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)
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*3 (TitleRowHdr
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)
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*4 (FilterRowHdr
|
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)
|
|
*5 (RefLabelColHdr
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tm "RefLabelColHdrMgr"
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)
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|
*6 (RowExpandColHdr
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|
tm "RowExpandColHdrMgr"
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|
)
|
|
*7 (GroupColHdr
|
|
tm "GroupColHdrMgr"
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|
)
|
|
*8 (NameColHdr
|
|
tm "NameColHdrMgr"
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|
)
|
|
*9 (ModeColHdr
|
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tm "ModeColHdrMgr"
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)
|
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*10 (TypeColHdr
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tm "TypeColHdrMgr"
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)
|
|
*11 (BoundsColHdr
|
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tm "BoundsColHdrMgr"
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)
|
|
*12 (InitColHdr
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|
tm "InitColHdrMgr"
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)
|
|
*13 (EolColHdr
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|
tm "EolColHdrMgr"
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|
)
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*14 (LogPort
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port (LogicalPort
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m 1
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decl (Decl
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n "clock"
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t "std_ulogic"
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o 3
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suid 2005,0
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)
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)
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uid 208,0
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)
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*15 (LogPort
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port (LogicalPort
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|
m 1
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decl (Decl
|
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n "reset"
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|
t "std_ulogic"
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o 2
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suid 2006,0
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)
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)
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uid 210,0
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)
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*16 (LogPort
|
|
port (LogicalPort
|
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decl (Decl
|
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n "triggerOut"
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|
t "std_ulogic"
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o 4
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suid 2007,0
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)
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)
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uid 212,0
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)
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*17 (LogPort
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port (LogicalPort
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decl (Decl
|
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n "xOut"
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|
t "std_ulogic"
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o 5
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suid 2008,0
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)
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)
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uid 214,0
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)
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*18 (LogPort
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port (LogicalPort
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decl (Decl
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n "yOut"
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t "std_ulogic"
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o 8
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suid 2009,0
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)
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)
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uid 216,0
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)
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]
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)
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pdm (PhysicalDM
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uid 156,0
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optionalChildren [
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*19 (Sheet
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sheetRow (SheetRow
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headerVa (MVa
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cellColor "49152,49152,49152"
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fontColor "0,0,0"
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font "Tahoma,10,0"
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)
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cellVa (MVa
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cellColor "65535,65535,65535"
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fontColor "0,0,0"
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font "Tahoma,10,0"
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)
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groupVa (MVa
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cellColor "39936,56832,65280"
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fontColor "0,0,0"
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font "Tahoma,10,0"
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)
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emptyMRCItem *20 (MRCItem
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litem &1
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pos 3
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dimension 20
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)
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uid 93,0
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optionalChildren [
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*21 (MRCItem
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litem &2
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pos 0
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dimension 20
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uid 96,0
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)
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*22 (MRCItem
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litem &3
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pos 1
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dimension 23
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uid 98,0
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)
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*23 (MRCItem
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litem &4
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pos 2
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hidden 1
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dimension 20
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uid 100,0
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)
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*24 (MRCItem
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litem &14
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pos 0
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dimension 20
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uid 209,0
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)
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*25 (MRCItem
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litem &15
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pos 1
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dimension 20
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uid 211,0
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)
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*26 (MRCItem
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litem &16
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pos 2
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dimension 20
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uid 213,0
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)
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*27 (MRCItem
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litem &17
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pos 3
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dimension 20
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uid 215,0
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)
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*28 (MRCItem
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litem &18
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pos 4
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dimension 20
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uid 217,0
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)
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]
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)
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sheetCol (SheetCol
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propVa (MVa
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cellColor "0,49152,49152"
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fontColor "0,0,0"
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font "Tahoma,10,0"
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textAngle 90
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)
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uid 94,0
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optionalChildren [
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*29 (MRCItem
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litem &5
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pos 0
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dimension 20
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uid 102,0
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)
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*30 (MRCItem
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litem &7
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pos 1
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dimension 50
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uid 106,0
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)
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*31 (MRCItem
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litem &8
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pos 2
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dimension 100
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uid 108,0
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)
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*32 (MRCItem
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litem &9
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pos 3
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dimension 50
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uid 110,0
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)
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*33 (MRCItem
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litem &10
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pos 4
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dimension 100
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uid 112,0
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)
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*34 (MRCItem
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litem &11
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pos 5
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dimension 100
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uid 114,0
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)
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*35 (MRCItem
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litem &12
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pos 6
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dimension 50
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uid 116,0
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)
|
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*36 (MRCItem
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litem &13
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pos 7
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dimension 80
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uid 118,0
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)
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]
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)
|
|
fixedCol 4
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fixedRow 2
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name "Ports"
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uid 92,0
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vaOverrides [
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]
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)
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]
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)
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uid 150,0
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)
|
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genericsCommonDM (CommonDM
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ldm (LogicalDM
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emptyRow *37 (LEmptyRow
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)
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uid 158,0
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optionalChildren [
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|
*38 (RefLabelRowHdr
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)
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*39 (TitleRowHdr
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)
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*40 (FilterRowHdr
|
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)
|
|
*41 (RefLabelColHdr
|
|
tm "RefLabelColHdrMgr"
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)
|
|
*42 (RowExpandColHdr
|
|
tm "RowExpandColHdrMgr"
|
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)
|
|
*43 (GroupColHdr
|
|
tm "GroupColHdrMgr"
|
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)
|
|
*44 (NameColHdr
|
|
tm "GenericNameColHdrMgr"
|
|
)
|
|
*45 (TypeColHdr
|
|
tm "GenericTypeColHdrMgr"
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)
|
|
*46 (InitColHdr
|
|
tm "GenericValueColHdrMgr"
|
|
)
|
|
*47 (PragmaColHdr
|
|
tm "GenericPragmaColHdrMgr"
|
|
)
|
|
*48 (EolColHdr
|
|
tm "GenericEolColHdrMgr"
|
|
)
|
|
*49 (LogGeneric
|
|
generic (GiElement
|
|
name "signalBitNb"
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type "positive"
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value "16"
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|
)
|
|
uid 148,0
|
|
)
|
|
]
|
|
)
|
|
pdm (PhysicalDM
|
|
uid 159,0
|
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optionalChildren [
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*50 (Sheet
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sheetRow (SheetRow
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headerVa (MVa
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cellColor "49152,49152,49152"
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fontColor "0,0,0"
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font "Tahoma,10,0"
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)
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cellVa (MVa
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cellColor "65535,65535,65535"
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fontColor "0,0,0"
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font "Tahoma,10,0"
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)
|
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groupVa (MVa
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cellColor "39936,56832,65280"
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fontColor "0,0,0"
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font "Tahoma,10,0"
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)
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emptyMRCItem *51 (MRCItem
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litem &37
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pos 3
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dimension 20
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)
|
|
uid 124,0
|
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optionalChildren [
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*52 (MRCItem
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litem &38
|
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pos 0
|
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dimension 20
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uid 127,0
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)
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*53 (MRCItem
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litem &39
|
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pos 1
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dimension 23
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|
uid 129,0
|
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)
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*54 (MRCItem
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litem &40
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pos 2
|
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hidden 1
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|
dimension 20
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uid 131,0
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)
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*55 (MRCItem
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litem &49
|
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pos 0
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dimension 20
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uid 149,0
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)
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]
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)
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sheetCol (SheetCol
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propVa (MVa
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cellColor "0,49152,49152"
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fontColor "0,0,0"
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font "Tahoma,10,0"
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textAngle 90
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)
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uid 125,0
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optionalChildren [
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*56 (MRCItem
|
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litem &41
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pos 0
|
|
dimension 20
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|
uid 133,0
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)
|
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*57 (MRCItem
|
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litem &43
|
|
pos 1
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dimension 50
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uid 137,0
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)
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*58 (MRCItem
|
|
litem &44
|
|
pos 2
|
|
dimension 100
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|
uid 139,0
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)
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*59 (MRCItem
|
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litem &45
|
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pos 3
|
|
dimension 100
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|
uid 141,0
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)
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*60 (MRCItem
|
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litem &46
|
|
pos 4
|
|
dimension 50
|
|
uid 143,0
|
|
)
|
|
*61 (MRCItem
|
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litem &47
|
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pos 5
|
|
dimension 50
|
|
uid 145,0
|
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)
|
|
*62 (MRCItem
|
|
litem &48
|
|
pos 6
|
|
dimension 80
|
|
uid 147,0
|
|
)
|
|
]
|
|
)
|
|
fixedCol 3
|
|
fixedRow 2
|
|
name "Ports"
|
|
uid 123,0
|
|
vaOverrides [
|
|
]
|
|
)
|
|
]
|
|
)
|
|
uid 157,0
|
|
type 1
|
|
)
|
|
VExpander (VariableExpander
|
|
vvMap [
|
|
(vvPair
|
|
variable " "
|
|
value " "
|
|
)
|
|
(vvPair
|
|
variable "HDLDir"
|
|
value "U:\\SEm_labs\\Prefs\\..\\Board\\hdl"
|
|
)
|
|
(vvPair
|
|
variable "HDSDir"
|
|
value "U:\\SEm_labs\\Prefs\\..\\Board\\hds"
|
|
)
|
|
(vvPair
|
|
variable "SideDataDesignDir"
|
|
value "U:\\SEm_labs\\Prefs\\..\\Board\\hds\\@f@p@g@a_sine@gen_tester\\interface.info"
|
|
)
|
|
(vvPair
|
|
variable "SideDataUserDir"
|
|
value "U:\\SEm_labs\\Prefs\\..\\Board\\hds\\@f@p@g@a_sine@gen_tester\\interface.user"
|
|
)
|
|
(vvPair
|
|
variable "SourceDir"
|
|
value "U:\\SEm_labs\\Prefs\\..\\Board\\hds"
|
|
)
|
|
(vvPair
|
|
variable "appl"
|
|
value "HDL Designer"
|
|
)
|
|
(vvPair
|
|
variable "arch_name"
|
|
value "interface"
|
|
)
|
|
(vvPair
|
|
variable "concat_file"
|
|
value "chronometer"
|
|
)
|
|
(vvPair
|
|
variable "config"
|
|
value "%(unit)_config"
|
|
)
|
|
(vvPair
|
|
variable "d"
|
|
value "U:\\SEm_labs\\Prefs\\..\\Board\\hds\\@f@p@g@a_sine@gen_tester"
|
|
)
|
|
(vvPair
|
|
variable "d_logical"
|
|
value "U:\\SEm_labs\\Prefs\\..\\Board\\hds\\FPGA_sineGen_tester"
|
|
)
|
|
(vvPair
|
|
variable "date"
|
|
value "27.01.2010"
|
|
)
|
|
(vvPair
|
|
variable "day"
|
|
value "mer."
|
|
)
|
|
(vvPair
|
|
variable "day_long"
|
|
value "mercredi"
|
|
)
|
|
(vvPair
|
|
variable "dd"
|
|
value "27"
|
|
)
|
|
(vvPair
|
|
variable "entity_name"
|
|
value "FPGA_sineGen_tester"
|
|
)
|
|
(vvPair
|
|
variable "ext"
|
|
value "<TBD>"
|
|
)
|
|
(vvPair
|
|
variable "f"
|
|
value "interface"
|
|
)
|
|
(vvPair
|
|
variable "f_logical"
|
|
value "interface"
|
|
)
|
|
(vvPair
|
|
variable "f_noext"
|
|
value "interface"
|
|
)
|
|
(vvPair
|
|
variable "group"
|
|
value "UNKNOWN"
|
|
)
|
|
(vvPair
|
|
variable "host"
|
|
value "WE3195"
|
|
)
|
|
(vvPair
|
|
variable "language"
|
|
value "VHDL"
|
|
)
|
|
(vvPair
|
|
variable "library"
|
|
value "Board"
|
|
)
|
|
(vvPair
|
|
variable "library_downstream_Concatenation"
|
|
value "$HDS_PROJECT_DIR/../Board/concat"
|
|
)
|
|
(vvPair
|
|
variable "library_downstream_Generic_1_file"
|
|
value "U:\\SEm_curves\\Synthesis"
|
|
)
|
|
(vvPair
|
|
variable "library_downstream_ModelSim"
|
|
value "D:\\Users\\ELN_labs\\VHDL_comp"
|
|
)
|
|
(vvPair
|
|
variable "library_downstream_ModelSimCompiler"
|
|
value "D:/Labs/ElN/Chronometer/Board/work"
|
|
)
|
|
(vvPair
|
|
variable "library_downstream_SpyGlass"
|
|
value "U:\\SEm_curves\\Synthesis"
|
|
)
|
|
(vvPair
|
|
variable "mm"
|
|
value "01"
|
|
)
|
|
(vvPair
|
|
variable "module_name"
|
|
value "FPGA_sineGen_tester"
|
|
)
|
|
(vvPair
|
|
variable "month"
|
|
value "janv."
|
|
)
|
|
(vvPair
|
|
variable "month_long"
|
|
value "janvier"
|
|
)
|
|
(vvPair
|
|
variable "p"
|
|
value "U:\\SEm_labs\\Prefs\\..\\Board\\hds\\@f@p@g@a_sine@gen_tester\\interface"
|
|
)
|
|
(vvPair
|
|
variable "p_logical"
|
|
value "U:\\SEm_labs\\Prefs\\..\\Board\\hds\\FPGA_sineGen_tester\\interface"
|
|
)
|
|
(vvPair
|
|
variable "package_name"
|
|
value "<Undefined Variable>"
|
|
)
|
|
(vvPair
|
|
variable "project_name"
|
|
value "hds"
|
|
)
|
|
(vvPair
|
|
variable "series"
|
|
value "HDL Designer Series"
|
|
)
|
|
(vvPair
|
|
variable "task_ADMS"
|
|
value "<TBD>"
|
|
)
|
|
(vvPair
|
|
variable "task_DesignCompilerPath"
|
|
value "<TBD>"
|
|
)
|
|
(vvPair
|
|
variable "task_ISEPath"
|
|
value "D:\\Labs\\ElN\\Chronometer\\Board\\ise"
|
|
)
|
|
(vvPair
|
|
variable "task_LeonardoPath"
|
|
value "<TBD>"
|
|
)
|
|
(vvPair
|
|
variable "task_ModelSimPath"
|
|
value "C:\\EDA\\Modelsim\\win32"
|
|
)
|
|
(vvPair
|
|
variable "task_NC"
|
|
value "<TBD>"
|
|
)
|
|
(vvPair
|
|
variable "task_PrecisionRTLPath"
|
|
value "<TBD>"
|
|
)
|
|
(vvPair
|
|
variable "task_QuestaSimPath"
|
|
value "<TBD>"
|
|
)
|
|
(vvPair
|
|
variable "task_VCSPath"
|
|
value "<TBD>"
|
|
)
|
|
(vvPair
|
|
variable "this_ext"
|
|
value "<TBD>"
|
|
)
|
|
(vvPair
|
|
variable "this_file"
|
|
value "interface"
|
|
)
|
|
(vvPair
|
|
variable "this_file_logical"
|
|
value "interface"
|
|
)
|
|
(vvPair
|
|
variable "time"
|
|
value "11:20:56"
|
|
)
|
|
(vvPair
|
|
variable "unit"
|
|
value "FPGA_sineGen_tester"
|
|
)
|
|
(vvPair
|
|
variable "user"
|
|
value "cof"
|
|
)
|
|
(vvPair
|
|
variable "version"
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