2037 lines
25 KiB
Plaintext
2037 lines
25 KiB
Plaintext
DocumentHdrVersion "1.1"
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Header (DocumentHdr
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version 2
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dmPackageRefs [
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(DmPackageRef
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library "ieee"
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unitName "std_logic_1164"
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)
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(DmPackageRef
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library "ieee"
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unitName "numeric_std"
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)
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(DmPackageRef
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library "AhbLite"
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unitName "ahbLite"
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)
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]
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libraryRefs [
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"ieee"
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"AhbLite"
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]
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)
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version "27.1"
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appVersion "2019.2 (Build 5)"
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model (Symbol
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commonDM (CommonDM
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ldm (LogicalDM
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suid 66,0
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usingSuid 1
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emptyRow *1 (LEmptyRow
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)
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uid 130,0
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optionalChildren [
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*2 (RefLabelRowHdr
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)
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*3 (TitleRowHdr
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)
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*4 (FilterRowHdr
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)
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*5 (RefLabelColHdr
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tm "RefLabelColHdrMgr"
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)
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*6 (RowExpandColHdr
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tm "RowExpandColHdrMgr"
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)
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|
*7 (GroupColHdr
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tm "GroupColHdrMgr"
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)
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|
*8 (NameColHdr
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tm "NameColHdrMgr"
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)
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*9 (ModeColHdr
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tm "ModeColHdrMgr"
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)
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*10 (TypeColHdr
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tm "TypeColHdrMgr"
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)
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*11 (BoundsColHdr
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tm "BoundsColHdrMgr"
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)
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|
*12 (InitColHdr
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tm "InitColHdrMgr"
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)
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|
*13 (EolColHdr
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tm "EolColHdrMgr"
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)
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|
*14 (LogPort
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port (LogicalPort
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m 1
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decl (Decl
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n "hAddr"
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t "unsigned"
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b "( ahbAddressBitNb-1 DOWNTO 0 )"
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o 1
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suid 56,0
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)
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)
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uid 713,0
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)
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*15 (LogPort
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port (LogicalPort
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m 1
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decl (Decl
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n "hClk"
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t "std_uLogic"
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o 2
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suid 57,0
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)
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)
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uid 715,0
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)
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*16 (LogPort
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port (LogicalPort
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decl (Decl
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n "hRData"
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t "std_ulogic_vector"
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b "(ahbDataBitNb-1 DOWNTO 0)"
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o 3
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suid 58,0
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)
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)
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uid 717,0
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)
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*17 (LogPort
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port (LogicalPort
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|
decl (Decl
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n "hReady"
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t "std_uLogic"
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o 4
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suid 59,0
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)
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)
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uid 719,0
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)
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*18 (LogPort
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port (LogicalPort
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|
m 1
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decl (Decl
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n "hReset_n"
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t "std_uLogic"
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o 5
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suid 60,0
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)
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)
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uid 721,0
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)
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|
*19 (LogPort
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port (LogicalPort
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|
decl (Decl
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|
n "hResp"
|
|
t "std_uLogic"
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o 6
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suid 61,0
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)
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)
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uid 723,0
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)
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|
*20 (LogPort
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port (LogicalPort
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|
m 1
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|
decl (Decl
|
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n "hSel"
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t "std_uLogic"
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o 7
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suid 62,0
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)
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)
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uid 725,0
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)
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*21 (LogPort
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port (LogicalPort
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m 1
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decl (Decl
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n "hTrans"
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t "std_ulogic_vector"
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|
b "(ahbTransBitNb-1 DOWNTO 0)"
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o 8
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suid 63,0
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)
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)
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uid 727,0
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)
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*22 (LogPort
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port (LogicalPort
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m 1
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|
decl (Decl
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n "hWData"
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t "std_ulogic_vector"
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|
b "(ahbDataBitNb-1 DOWNTO 0)"
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o 9
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suid 64,0
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)
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)
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|
uid 729,0
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)
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*23 (LogPort
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port (LogicalPort
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|
m 1
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|
decl (Decl
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|
n "hWrite"
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|
t "std_uLogic"
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o 10
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suid 65,0
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)
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)
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uid 731,0
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)
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*24 (LogPort
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port (LogicalPort
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m 2
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decl (Decl
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|
n "io"
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|
t "std_logic_vector"
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b "(ioNb-1 DOWNTO 0)"
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o 11
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suid 66,0
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)
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)
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|
uid 733,0
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)
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]
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)
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pdm (PhysicalDM
|
|
displayShortBounds 1
|
|
editShortBounds 1
|
|
uid 143,0
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|
optionalChildren [
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*25 (Sheet
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|
sheetRow (SheetRow
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|
headerVa (MVa
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|
cellColor "49152,49152,49152"
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fontColor "0,0,0"
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font "Tahoma,10,0"
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)
|
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cellVa (MVa
|
|
cellColor "65535,65535,65535"
|
|
fontColor "0,0,0"
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font "Tahoma,10,0"
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)
|
|
groupVa (MVa
|
|
cellColor "39936,56832,65280"
|
|
fontColor "0,0,0"
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font "Tahoma,10,0"
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)
|
|
emptyMRCItem *26 (MRCItem
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litem &1
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pos 11
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dimension 20
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)
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uid 145,0
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optionalChildren [
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*27 (MRCItem
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litem &2
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pos 0
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dimension 20
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uid 146,0
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)
|
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*28 (MRCItem
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litem &3
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pos 1
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dimension 23
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|
uid 147,0
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)
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*29 (MRCItem
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litem &4
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pos 2
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hidden 1
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dimension 20
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|
uid 148,0
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)
|
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*30 (MRCItem
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litem &14
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pos 0
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dimension 20
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uid 714,0
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)
|
|
*31 (MRCItem
|
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litem &15
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pos 1
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dimension 20
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uid 716,0
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)
|
|
*32 (MRCItem
|
|
litem &16
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pos 2
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dimension 20
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|
uid 718,0
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)
|
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*33 (MRCItem
|
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litem &17
|
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pos 3
|
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dimension 20
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|
uid 720,0
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)
|
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*34 (MRCItem
|
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litem &18
|
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pos 4
|
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dimension 20
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|
uid 722,0
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)
|
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*35 (MRCItem
|
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litem &19
|
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pos 5
|
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dimension 20
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|
uid 724,0
|
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)
|
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*36 (MRCItem
|
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litem &20
|
|
pos 6
|
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dimension 20
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uid 726,0
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)
|
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*37 (MRCItem
|
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litem &21
|
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pos 7
|
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dimension 20
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uid 728,0
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)
|
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*38 (MRCItem
|
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litem &22
|
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pos 8
|
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dimension 20
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uid 730,0
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)
|
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*39 (MRCItem
|
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litem &23
|
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pos 9
|
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dimension 20
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|
uid 732,0
|
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)
|
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*40 (MRCItem
|
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litem &24
|
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pos 10
|
|
dimension 20
|
|
uid 734,0
|
|
)
|
|
]
|
|
)
|
|
sheetCol (SheetCol
|
|
propVa (MVa
|
|
cellColor "0,49152,49152"
|
|
fontColor "0,0,0"
|
|
font "Tahoma,10,0"
|
|
textAngle 90
|
|
)
|
|
uid 149,0
|
|
optionalChildren [
|
|
*41 (MRCItem
|
|
litem &5
|
|
pos 0
|
|
dimension 20
|
|
uid 150,0
|
|
)
|
|
*42 (MRCItem
|
|
litem &7
|
|
pos 1
|
|
dimension 50
|
|
uid 151,0
|
|
)
|
|
*43 (MRCItem
|
|
litem &8
|
|
pos 2
|
|
dimension 100
|
|
uid 152,0
|
|
)
|
|
*44 (MRCItem
|
|
litem &9
|
|
pos 3
|
|
dimension 50
|
|
uid 153,0
|
|
)
|
|
*45 (MRCItem
|
|
litem &10
|
|
pos 4
|
|
dimension 100
|
|
uid 154,0
|
|
)
|
|
*46 (MRCItem
|
|
litem &11
|
|
pos 5
|
|
dimension 100
|
|
uid 155,0
|
|
)
|
|
*47 (MRCItem
|
|
litem &12
|
|
pos 6
|
|
dimension 50
|
|
uid 156,0
|
|
)
|
|
*48 (MRCItem
|
|
litem &13
|
|
pos 7
|
|
dimension 80
|
|
uid 157,0
|
|
)
|
|
]
|
|
)
|
|
fixedCol 4
|
|
fixedRow 2
|
|
name "Ports"
|
|
uid 144,0
|
|
vaOverrides [
|
|
]
|
|
)
|
|
]
|
|
)
|
|
uid 129,0
|
|
)
|
|
genericsCommonDM (CommonDM
|
|
ldm (LogicalDM
|
|
emptyRow *49 (LEmptyRow
|
|
)
|
|
uid 159,0
|
|
optionalChildren [
|
|
*50 (RefLabelRowHdr
|
|
)
|
|
*51 (TitleRowHdr
|
|
)
|
|
*52 (FilterRowHdr
|
|
)
|
|
*53 (RefLabelColHdr
|
|
tm "RefLabelColHdrMgr"
|
|
)
|
|
*54 (RowExpandColHdr
|
|
tm "RowExpandColHdrMgr"
|
|
)
|
|
*55 (GroupColHdr
|
|
tm "GroupColHdrMgr"
|
|
)
|
|
*56 (NameColHdr
|
|
tm "GenericNameColHdrMgr"
|
|
)
|
|
*57 (TypeColHdr
|
|
tm "GenericTypeColHdrMgr"
|
|
)
|
|
*58 (InitColHdr
|
|
tm "GenericValueColHdrMgr"
|
|
)
|
|
*59 (PragmaColHdr
|
|
tm "GenericPragmaColHdrMgr"
|
|
)
|
|
*60 (EolColHdr
|
|
tm "GenericEolColHdrMgr"
|
|
)
|
|
*61 (LogGeneric
|
|
generic (GiElement
|
|
name "ioNb"
|
|
type "positive"
|
|
value ""
|
|
)
|
|
uid 208,0
|
|
)
|
|
*62 (LogGeneric
|
|
generic (GiElement
|
|
name "clockFrequency"
|
|
type "real"
|
|
value ""
|
|
)
|
|
uid 433,0
|
|
)
|
|
]
|
|
)
|
|
pdm (PhysicalDM
|
|
displayShortBounds 1
|
|
editShortBounds 1
|
|
uid 171,0
|
|
optionalChildren [
|
|
*63 (Sheet
|
|
sheetRow (SheetRow
|
|
headerVa (MVa
|
|
cellColor "49152,49152,49152"
|
|
fontColor "0,0,0"
|
|
font "Tahoma,10,0"
|
|
)
|
|
cellVa (MVa
|
|
cellColor "65535,65535,65535"
|
|
fontColor "0,0,0"
|
|
font "Tahoma,10,0"
|
|
)
|
|
groupVa (MVa
|
|
cellColor "39936,56832,65280"
|
|
fontColor "0,0,0"
|
|
font "Tahoma,10,0"
|
|
)
|
|
emptyMRCItem *64 (MRCItem
|
|
litem &49
|
|
pos 2
|
|
dimension 20
|
|
)
|
|
uid 173,0
|
|
optionalChildren [
|
|
*65 (MRCItem
|
|
litem &50
|
|
pos 0
|
|
dimension 20
|
|
uid 174,0
|
|
)
|
|
*66 (MRCItem
|
|
litem &51
|
|
pos 1
|
|
dimension 23
|
|
uid 175,0
|
|
)
|
|
*67 (MRCItem
|
|
litem &52
|
|
pos 2
|
|
hidden 1
|
|
dimension 20
|
|
uid 176,0
|
|
)
|
|
*68 (MRCItem
|
|
litem &61
|
|
pos 0
|
|
dimension 20
|
|
uid 209,0
|
|
)
|
|
*69 (MRCItem
|
|
litem &62
|
|
pos 1
|
|
dimension 20
|
|
uid 434,0
|
|
)
|
|
]
|
|
)
|
|
sheetCol (SheetCol
|
|
propVa (MVa
|
|
cellColor "0,49152,49152"
|
|
fontColor "0,0,0"
|
|
font "Tahoma,10,0"
|
|
textAngle 90
|
|
)
|
|
uid 177,0
|
|
optionalChildren [
|
|
*70 (MRCItem
|
|
litem &53
|
|
pos 0
|
|
dimension 20
|
|
uid 178,0
|
|
)
|
|
*71 (MRCItem
|
|
litem &55
|
|
pos 1
|
|
dimension 50
|
|
uid 179,0
|
|
)
|
|
*72 (MRCItem
|
|
litem &56
|
|
pos 2
|
|
dimension 100
|
|
uid 180,0
|
|
)
|
|
*73 (MRCItem
|
|
litem &57
|
|
pos 3
|
|
dimension 100
|
|
uid 181,0
|
|
)
|
|
*74 (MRCItem
|
|
litem &58
|
|
pos 4
|
|
dimension 50
|
|
uid 182,0
|
|
)
|
|
*75 (MRCItem
|
|
litem &59
|
|
pos 5
|
|
dimension 50
|
|
uid 183,0
|
|
)
|
|
*76 (MRCItem
|
|
litem &60
|
|
pos 6
|
|
dimension 80
|
|
uid 184,0
|
|
)
|
|
]
|
|
)
|
|
fixedCol 3
|
|
fixedRow 2
|
|
name "Ports"
|
|
uid 172,0
|
|
vaOverrides [
|
|
]
|
|
)
|
|
]
|
|
)
|
|
uid 158,0
|
|
type 1
|
|
)
|
|
VExpander (VariableExpander
|
|
vvMap [
|
|
(vvPair
|
|
variable "HDLDir"
|
|
value "C:\\dev\\sem-labs\\06-07-08-09-SystemOnChip\\Prefs\\..\\AhbLiteComponents_test\\hdl"
|
|
)
|
|
(vvPair
|
|
variable "HDSDir"
|
|
value "C:\\dev\\sem-labs\\06-07-08-09-SystemOnChip\\Prefs\\..\\AhbLiteComponents_test\\hds"
|
|
)
|
|
(vvPair
|
|
variable "SideDataDesignDir"
|
|
value "C:\\dev\\sem-labs\\06-07-08-09-SystemOnChip\\Prefs\\..\\AhbLiteComponents_test\\hds\\ahb@gpio_tester\\interface.info"
|
|
)
|
|
(vvPair
|
|
variable "SideDataUserDir"
|
|
value "C:\\dev\\sem-labs\\06-07-08-09-SystemOnChip\\Prefs\\..\\AhbLiteComponents_test\\hds\\ahb@gpio_tester\\interface.user"
|
|
)
|
|
(vvPair
|
|
variable "SourceDir"
|
|
value "C:\\dev\\sem-labs\\06-07-08-09-SystemOnChip\\Prefs\\..\\AhbLiteComponents_test\\hds"
|
|
)
|
|
(vvPair
|
|
variable "appl"
|
|
value "HDL Designer"
|
|
)
|
|
(vvPair
|
|
variable "arch_name"
|
|
value "interface"
|
|
)
|
|
(vvPair
|
|
variable "asm_file"
|
|
value "beamer.asm"
|
|
)
|
|
(vvPair
|
|
variable "concat_file"
|
|
value "concatenated"
|
|
)
|
|
(vvPair
|
|
variable "config"
|
|
value "%(unit)_%(view)_config"
|
|
)
|
|
(vvPair
|
|
variable "d"
|
|
value "C:\\dev\\sem-labs\\06-07-08-09-SystemOnChip\\Prefs\\..\\AhbLiteComponents_test\\hds\\ahb@gpio_tester"
|
|
)
|
|
(vvPair
|
|
variable "d_logical"
|
|
value "C:\\dev\\sem-labs\\06-07-08-09-SystemOnChip\\Prefs\\..\\AhbLiteComponents_test\\hds\\ahbGpio_tester"
|
|
)
|
|
(vvPair
|
|
variable "date"
|
|
value "28.04.2023"
|
|
)
|
|
(vvPair
|
|
variable "day"
|
|
value "ven."
|
|
)
|
|
(vvPair
|
|
variable "day_long"
|
|
value "vendredi"
|
|
)
|
|
(vvPair
|
|
variable "dd"
|
|
value "28"
|
|
)
|
|
(vvPair
|
|
variable "designName"
|
|
value "$DESIGN_NAME"
|
|
)
|
|
(vvPair
|
|
variable "entity_name"
|
|
value "ahbGpio_tester"
|
|
)
|
|
(vvPair
|
|
variable "ext"
|
|
value "<TBD>"
|
|
)
|
|
(vvPair
|
|
variable "f"
|
|
value "interface"
|
|
)
|
|
(vvPair
|
|
variable "f_logical"
|
|
value "interface"
|
|
)
|
|
(vvPair
|
|
variable "f_noext"
|
|
value "interface"
|
|
)
|
|
(vvPair
|
|
variable "graphical_source_author"
|
|
value "axel.amand"
|
|
)
|
|
(vvPair
|
|
variable "graphical_source_date"
|
|
value "28.04.2023"
|
|
)
|
|
(vvPair
|
|
variable "graphical_source_group"
|
|
value "UNKNOWN"
|
|
)
|
|
(vvPair
|
|
variable "graphical_source_host"
|
|
value "WE7860"
|
|
)
|
|
(vvPair
|
|
variable "graphical_source_time"
|
|
value "14:51:40"
|
|
)
|
|
(vvPair
|
|
variable "group"
|
|
value "UNKNOWN"
|
|
)
|
|
(vvPair
|
|
variable "host"
|
|
value "WE7860"
|
|
)
|
|
(vvPair
|
|
variable "language"
|
|
value "VHDL"
|
|
)
|
|
(vvPair
|
|
variable "library"
|
|
value "AhbLiteComponents_test"
|
|
)
|
|
(vvPair
|
|
variable "library_downstream_ModelSimCompiler"
|
|
value "$SCRATCH_DIR/AhbLiteComponents_test"
|
|
)
|
|
(vvPair
|
|
variable "mm"
|
|
value "04"
|
|
)
|
|
(vvPair
|
|
variable "module_name"
|
|
value "ahbGpio_tester"
|
|
)
|
|
(vvPair
|
|
variable "month"
|
|
value "avr."
|
|
)
|
|
(vvPair
|
|
variable "month_long"
|
|
value "avril"
|
|
)
|
|
(vvPair
|
|
variable "p"
|
|
value "C:\\dev\\sem-labs\\06-07-08-09-SystemOnChip\\Prefs\\..\\AhbLiteComponents_test\\hds\\ahb@gpio_tester\\interface"
|
|
)
|
|
(vvPair
|
|
variable "p_logical"
|
|
value "C:\\dev\\sem-labs\\06-07-08-09-SystemOnChip\\Prefs\\..\\AhbLiteComponents_test\\hds\\ahbGpio_tester\\interface"
|
|
)
|
|
(vvPair
|
|
variable "package_name"
|
|
value "<Undefined Variable>"
|
|
)
|
|
(vvPair
|
|
variable "project_name"
|
|
value "hds"
|
|
)
|
|
(vvPair
|
|
variable "series"
|
|
value "HDL Designer Series"
|
|
)
|
|
(vvPair
|
|
variable "task_AsmPath"
|
|
value "$HDS_LIBS_DIR\\NanoBlaze\\hdl"
|
|
)
|
|
(vvPair
|
|
variable "task_HDSPath"
|
|
value "$HDS_HOME"
|
|
)
|
|
(vvPair
|
|
variable "task_ISEBinPath"
|
|
value "$ISE_HOME"
|
|
)
|
|
(vvPair
|
|
variable "task_ISEPath"
|
|
value "$ISE_SCRATCH_WORK_DIR"
|
|
)
|
|
(vvPair
|
|
variable "task_ModelSimPath"
|
|
value "$MODELSIM_HOME\\win32"
|
|
)
|
|
(vvPair
|
|
variable "this_ext"
|
|
value "<TBD>"
|
|
)
|
|
(vvPair
|
|
variable "this_file"
|
|
value "interface"
|
|
)
|
|
(vvPair
|
|
variable "this_file_logical"
|
|
value "interface"
|
|
)
|
|
(vvPair
|
|
variable "time"
|
|
value "14:51:40"
|
|
)
|
|
(vvPair
|
|
variable "unit"
|
|
value "ahbGpio_tester"
|
|
)
|
|
(vvPair
|
|
variable "user"
|
|
value "axel.amand"
|
|
)
|
|
(vvPair
|
|
variable "version"
|
|
value "2019.2 (Build 5)"
|
|
)
|
|
(vvPair
|
|
variable "view"
|
|
value "interface"
|
|
)
|
|
(vvPair
|
|
variable "year"
|
|
value "2023"
|
|
)
|
|
(vvPair
|
|
variable "yy"
|
|
value "23"
|
|
)
|
|
]
|
|
)
|
|
LanguageMgr "VhdlLangMgr"
|
|
uid 128,0
|
|
optionalChildren [
|
|
*77 (SymbolBody
|
|
uid 8,0
|
|
optionalChildren [
|
|
*78 (CptPort
|
|
uid 658,0
|
|
ps "OnEdgeStrategy"
|
|
shape (Triangle
|
|
uid 659,0
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "0,65535,0"
|
|
)
|
|
xt "22625,5250,23375,6000"
|
|
)
|
|
tg (CPTG
|
|
uid 660,0
|
|
ps "CptPortTextPlaceStrategy"
|
|
stg "RightVerticalLayoutStrategy"
|
|
f (Text
|
|
uid 661,0
|
|
ro 270
|
|
va (VaSet
|
|
font "Verdana,12,0"
|
|
)
|
|
xt "22300,7000,23700,11500"
|
|
st "hAddr"
|
|
ju 2
|
|
blo "23500,7000"
|
|
tm "CptPortNameMgr"
|
|
)
|
|
)
|
|
dt (MLText
|
|
uid 662,0
|
|
va (VaSet
|
|
font "Courier New,8,0"
|
|
)
|
|
xt "44000,4400,75500,5200"
|
|
st "hAddr : OUT unsigned ( ahbAddressBitNb-1 DOWNTO 0 ) ;
|
|
"
|
|
)
|
|
thePort (LogicalPort
|
|
m 1
|
|
decl (Decl
|
|
n "hAddr"
|
|
t "unsigned"
|
|
b "( ahbAddressBitNb-1 DOWNTO 0 )"
|
|
o 1
|
|
suid 56,0
|
|
)
|
|
)
|
|
)
|
|
*79 (CptPort
|
|
uid 663,0
|
|
ps "OnEdgeStrategy"
|
|
shape (Triangle
|
|
uid 664,0
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "0,65535,0"
|
|
)
|
|
xt "40625,5250,41375,6000"
|
|
)
|
|
tg (CPTG
|
|
uid 665,0
|
|
ps "CptPortTextPlaceStrategy"
|
|
stg "RightVerticalLayoutStrategy"
|
|
f (Text
|
|
uid 666,0
|
|
ro 270
|
|
va (VaSet
|
|
font "Verdana,12,0"
|
|
)
|
|
xt "40300,7000,41700,10500"
|
|
st "hClk"
|
|
ju 2
|
|
blo "41500,7000"
|
|
tm "CptPortNameMgr"
|
|
)
|
|
)
|
|
dt (MLText
|
|
uid 667,0
|
|
va (VaSet
|
|
font "Courier New,8,0"
|
|
)
|
|
xt "44000,5200,61000,6000"
|
|
st "hClk : OUT std_uLogic ;
|
|
"
|
|
)
|
|
thePort (LogicalPort
|
|
m 1
|
|
decl (Decl
|
|
n "hClk"
|
|
t "std_uLogic"
|
|
o 2
|
|
suid 57,0
|
|
)
|
|
)
|
|
)
|
|
*80 (CptPort
|
|
uid 668,0
|
|
ps "OnEdgeStrategy"
|
|
shape (Triangle
|
|
uid 669,0
|
|
ro 180
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "0,65535,0"
|
|
)
|
|
xt "32625,5250,33375,6000"
|
|
)
|
|
tg (CPTG
|
|
uid 670,0
|
|
ps "CptPortTextPlaceStrategy"
|
|
stg "RightVerticalLayoutStrategy"
|
|
f (Text
|
|
uid 671,0
|
|
ro 270
|
|
va (VaSet
|
|
font "Verdana,12,0"
|
|
)
|
|
xt "32300,7000,33700,12400"
|
|
st "hRData"
|
|
ju 2
|
|
blo "33500,7000"
|
|
tm "CptPortNameMgr"
|
|
)
|
|
)
|
|
dt (MLText
|
|
uid 672,0
|
|
va (VaSet
|
|
font "Courier New,8,0"
|
|
)
|
|
xt "44000,2000,77500,2800"
|
|
st "hRData : IN std_ulogic_vector (ahbDataBitNb-1 DOWNTO 0) ;
|
|
"
|
|
)
|
|
thePort (LogicalPort
|
|
decl (Decl
|
|
n "hRData"
|
|
t "std_ulogic_vector"
|
|
b "(ahbDataBitNb-1 DOWNTO 0)"
|
|
o 3
|
|
suid 58,0
|
|
)
|
|
)
|
|
)
|
|
*81 (CptPort
|
|
uid 673,0
|
|
ps "OnEdgeStrategy"
|
|
shape (Triangle
|
|
uid 674,0
|
|
ro 180
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "0,65535,0"
|
|
)
|
|
xt "34625,5250,35375,6000"
|
|
)
|
|
tg (CPTG
|
|
uid 675,0
|
|
ps "CptPortTextPlaceStrategy"
|
|
stg "RightVerticalLayoutStrategy"
|
|
f (Text
|
|
uid 676,0
|
|
ro 270
|
|
va (VaSet
|
|
font "Verdana,12,0"
|
|
)
|
|
xt "34300,7000,35700,12500"
|
|
st "hReady"
|
|
ju 2
|
|
blo "35500,7000"
|
|
tm "CptPortNameMgr"
|
|
)
|
|
)
|
|
dt (MLText
|
|
uid 677,0
|
|
va (VaSet
|
|
font "Courier New,8,0"
|
|
)
|
|
xt "44000,2800,61000,3600"
|
|
st "hReady : IN std_uLogic ;
|
|
"
|
|
)
|
|
thePort (LogicalPort
|
|
decl (Decl
|
|
n "hReady"
|
|
t "std_uLogic"
|
|
o 4
|
|
suid 59,0
|
|
)
|
|
)
|
|
)
|
|
*82 (CptPort
|
|
uid 678,0
|
|
ps "OnEdgeStrategy"
|
|
shape (Triangle
|
|
uid 679,0
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "0,65535,0"
|
|
)
|
|
xt "42625,5250,43375,6000"
|
|
)
|
|
tg (CPTG
|
|
uid 680,0
|
|
ps "CptPortTextPlaceStrategy"
|
|
stg "RightVerticalLayoutStrategy"
|
|
f (Text
|
|
uid 681,0
|
|
ro 270
|
|
va (VaSet
|
|
font "Verdana,12,0"
|
|
)
|
|
xt "42300,7000,43700,13800"
|
|
st "hReset_n"
|
|
ju 2
|
|
blo "43500,7000"
|
|
tm "CptPortNameMgr"
|
|
)
|
|
)
|
|
dt (MLText
|
|
uid 682,0
|
|
va (VaSet
|
|
font "Courier New,8,0"
|
|
)
|
|
xt "44000,6000,61000,6800"
|
|
st "hReset_n : OUT std_uLogic ;
|
|
"
|
|
)
|
|
thePort (LogicalPort
|
|
m 1
|
|
decl (Decl
|
|
n "hReset_n"
|
|
t "std_uLogic"
|
|
o 5
|
|
suid 60,0
|
|
)
|
|
)
|
|
)
|
|
*83 (CptPort
|
|
uid 683,0
|
|
ps "OnEdgeStrategy"
|
|
shape (Triangle
|
|
uid 684,0
|
|
ro 180
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "0,65535,0"
|
|
)
|
|
xt "36625,5250,37375,6000"
|
|
)
|
|
tg (CPTG
|
|
uid 685,0
|
|
ps "CptPortTextPlaceStrategy"
|
|
stg "RightVerticalLayoutStrategy"
|
|
f (Text
|
|
uid 686,0
|
|
ro 270
|
|
va (VaSet
|
|
font "Verdana,12,0"
|
|
)
|
|
xt "36300,7000,37700,11700"
|
|
st "hResp"
|
|
ju 2
|
|
blo "37500,7000"
|
|
tm "CptPortNameMgr"
|
|
)
|
|
)
|
|
dt (MLText
|
|
uid 687,0
|
|
va (VaSet
|
|
font "Courier New,8,0"
|
|
)
|
|
xt "44000,3600,61000,4400"
|
|
st "hResp : IN std_uLogic ;
|
|
"
|
|
)
|
|
thePort (LogicalPort
|
|
decl (Decl
|
|
n "hResp"
|
|
t "std_uLogic"
|
|
o 6
|
|
suid 61,0
|
|
)
|
|
)
|
|
)
|
|
*84 (CptPort
|
|
uid 688,0
|
|
ps "OnEdgeStrategy"
|
|
shape (Triangle
|
|
uid 689,0
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "0,65535,0"
|
|
)
|
|
xt "30625,5250,31375,6000"
|
|
)
|
|
tg (CPTG
|
|
uid 690,0
|
|
ps "CptPortTextPlaceStrategy"
|
|
stg "RightVerticalLayoutStrategy"
|
|
f (Text
|
|
uid 691,0
|
|
ro 270
|
|
va (VaSet
|
|
font "Verdana,12,0"
|
|
)
|
|
xt "30300,7000,31700,10500"
|
|
st "hSel"
|
|
ju 2
|
|
blo "31500,7000"
|
|
tm "CptPortNameMgr"
|
|
)
|
|
)
|
|
dt (MLText
|
|
uid 692,0
|
|
va (VaSet
|
|
font "Courier New,8,0"
|
|
)
|
|
xt "44000,6800,61000,7600"
|
|
st "hSel : OUT std_uLogic ;
|
|
"
|
|
)
|
|
thePort (LogicalPort
|
|
m 1
|
|
decl (Decl
|
|
n "hSel"
|
|
t "std_uLogic"
|
|
o 7
|
|
suid 62,0
|
|
)
|
|
)
|
|
)
|
|
*85 (CptPort
|
|
uid 693,0
|
|
ps "OnEdgeStrategy"
|
|
shape (Triangle
|
|
uid 694,0
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "0,65535,0"
|
|
)
|
|
xt "26625,5250,27375,6000"
|
|
)
|
|
tg (CPTG
|
|
uid 695,0
|
|
ps "CptPortTextPlaceStrategy"
|
|
stg "RightVerticalLayoutStrategy"
|
|
f (Text
|
|
uid 696,0
|
|
ro 270
|
|
va (VaSet
|
|
font "Verdana,12,0"
|
|
)
|
|
xt "26300,7000,27700,12100"
|
|
st "hTrans"
|
|
ju 2
|
|
blo "27500,7000"
|
|
tm "CptPortNameMgr"
|
|
)
|
|
)
|
|
dt (MLText
|
|
uid 697,0
|
|
va (VaSet
|
|
font "Courier New,8,0"
|
|
)
|
|
xt "44000,7600,78000,8400"
|
|
st "hTrans : OUT std_ulogic_vector (ahbTransBitNb-1 DOWNTO 0) ;
|
|
"
|
|
)
|
|
thePort (LogicalPort
|
|
m 1
|
|
decl (Decl
|
|
n "hTrans"
|
|
t "std_ulogic_vector"
|
|
b "(ahbTransBitNb-1 DOWNTO 0)"
|
|
o 8
|
|
suid 63,0
|
|
)
|
|
)
|
|
)
|
|
*86 (CptPort
|
|
uid 698,0
|
|
ps "OnEdgeStrategy"
|
|
shape (Triangle
|
|
uid 699,0
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "0,65535,0"
|
|
)
|
|
xt "24625,5250,25375,6000"
|
|
)
|
|
tg (CPTG
|
|
uid 700,0
|
|
ps "CptPortTextPlaceStrategy"
|
|
stg "RightVerticalLayoutStrategy"
|
|
f (Text
|
|
uid 701,0
|
|
ro 270
|
|
va (VaSet
|
|
font "Verdana,12,0"
|
|
)
|
|
xt "24300,7000,25700,12900"
|
|
st "hWData"
|
|
ju 2
|
|
blo "25500,7000"
|
|
tm "CptPortNameMgr"
|
|
)
|
|
)
|
|
dt (MLText
|
|
uid 702,0
|
|
va (VaSet
|
|
font "Courier New,8,0"
|
|
)
|
|
xt "44000,8400,77500,9200"
|
|
st "hWData : OUT std_ulogic_vector (ahbDataBitNb-1 DOWNTO 0) ;
|
|
"
|
|
)
|
|
thePort (LogicalPort
|
|
m 1
|
|
decl (Decl
|
|
n "hWData"
|
|
t "std_ulogic_vector"
|
|
b "(ahbDataBitNb-1 DOWNTO 0)"
|
|
o 9
|
|
suid 64,0
|
|
)
|
|
)
|
|
)
|
|
*87 (CptPort
|
|
uid 703,0
|
|
ps "OnEdgeStrategy"
|
|
shape (Triangle
|
|
uid 704,0
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "0,65535,0"
|
|
)
|
|
xt "28625,5250,29375,6000"
|
|
)
|
|
tg (CPTG
|
|
uid 705,0
|
|
ps "CptPortTextPlaceStrategy"
|
|
stg "RightVerticalLayoutStrategy"
|
|
f (Text
|
|
uid 706,0
|
|
ro 270
|
|
va (VaSet
|
|
font "Verdana,12,0"
|
|
)
|
|
xt "28300,7000,29700,12000"
|
|
st "hWrite"
|
|
ju 2
|
|
blo "29500,7000"
|
|
tm "CptPortNameMgr"
|
|
)
|
|
)
|
|
dt (MLText
|
|
uid 707,0
|
|
va (VaSet
|
|
font "Courier New,8,0"
|
|
)
|
|
xt "44000,9200,61000,10000"
|
|
st "hWrite : OUT std_uLogic ;
|
|
"
|
|
)
|
|
thePort (LogicalPort
|
|
m 1
|
|
decl (Decl
|
|
n "hWrite"
|
|
t "std_uLogic"
|
|
o 10
|
|
suid 65,0
|
|
)
|
|
)
|
|
)
|
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|
)
|
|
tg (CPTG
|
|
ps "CptPortTextPlaceStrategy"
|
|
stg "VerticalLayoutStrategy"
|
|
f (Text
|
|
va (VaSet
|
|
)
|
|
xt "0,750,1400,1750"
|
|
st "In0"
|
|
blo "0,1550"
|
|
tm "CptPortNameMgr"
|
|
)
|
|
)
|
|
dt (MLText
|
|
va (VaSet
|
|
font "Courier New,8,0"
|
|
)
|
|
)
|
|
thePort (LogicalPort
|
|
decl (Decl
|
|
n "In0"
|
|
t "std_logic_vector"
|
|
b "(15 DOWNTO 0)"
|
|
o 0
|
|
)
|
|
)
|
|
)
|
|
defaultCptPortBuffer (CptPort
|
|
ps "OnEdgeStrategy"
|
|
shape (Diamond
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "65535,65535,65535"
|
|
bg "0,0,0"
|
|
)
|
|
xt "0,0,750,750"
|
|
)
|
|
tg (CPTG
|
|
ps "CptPortTextPlaceStrategy"
|
|
stg "VerticalLayoutStrategy"
|
|
f (Text
|
|
va (VaSet
|
|
)
|
|
xt "0,750,2800,1750"
|
|
st "Buffer0"
|
|
blo "0,1550"
|
|
tm "CptPortNameMgr"
|
|
)
|
|
)
|
|
dt (MLText
|
|
va (VaSet
|
|
font "Courier New,8,0"
|
|
)
|
|
)
|
|
thePort (LogicalPort
|
|
m 3
|
|
decl (Decl
|
|
n "Buffer0"
|
|
t "std_logic_vector"
|
|
b "(15 DOWNTO 0)"
|
|
o 0
|
|
)
|
|
)
|
|
)
|
|
DeclarativeBlock *105 (SymDeclBlock
|
|
uid 1,0
|
|
stg "SymDeclLayoutStrategy"
|
|
declLabel (Text
|
|
uid 2,0
|
|
va (VaSet
|
|
font "Arial,8,1"
|
|
)
|
|
xt "42000,0,47400,1000"
|
|
st "Declarations"
|
|
blo "42000,800"
|
|
)
|
|
portLabel (Text
|
|
uid 3,0
|
|
va (VaSet
|
|
font "Arial,8,1"
|
|
)
|
|
xt "42000,1000,44700,2000"
|
|
st "Ports:"
|
|
blo "42000,1800"
|
|
)
|
|
externalLabel (Text
|
|
uid 4,0
|
|
va (VaSet
|
|
font "Arial,8,1"
|
|
)
|
|
xt "42000,10800,44400,11800"
|
|
st "User:"
|
|
blo "42000,11600"
|
|
)
|
|
internalLabel (Text
|
|
uid 6,0
|
|
va (VaSet
|
|
isHidden 1
|
|
font "Arial,8,1"
|
|
)
|
|
xt "42000,0,47800,1000"
|
|
st "Internal User:"
|
|
blo "42000,800"
|
|
)
|
|
externalText (MLText
|
|
uid 5,0
|
|
va (VaSet
|
|
font "Courier New,8,0"
|
|
)
|
|
xt "44000,11800,44000,11800"
|
|
tm "SyDeclarativeTextMgr"
|
|
)
|
|
internalText (MLText
|
|
uid 7,0
|
|
va (VaSet
|
|
isHidden 1
|
|
font "Courier New,8,0"
|
|
)
|
|
xt "42000,0,42000,0"
|
|
tm "SyDeclarativeTextMgr"
|
|
)
|
|
)
|
|
lastUid 734,0
|
|
activeModelName "Symbol:GEN"
|
|
)
|