8 lines
219 B
VHDL
8 lines
219 B
VHDL
ARCHITECTURE studentVersion OF interpolatorShiftRegister IS
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BEGIN
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sample1 <= (others => '0');
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sample2 <= (others => '0');
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sample3 <= (others => '0');
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sample4 <= (others => '0');
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END ARCHITECTURE studentVersion;
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