Archived
1
0
This repository has been archived on 2025-05-03. You can view files and clone it, but cannot push or open issues or pull requests.
Files
SEm-Labos/05-Morse/Board/hdl/DFF_sim.vhd
github-classroom[bot] d212040c30 Initial commit
2024-02-23 13:01:05 +00:00

15 lines
197 B
VHDL

ARCHITECTURE sim OF DFF IS
BEGIN
process(clk, clr)
begin
if clr = '1' then
q <= '0';
elsif rising_edge(clk) then
q <= d;
end if;
end process;
END ARCHITECTURE sim;