47 lines
1.5 KiB
VHDL
47 lines
1.5 KiB
VHDL
ARCHITECTURE studentVersion OF sineTable IS
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signal phaseTableAddress : unsigned(tableAddressBitNb-1 downto 0);
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signal phaseTableAddress2 : unsigned(tableAddressBitNb-1 downto 0);
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signal quarterSine : signed(sine'range);
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BEGIN
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phaseTableAddress <= phase(phase'high-2 downto phase'high-2-tableAddressBitNb+1);
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sequenceTable: process(phase)
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begin
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if phase(phase'high-1) = '1' then
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phaseTableAddress2 <= 8 - phaseTableAddress;
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else
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phaseTableAddress2 <= phaseTableAddress;
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end if;
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end process sequenceTable;
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quarterTable: process(phaseTableAddress2)
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begin
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case to_integer(phaseTableAddress2) is
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when 0 => quarterSine <= to_signed(16#0000#, quarterSine'length);
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when 1 => quarterSine <= to_signed(16#18F9#, quarterSine'length);
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when 2 => quarterSine <= to_signed(16#30FB#, quarterSine'length);
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when 3 => quarterSine <= to_signed(16#471C#, quarterSine'length);
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when 4 => quarterSine <= to_signed(16#5A82#, quarterSine'length);
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when 5 => quarterSine <= to_signed(16#6A6D#, quarterSine'length);
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when 6 => quarterSine <= to_signed(16#7641#, quarterSine'length);
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when 7 => quarterSine <= to_signed(16#7D89#, quarterSine'length);
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when others => quarterSine <= (others => '-');
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end case;
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end process quarterTable;
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invert: process(quarterSine)
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begin
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if phase(phase'high) = '1' then
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sine <= NOT quarterSine;
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else
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sine <= quarterSine;
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end if;
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end process invert;
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--sine <= quarterSine;
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END ARCHITECTURE studentVersion;
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