1505 lines
18 KiB
Plaintext
1505 lines
18 KiB
Plaintext
DocumentHdrVersion "1.1"
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Header (DocumentHdr
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version 2
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dialect 11
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dmPackageRefs [
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(DmPackageRef
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library "ieee"
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unitName "std_logic_1164"
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)
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(DmPackageRef
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library "ieee"
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unitName "numeric_std"
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)
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]
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libraryRefs [
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"ieee"
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]
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)
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version "26.1"
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appVersion "2018.1 (Build 12)"
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model (Symbol
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commonDM (CommonDM
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ldm (LogicalDM
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suid 32,0
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usingSuid 1
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emptyRow *1 (LEmptyRow
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)
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uid 77,0
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optionalChildren [
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*2 (RefLabelRowHdr
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*3 (TitleRowHdr
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)
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*4 (FilterRowHdr
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)
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*5 (RefLabelColHdr
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tm "RefLabelColHdrMgr"
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)
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*6 (RowExpandColHdr
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tm "RowExpandColHdrMgr"
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)
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*7 (GroupColHdr
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tm "GroupColHdrMgr"
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)
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*8 (NameColHdr
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tm "NameColHdrMgr"
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)
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*9 (ModeColHdr
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tm "ModeColHdrMgr"
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)
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*10 (TypeColHdr
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tm "TypeColHdrMgr"
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)
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*11 (BoundsColHdr
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tm "BoundsColHdrMgr"
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)
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*12 (InitColHdr
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tm "InitColHdrMgr"
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)
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*13 (EolColHdr
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tm "EolColHdrMgr"
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)
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*14 (LogPort
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port (LogicalPort
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m 1
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decl (Decl
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n "clock"
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t "std_ulogic"
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o 1
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suid 25,0
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)
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)
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uid 403,0
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)
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*15 (LogPort
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port (LogicalPort
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m 1
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decl (Decl
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n "dataIn"
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t "std_ulogic_vector"
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b "(dataBitNb-1 DOWNTO 0)"
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o 2
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suid 26,0
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)
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)
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uid 405,0
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)
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*16 (LogPort
|
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port (LogicalPort
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decl (Decl
|
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n "dataOut"
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t "std_ulogic_vector"
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b "(dataBitNb-1 DOWNTO 0)"
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o 3
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suid 27,0
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)
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)
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uid 407,0
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)
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*17 (LogPort
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port (LogicalPort
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decl (Decl
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n "empty"
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t "std_ulogic"
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o 4
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suid 28,0
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)
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)
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uid 409,0
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)
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*18 (LogPort
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port (LogicalPort
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decl (Decl
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n "full"
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t "std_ulogic"
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o 5
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suid 29,0
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)
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)
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uid 411,0
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)
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*19 (LogPort
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port (LogicalPort
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m 1
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decl (Decl
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n "read"
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t "std_ulogic"
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o 6
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suid 30,0
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)
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)
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uid 413,0
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)
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*20 (LogPort
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port (LogicalPort
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m 1
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decl (Decl
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n "reset"
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t "std_ulogic"
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o 7
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suid 31,0
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)
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)
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uid 415,0
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)
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*21 (LogPort
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port (LogicalPort
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m 1
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decl (Decl
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n "write"
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t "std_ulogic"
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o 8
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suid 32,0
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)
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)
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uid 417,0
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)
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]
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)
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pdm (PhysicalDM
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displayShortBounds 1
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editShortBounds 1
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uid 90,0
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optionalChildren [
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*22 (Sheet
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sheetRow (SheetRow
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headerVa (MVa
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cellColor "49152,49152,49152"
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fontColor "0,0,0"
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font "courier,10,0"
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)
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cellVa (MVa
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cellColor "65535,65535,65535"
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fontColor "0,0,0"
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font "courier,10,0"
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)
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groupVa (MVa
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cellColor "39936,56832,65280"
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fontColor "0,0,0"
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font "courier,10,0"
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)
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emptyMRCItem *23 (MRCItem
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litem &1
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pos 8
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dimension 20
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)
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uid 92,0
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optionalChildren [
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*24 (MRCItem
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litem &2
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pos 0
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dimension 20
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uid 93,0
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)
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*25 (MRCItem
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litem &3
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pos 1
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dimension 23
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uid 94,0
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)
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*26 (MRCItem
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litem &4
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pos 2
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hidden 1
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dimension 20
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uid 95,0
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)
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*27 (MRCItem
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litem &14
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pos 0
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dimension 20
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uid 404,0
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)
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*28 (MRCItem
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litem &15
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pos 1
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dimension 20
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uid 406,0
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)
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*29 (MRCItem
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litem &16
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pos 2
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dimension 20
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uid 408,0
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)
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*30 (MRCItem
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litem &17
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pos 3
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dimension 20
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uid 410,0
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)
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*31 (MRCItem
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litem &18
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pos 4
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dimension 20
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uid 412,0
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)
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*32 (MRCItem
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litem &19
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pos 5
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dimension 20
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uid 414,0
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)
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*33 (MRCItem
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litem &20
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pos 6
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dimension 20
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uid 416,0
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)
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*34 (MRCItem
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litem &21
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pos 7
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dimension 20
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uid 418,0
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)
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]
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)
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sheetCol (SheetCol
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propVa (MVa
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cellColor "0,49152,49152"
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fontColor "0,0,0"
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font "courier,10,0"
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textAngle 90
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)
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uid 96,0
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optionalChildren [
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*35 (MRCItem
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litem &5
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pos 0
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dimension 20
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uid 97,0
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)
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*36 (MRCItem
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litem &7
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pos 1
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dimension 50
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uid 98,0
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)
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*37 (MRCItem
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litem &8
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pos 2
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dimension 100
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uid 99,0
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)
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*38 (MRCItem
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litem &9
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pos 3
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dimension 50
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uid 100,0
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)
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*39 (MRCItem
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litem &10
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pos 4
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dimension 100
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|
uid 101,0
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)
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*40 (MRCItem
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litem &11
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pos 5
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dimension 100
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uid 102,0
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)
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*41 (MRCItem
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litem &12
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pos 6
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dimension 50
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uid 103,0
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)
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*42 (MRCItem
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litem &13
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pos 7
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dimension 80
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uid 104,0
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)
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]
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)
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fixedCol 4
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fixedRow 2
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name "Ports"
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uid 91,0
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vaOverrides [
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]
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)
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]
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)
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uid 76,0
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)
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genericsCommonDM (CommonDM
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ldm (LogicalDM
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emptyRow *43 (LEmptyRow
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)
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uid 106,0
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optionalChildren [
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*44 (RefLabelRowHdr
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)
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*45 (TitleRowHdr
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)
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*46 (FilterRowHdr
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)
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*47 (RefLabelColHdr
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tm "RefLabelColHdrMgr"
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)
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*48 (RowExpandColHdr
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tm "RowExpandColHdrMgr"
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)
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*49 (GroupColHdr
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tm "GroupColHdrMgr"
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)
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*50 (NameColHdr
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tm "GenericNameColHdrMgr"
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)
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*51 (TypeColHdr
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tm "GenericTypeColHdrMgr"
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)
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*52 (InitColHdr
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tm "GenericValueColHdrMgr"
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)
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*53 (PragmaColHdr
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tm "GenericPragmaColHdrMgr"
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)
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*54 (EolColHdr
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tm "GenericEolColHdrMgr"
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)
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*55 (LogGeneric
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generic (GiElement
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name "dataBitNb"
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type "positive"
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value "8"
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)
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uid 155,0
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)
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*56 (LogGeneric
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generic (GiElement
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name "fifoDepth"
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type "positive"
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value "64"
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)
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uid 157,0
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)
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]
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)
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pdm (PhysicalDM
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displayShortBounds 1
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editShortBounds 1
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uid 118,0
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optionalChildren [
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*57 (Sheet
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sheetRow (SheetRow
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headerVa (MVa
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cellColor "49152,49152,49152"
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fontColor "0,0,0"
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font "courier,10,0"
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)
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cellVa (MVa
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cellColor "65535,65535,65535"
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fontColor "0,0,0"
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font "courier,10,0"
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)
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groupVa (MVa
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cellColor "39936,56832,65280"
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fontColor "0,0,0"
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font "courier,10,0"
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)
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emptyMRCItem *58 (MRCItem
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litem &43
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pos 2
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dimension 20
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)
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uid 120,0
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optionalChildren [
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*59 (MRCItem
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litem &44
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pos 0
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dimension 20
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uid 121,0
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)
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*60 (MRCItem
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litem &45
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pos 1
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dimension 23
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uid 122,0
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)
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*61 (MRCItem
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litem &46
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pos 2
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hidden 1
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dimension 20
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uid 123,0
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)
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*62 (MRCItem
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litem &55
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pos 0
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dimension 20
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uid 156,0
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)
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*63 (MRCItem
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litem &56
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pos 1
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dimension 20
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uid 158,0
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)
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]
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)
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sheetCol (SheetCol
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propVa (MVa
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cellColor "0,49152,49152"
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fontColor "0,0,0"
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font "courier,10,0"
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textAngle 90
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)
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uid 124,0
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optionalChildren [
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*64 (MRCItem
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litem &47
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pos 0
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dimension 20
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uid 125,0
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)
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*65 (MRCItem
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litem &49
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pos 1
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dimension 50
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uid 126,0
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)
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*66 (MRCItem
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litem &50
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pos 2
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dimension 100
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uid 127,0
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)
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*67 (MRCItem
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litem &51
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pos 3
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dimension 100
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uid 128,0
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)
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*68 (MRCItem
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litem &52
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pos 4
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dimension 50
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uid 129,0
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)
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*69 (MRCItem
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litem &53
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pos 5
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dimension 50
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uid 130,0
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)
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*70 (MRCItem
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litem &54
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pos 6
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dimension 80
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uid 131,0
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)
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]
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)
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fixedCol 3
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fixedRow 2
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name "Ports"
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uid 119,0
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vaOverrides [
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]
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)
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]
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)
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uid 105,0
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type 1
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)
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VExpander (VariableExpander
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vvMap [
|
|
(vvPair
|
|
variable " "
|
|
value " "
|
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)
|
|
(vvPair
|
|
variable "HDLDir"
|
|
value "/home/francois/Documents/HEVs/Kart/eln_kart/04-Controller/../Libs/Memory_test/hdl"
|
|
)
|
|
(vvPair
|
|
variable "HDSDir"
|
|
value "/home/francois/Documents/HEVs/Kart/eln_kart/04-Controller/../Libs/Memory_test/hds"
|
|
)
|
|
(vvPair
|
|
variable "SideDataDesignDir"
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|
value "/home/francois/Documents/HEVs/Kart/eln_kart/04-Controller/../Libs/Memory_test/hds/fifo_tester/interface.info"
|
|
)
|
|
(vvPair
|
|
variable "SideDataUserDir"
|
|
value "/home/francois/Documents/HEVs/Kart/eln_kart/04-Controller/../Libs/Memory_test/hds/fifo_tester/interface.user"
|
|
)
|
|
(vvPair
|
|
variable "SourceDir"
|
|
value "/home/francois/Documents/HEVs/Kart/eln_kart/04-Controller/../Libs/Memory_test/hds"
|
|
)
|
|
(vvPair
|
|
variable "appl"
|
|
value "HDL Designer"
|
|
)
|
|
(vvPair
|
|
variable "arch_name"
|
|
value "interface"
|
|
)
|
|
(vvPair
|
|
variable "concat_file"
|
|
value "concatenated"
|
|
)
|
|
(vvPair
|
|
variable "config"
|
|
value "%(unit)_%(view)_config"
|
|
)
|
|
(vvPair
|
|
variable "d"
|
|
value "/home/francois/Documents/HEVs/Kart/eln_kart/04-Controller/../Libs/Memory_test/hds/fifo_tester"
|
|
)
|
|
(vvPair
|
|
variable "d_logical"
|
|
value "/home/francois/Documents/HEVs/Kart/eln_kart/04-Controller/../Libs/Memory_test/hds/fifo_tester"
|
|
)
|
|
(vvPair
|
|
variable "date"
|
|
value "08/28/19"
|
|
)
|
|
(vvPair
|
|
variable "day"
|
|
value "Wed"
|
|
)
|
|
(vvPair
|
|
variable "day_long"
|
|
value "Wednesday"
|
|
)
|
|
(vvPair
|
|
variable "dd"
|
|
value "28"
|
|
)
|
|
(vvPair
|
|
variable "designName"
|
|
value "$DESIGN_NAME"
|
|
)
|
|
(vvPair
|
|
variable "entity_name"
|
|
value "fifo_tester"
|
|
)
|
|
(vvPair
|
|
variable "ext"
|
|
value "<TBD>"
|
|
)
|
|
(vvPair
|
|
variable "f"
|
|
value "interface"
|
|
)
|
|
(vvPair
|
|
variable "f_logical"
|
|
value "interface"
|
|
)
|
|
(vvPair
|
|
variable "f_noext"
|
|
value "interface"
|
|
)
|
|
(vvPair
|
|
variable "graphical_source_author"
|
|
value "francois"
|
|
)
|
|
(vvPair
|
|
variable "graphical_source_date"
|
|
value "08/28/19"
|
|
)
|
|
(vvPair
|
|
variable "graphical_source_group"
|
|
value "francois"
|
|
)
|
|
(vvPair
|
|
variable "graphical_source_host"
|
|
value "Aphelia"
|
|
)
|
|
(vvPair
|
|
variable "graphical_source_time"
|
|
value "13:45:28"
|
|
)
|
|
(vvPair
|
|
variable "group"
|
|
value "francois"
|
|
)
|
|
(vvPair
|
|
variable "host"
|
|
value "Aphelia"
|
|
)
|
|
(vvPair
|
|
variable "language"
|
|
value "VHDL"
|
|
)
|
|
(vvPair
|
|
variable "library"
|
|
value "Memory_test"
|
|
)
|
|
(vvPair
|
|
variable "library_downstream_ModelSimCompiler"
|
|
value "$SCRATCH_DIR/Libs/Memory_test/work"
|
|
)
|
|
(vvPair
|
|
variable "mm"
|
|
value "08"
|
|
)
|
|
(vvPair
|
|
variable "module_name"
|
|
value "fifo_tester"
|
|
)
|
|
(vvPair
|
|
variable "month"
|
|
value "Aug"
|
|
)
|
|
(vvPair
|
|
variable "month_long"
|
|
value "August"
|
|
)
|
|
(vvPair
|
|
variable "p"
|
|
value "/home/francois/Documents/HEVs/Kart/eln_kart/04-Controller/../Libs/Memory_test/hds/fifo_tester/interface"
|
|
)
|
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(vvPair
|
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variable "time"
|
|
value "13:45:28"
|
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|
|
(vvPair
|
|
variable "unit"
|
|
value "fifo_tester"
|
|
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|
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|
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variable "user"
|
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value "francois"
|
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value "2018.1 (Build 12)"
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variable "view"
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