1974 lines
24 KiB
Plaintext
1974 lines
24 KiB
Plaintext
DocumentHdrVersion "1.1"
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Header (DocumentHdr
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version 2
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dialect 11
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dmPackageRefs [
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(DmPackageRef
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library "ieee"
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unitName "std_logic_1164"
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)
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(DmPackageRef
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library "ieee"
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unitName "numeric_std"
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)
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]
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libraryRefs [
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"ieee"
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]
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)
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version "26.1"
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appVersion "2018.1 (Build 12)"
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model (Symbol
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commonDM (CommonDM
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ldm (LogicalDM
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suid 48,0
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usingSuid 1
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emptyRow *1 (LEmptyRow
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)
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uid 116,0
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optionalChildren [
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*2 (RefLabelRowHdr
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)
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*3 (TitleRowHdr
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)
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*4 (FilterRowHdr
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)
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|
*5 (RefLabelColHdr
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tm "RefLabelColHdrMgr"
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)
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*6 (RowExpandColHdr
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tm "RowExpandColHdrMgr"
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)
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*7 (GroupColHdr
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tm "GroupColHdrMgr"
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)
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*8 (NameColHdr
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tm "NameColHdrMgr"
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)
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*9 (ModeColHdr
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tm "ModeColHdrMgr"
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)
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*10 (TypeColHdr
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tm "TypeColHdrMgr"
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)
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*11 (BoundsColHdr
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tm "BoundsColHdrMgr"
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)
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*12 (InitColHdr
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tm "InitColHdrMgr"
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)
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*13 (EolColHdr
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tm "EolColHdrMgr"
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)
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*14 (LogPort
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port (LogicalPort
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m 1
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decl (Decl
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n "clock"
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t "std_ulogic"
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o 5
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suid 39,0
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)
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)
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uid 566,0
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)
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*15 (LogPort
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port (LogicalPort
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m 1
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decl (Decl
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n "flashAddr"
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t "unsigned"
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b "(addressBitNb-1 DOWNTO 0)"
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o 6
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suid 40,0
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)
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)
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uid 568,0
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)
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*16 (LogPort
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port (LogicalPort
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decl (Decl
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n "flashDataIn"
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t "std_ulogic_vector"
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b "(dataBitNb-1 DOWNTO 0)"
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o 8
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suid 41,0
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)
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)
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uid 570,0
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)
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*17 (LogPort
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port (LogicalPort
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m 1
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decl (Decl
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n "flashDataOut"
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t "std_ulogic_vector"
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b "(dataBitNb-1 DOWNTO 0)"
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o 9
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suid 42,0
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)
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)
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uid 572,0
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)
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*18 (LogPort
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port (LogicalPort
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decl (Decl
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n "flashDataValid"
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t "std_ulogic"
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o 10
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suid 43,0
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)
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)
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uid 574,0
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)
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*19 (LogPort
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port (LogicalPort
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m 1
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|
decl (Decl
|
|
n "flashEn"
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t "std_ulogic"
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o 11
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suid 44,0
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)
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)
|
|
uid 576,0
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)
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|
*20 (LogPort
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port (LogicalPort
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|
m 1
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|
decl (Decl
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n "flashRd"
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t "std_ulogic"
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o 12
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suid 45,0
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)
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)
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uid 578,0
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)
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*21 (LogPort
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port (LogicalPort
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m 1
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decl (Decl
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n "flashWr"
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t "std_ulogic"
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o 14
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suid 46,0
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)
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)
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uid 580,0
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)
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*22 (LogPort
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port (LogicalPort
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m 1
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decl (Decl
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n "memBusEn_n"
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t "std_ulogic"
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o 16
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suid 47,0
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)
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)
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uid 582,0
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)
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*23 (LogPort
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port (LogicalPort
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m 1
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decl (Decl
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n "reset"
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t "std_ulogic"
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o 23
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suid 48,0
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)
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)
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uid 584,0
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)
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]
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)
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pdm (PhysicalDM
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displayShortBounds 1
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editShortBounds 1
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uid 129,0
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optionalChildren [
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*24 (Sheet
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sheetRow (SheetRow
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headerVa (MVa
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cellColor "49152,49152,49152"
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fontColor "0,0,0"
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font "courier,10,0"
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)
|
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cellVa (MVa
|
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cellColor "65535,65535,65535"
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fontColor "0,0,0"
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font "courier,10,0"
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)
|
|
groupVa (MVa
|
|
cellColor "39936,56832,65280"
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|
fontColor "0,0,0"
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font "courier,10,0"
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)
|
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emptyMRCItem *25 (MRCItem
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litem &1
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pos 9
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dimension 20
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)
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uid 131,0
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optionalChildren [
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*26 (MRCItem
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litem &2
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pos 0
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dimension 20
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uid 132,0
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)
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*27 (MRCItem
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litem &3
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pos 1
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dimension 23
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uid 133,0
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)
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*28 (MRCItem
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litem &4
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pos 2
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hidden 1
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dimension 20
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uid 134,0
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)
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*29 (MRCItem
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litem &14
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pos 0
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dimension 20
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uid 567,0
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)
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*30 (MRCItem
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litem &15
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pos 1
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dimension 20
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uid 569,0
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)
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*31 (MRCItem
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litem &16
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pos 2
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dimension 20
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uid 571,0
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)
|
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*32 (MRCItem
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litem &17
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pos 3
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dimension 20
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uid 573,0
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)
|
|
*33 (MRCItem
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litem &18
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pos 4
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dimension 20
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uid 575,0
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)
|
|
*34 (MRCItem
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litem &19
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pos 5
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dimension 20
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uid 577,0
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)
|
|
*35 (MRCItem
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litem &20
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pos 6
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dimension 20
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uid 579,0
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)
|
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*36 (MRCItem
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litem &21
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pos 7
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dimension 20
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uid 581,0
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)
|
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*37 (MRCItem
|
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litem &22
|
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pos 8
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dimension 20
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uid 583,0
|
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)
|
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*38 (MRCItem
|
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litem &23
|
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pos 9
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dimension 20
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uid 585,0
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)
|
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]
|
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)
|
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sheetCol (SheetCol
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|
propVa (MVa
|
|
cellColor "0,49152,49152"
|
|
fontColor "0,0,0"
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font "courier,10,0"
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textAngle 90
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)
|
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uid 135,0
|
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optionalChildren [
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*39 (MRCItem
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litem &5
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pos 0
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dimension 20
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uid 136,0
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)
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*40 (MRCItem
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litem &7
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pos 1
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dimension 50
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uid 137,0
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)
|
|
*41 (MRCItem
|
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litem &8
|
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pos 2
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dimension 100
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uid 138,0
|
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)
|
|
*42 (MRCItem
|
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litem &9
|
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pos 3
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dimension 50
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uid 139,0
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)
|
|
*43 (MRCItem
|
|
litem &10
|
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pos 4
|
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dimension 100
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uid 140,0
|
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)
|
|
*44 (MRCItem
|
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litem &11
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pos 5
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dimension 100
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uid 141,0
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)
|
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*45 (MRCItem
|
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litem &12
|
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pos 6
|
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dimension 50
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uid 142,0
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)
|
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*46 (MRCItem
|
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litem &13
|
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pos 7
|
|
dimension 80
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uid 143,0
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)
|
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]
|
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)
|
|
fixedCol 4
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fixedRow 2
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name "Ports"
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uid 130,0
|
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vaOverrides [
|
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]
|
|
)
|
|
]
|
|
)
|
|
uid 115,0
|
|
)
|
|
genericsCommonDM (CommonDM
|
|
ldm (LogicalDM
|
|
emptyRow *47 (LEmptyRow
|
|
)
|
|
uid 145,0
|
|
optionalChildren [
|
|
*48 (RefLabelRowHdr
|
|
)
|
|
*49 (TitleRowHdr
|
|
)
|
|
*50 (FilterRowHdr
|
|
)
|
|
*51 (RefLabelColHdr
|
|
tm "RefLabelColHdrMgr"
|
|
)
|
|
*52 (RowExpandColHdr
|
|
tm "RowExpandColHdrMgr"
|
|
)
|
|
*53 (GroupColHdr
|
|
tm "GroupColHdrMgr"
|
|
)
|
|
*54 (NameColHdr
|
|
tm "GenericNameColHdrMgr"
|
|
)
|
|
*55 (TypeColHdr
|
|
tm "GenericTypeColHdrMgr"
|
|
)
|
|
*56 (InitColHdr
|
|
tm "GenericValueColHdrMgr"
|
|
)
|
|
*57 (PragmaColHdr
|
|
tm "GenericPragmaColHdrMgr"
|
|
)
|
|
*58 (EolColHdr
|
|
tm "GenericEolColHdrMgr"
|
|
)
|
|
*59 (LogGeneric
|
|
generic (GiElement
|
|
name "addressBitNb"
|
|
type "positive"
|
|
value "24"
|
|
)
|
|
uid 280,0
|
|
)
|
|
*60 (LogGeneric
|
|
generic (GiElement
|
|
name "dataBitNb"
|
|
type "positive"
|
|
value "16"
|
|
)
|
|
uid 282,0
|
|
)
|
|
]
|
|
)
|
|
pdm (PhysicalDM
|
|
displayShortBounds 1
|
|
editShortBounds 1
|
|
uid 157,0
|
|
optionalChildren [
|
|
*61 (Sheet
|
|
sheetRow (SheetRow
|
|
headerVa (MVa
|
|
cellColor "49152,49152,49152"
|
|
fontColor "0,0,0"
|
|
font "courier,10,0"
|
|
)
|
|
cellVa (MVa
|
|
cellColor "65535,65535,65535"
|
|
fontColor "0,0,0"
|
|
font "courier,10,0"
|
|
)
|
|
groupVa (MVa
|
|
cellColor "39936,56832,65280"
|
|
fontColor "0,0,0"
|
|
font "courier,10,0"
|
|
)
|
|
emptyMRCItem *62 (MRCItem
|
|
litem &47
|
|
pos 2
|
|
dimension 20
|
|
)
|
|
uid 159,0
|
|
optionalChildren [
|
|
*63 (MRCItem
|
|
litem &48
|
|
pos 0
|
|
dimension 20
|
|
uid 160,0
|
|
)
|
|
*64 (MRCItem
|
|
litem &49
|
|
pos 1
|
|
dimension 23
|
|
uid 161,0
|
|
)
|
|
*65 (MRCItem
|
|
litem &50
|
|
pos 2
|
|
hidden 1
|
|
dimension 20
|
|
uid 162,0
|
|
)
|
|
*66 (MRCItem
|
|
litem &59
|
|
pos 0
|
|
dimension 20
|
|
uid 281,0
|
|
)
|
|
*67 (MRCItem
|
|
litem &60
|
|
pos 1
|
|
dimension 20
|
|
uid 283,0
|
|
)
|
|
]
|
|
)
|
|
sheetCol (SheetCol
|
|
propVa (MVa
|
|
cellColor "0,49152,49152"
|
|
fontColor "0,0,0"
|
|
font "courier,10,0"
|
|
textAngle 90
|
|
)
|
|
uid 163,0
|
|
optionalChildren [
|
|
*68 (MRCItem
|
|
litem &51
|
|
pos 0
|
|
dimension 20
|
|
uid 164,0
|
|
)
|
|
*69 (MRCItem
|
|
litem &53
|
|
pos 1
|
|
dimension 50
|
|
uid 165,0
|
|
)
|
|
*70 (MRCItem
|
|
litem &54
|
|
pos 2
|
|
dimension 100
|
|
uid 166,0
|
|
)
|
|
*71 (MRCItem
|
|
litem &55
|
|
pos 3
|
|
dimension 100
|
|
uid 167,0
|
|
)
|
|
*72 (MRCItem
|
|
litem &56
|
|
pos 4
|
|
dimension 50
|
|
uid 168,0
|
|
)
|
|
*73 (MRCItem
|
|
litem &57
|
|
pos 5
|
|
dimension 50
|
|
uid 169,0
|
|
)
|
|
*74 (MRCItem
|
|
litem &58
|
|
pos 6
|
|
dimension 80
|
|
uid 170,0
|
|
)
|
|
]
|
|
)
|
|
fixedCol 3
|
|
fixedRow 2
|
|
name "Ports"
|
|
uid 158,0
|
|
vaOverrides [
|
|
]
|
|
)
|
|
]
|
|
)
|
|
uid 144,0
|
|
type 1
|
|
)
|
|
VExpander (VariableExpander
|
|
vvMap [
|
|
(vvPair
|
|
variable "HDLDir"
|
|
value "/home/francois/Documents/HEVs/Kart/eln_kart/04-Controller/../Libs/Memory_test/hdl"
|
|
)
|
|
(vvPair
|
|
variable "HDSDir"
|
|
value "/home/francois/Documents/HEVs/Kart/eln_kart/04-Controller/../Libs/Memory_test/hds"
|
|
)
|
|
(vvPair
|
|
variable "SideDataDesignDir"
|
|
value "/home/francois/Documents/HEVs/Kart/eln_kart/04-Controller/../Libs/Memory_test/hds/flash@controller_tester/interface.info"
|
|
)
|
|
(vvPair
|
|
variable "SideDataUserDir"
|
|
value "/home/francois/Documents/HEVs/Kart/eln_kart/04-Controller/../Libs/Memory_test/hds/flash@controller_tester/interface.user"
|
|
)
|
|
(vvPair
|
|
variable "SourceDir"
|
|
value "/home/francois/Documents/HEVs/Kart/eln_kart/04-Controller/../Libs/Memory_test/hds"
|
|
)
|
|
(vvPair
|
|
variable "appl"
|
|
value "HDL Designer"
|
|
)
|
|
(vvPair
|
|
variable "arch_name"
|
|
value "interface"
|
|
)
|
|
(vvPair
|
|
variable "concat_file"
|
|
value "concatenated"
|
|
)
|
|
(vvPair
|
|
variable "config"
|
|
value "%(unit)_%(view)_config"
|
|
)
|
|
(vvPair
|
|
variable "d"
|
|
value "/home/francois/Documents/HEVs/Kart/eln_kart/04-Controller/../Libs/Memory_test/hds/flash@controller_tester"
|
|
)
|
|
(vvPair
|
|
variable "d_logical"
|
|
value "/home/francois/Documents/HEVs/Kart/eln_kart/04-Controller/../Libs/Memory_test/hds/flashController_tester"
|
|
)
|
|
(vvPair
|
|
variable "date"
|
|
value "08/28/19"
|
|
)
|
|
(vvPair
|
|
variable "day"
|
|
value "Wed"
|
|
)
|
|
(vvPair
|
|
variable "day_long"
|
|
value "Wednesday"
|
|
)
|
|
(vvPair
|
|
variable "dd"
|
|
value "28"
|
|
)
|
|
(vvPair
|
|
variable "entity_name"
|
|
value "flashController_tester"
|
|
)
|
|
(vvPair
|
|
variable "ext"
|
|
value "<TBD>"
|
|
)
|
|
(vvPair
|
|
variable "f"
|
|
value "interface"
|
|
)
|
|
(vvPair
|
|
variable "f_logical"
|
|
value "interface"
|
|
)
|
|
(vvPair
|
|
variable "f_noext"
|
|
value "interface"
|
|
)
|
|
(vvPair
|
|
variable "graphical_source_author"
|
|
value "francois"
|
|
)
|
|
(vvPair
|
|
variable "graphical_source_date"
|
|
value "08/28/19"
|
|
)
|
|
(vvPair
|
|
variable "graphical_source_group"
|
|
value "francois"
|
|
)
|
|
(vvPair
|
|
variable "graphical_source_host"
|
|
value "Aphelia"
|
|
)
|
|
(vvPair
|
|
variable "graphical_source_time"
|
|
value "13:45:28"
|
|
)
|
|
(vvPair
|
|
variable "group"
|
|
value "francois"
|
|
)
|
|
(vvPair
|
|
variable "host"
|
|
value "Aphelia"
|
|
)
|
|
(vvPair
|
|
variable "language"
|
|
value "VHDL"
|
|
)
|
|
(vvPair
|
|
variable "library"
|
|
value "memory_test"
|
|
)
|
|
(vvPair
|
|
variable "library_downstream_ModelSimCompiler"
|
|
value "$SCRATCH_DIR/Libs/Memory_test/work"
|
|
)
|
|
(vvPair
|
|
variable "mm"
|
|
value "08"
|
|
)
|
|
(vvPair
|
|
variable "module_name"
|
|
value "flashController_tester"
|
|
)
|
|
(vvPair
|
|
variable "month"
|
|
value "Aug"
|
|
)
|
|
(vvPair
|
|
variable "month_long"
|
|
value "August"
|
|
)
|
|
(vvPair
|
|
variable "p"
|
|
value "/home/francois/Documents/HEVs/Kart/eln_kart/04-Controller/../Libs/Memory_test/hds/flash@controller_tester/interface"
|
|
)
|
|
(vvPair
|
|
variable "p_logical"
|
|
value "/home/francois/Documents/HEVs/Kart/eln_kart/04-Controller/../Libs/Memory_test/hds/flashController_tester/interface"
|
|
)
|
|
(vvPair
|
|
variable "package_name"
|
|
value "<Undefined Variable>"
|
|
)
|
|
(vvPair
|
|
variable "project_name"
|
|
value "hds"
|
|
)
|
|
(vvPair
|
|
variable "series"
|
|
value "HDL Designer Series"
|
|
)
|
|
(vvPair
|
|
variable "task_DesignCompilerPath"
|
|
value "<TBD>"
|
|
)
|
|
(vvPair
|
|
variable "task_ISEPath"
|
|
value "D:\\Labs\\ElN\\BoardTester\\Board\\ise"
|
|
)
|
|
(vvPair
|
|
variable "task_LeonardoPath"
|
|
value "<TBD>"
|
|
)
|
|
(vvPair
|
|
variable "task_ModelSimPath"
|
|
value "C:\\EDA\\Modelsim\\win32"
|
|
)
|
|
(vvPair
|
|
variable "task_NC-SimPath"
|
|
value "<TBD>"
|
|
)
|
|
(vvPair
|
|
variable "task_PrecisionRTLPath"
|
|
value "<TBD>"
|
|
)
|
|
(vvPair
|
|
variable "task_QuestaSimPath"
|
|
value "<TBD>"
|
|
)
|
|
(vvPair
|
|
variable "task_VCSPath"
|
|
value "<TBD>"
|
|
)
|
|
(vvPair
|
|
variable "this_ext"
|
|
value "<TBD>"
|
|
)
|
|
(vvPair
|
|
variable "this_file"
|
|
value "interface"
|
|
)
|
|
(vvPair
|
|
variable "this_file_logical"
|
|
value "interface"
|
|
)
|
|
(vvPair
|
|
variable "time"
|
|
value "13:45:28"
|
|
)
|
|
(vvPair
|
|
variable "unit"
|
|
value "flashController_tester"
|
|
)
|
|
(vvPair
|
|
variable "user"
|
|
value "francois"
|
|
)
|
|
(vvPair
|
|
variable "version"
|
|
value "2018.1 (Build 12)"
|
|
)
|
|
(vvPair
|
|
variable "view"
|
|
value "interface"
|
|
)
|
|
(vvPair
|
|
variable "year"
|
|
value "2019"
|
|
)
|
|
(vvPair
|
|
variable "yy"
|
|
value "19"
|
|
)
|
|
]
|
|
)
|
|
LanguageMgr "Vhdl2008LangMgr"
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