1808 lines
23 KiB
Plaintext
1808 lines
23 KiB
Plaintext
DocumentHdrVersion "1.1"
|
|
Header (DocumentHdr
|
|
version 2
|
|
dialect 11
|
|
dmPackageRefs [
|
|
(DmPackageRef
|
|
library "ieee"
|
|
unitName "std_logic_1164"
|
|
)
|
|
(DmPackageRef
|
|
library "ieee"
|
|
unitName "numeric_std"
|
|
itemName "ALL"
|
|
)
|
|
]
|
|
libraryRefs [
|
|
"ieee"
|
|
]
|
|
)
|
|
version "27.1"
|
|
appVersion "2019.2 (Build 5)"
|
|
model (Symbol
|
|
commonDM (CommonDM
|
|
ldm (LogicalDM
|
|
suid 28,0
|
|
usingSuid 1
|
|
emptyRow *1 (LEmptyRow
|
|
)
|
|
uid 102,0
|
|
optionalChildren [
|
|
*2 (RefLabelRowHdr
|
|
)
|
|
*3 (TitleRowHdr
|
|
)
|
|
*4 (FilterRowHdr
|
|
)
|
|
*5 (RefLabelColHdr
|
|
tm "RefLabelColHdrMgr"
|
|
)
|
|
*6 (RowExpandColHdr
|
|
tm "RowExpandColHdrMgr"
|
|
)
|
|
*7 (GroupColHdr
|
|
tm "GroupColHdrMgr"
|
|
)
|
|
*8 (NameColHdr
|
|
tm "NameColHdrMgr"
|
|
)
|
|
*9 (ModeColHdr
|
|
tm "ModeColHdrMgr"
|
|
)
|
|
*10 (TypeColHdr
|
|
tm "TypeColHdrMgr"
|
|
)
|
|
*11 (BoundsColHdr
|
|
tm "BoundsColHdrMgr"
|
|
)
|
|
*12 (InitColHdr
|
|
tm "InitColHdrMgr"
|
|
)
|
|
*13 (EolColHdr
|
|
tm "EolColHdrMgr"
|
|
)
|
|
*14 (LogPort
|
|
port (LogicalPort
|
|
m 1
|
|
decl (Decl
|
|
n "clock"
|
|
t "std_ulogic"
|
|
o 1
|
|
suid 22,0
|
|
)
|
|
)
|
|
uid 434,0
|
|
)
|
|
*15 (LogPort
|
|
port (LogicalPort
|
|
m 1
|
|
decl (Decl
|
|
n "reset"
|
|
t "std_ulogic"
|
|
o 2
|
|
suid 23,0
|
|
)
|
|
)
|
|
uid 436,0
|
|
)
|
|
*16 (LogPort
|
|
port (LogicalPort
|
|
decl (Decl
|
|
n "sawtooth"
|
|
t "unsigned"
|
|
b "(signalBitNb-1 DOWNTO 0)"
|
|
o 3
|
|
suid 24,0
|
|
)
|
|
)
|
|
uid 438,0
|
|
)
|
|
*17 (LogPort
|
|
port (LogicalPort
|
|
decl (Decl
|
|
n "sine"
|
|
t "unsigned"
|
|
b "(signalBitNb-1 DOWNTO 0)"
|
|
o 4
|
|
suid 25,0
|
|
)
|
|
)
|
|
uid 440,0
|
|
)
|
|
*18 (LogPort
|
|
port (LogicalPort
|
|
decl (Decl
|
|
n "square"
|
|
t "unsigned"
|
|
b "(signalBitNb-1 DOWNTO 0)"
|
|
o 5
|
|
suid 26,0
|
|
)
|
|
)
|
|
uid 442,0
|
|
)
|
|
*19 (LogPort
|
|
port (LogicalPort
|
|
m 1
|
|
decl (Decl
|
|
n "step"
|
|
t "unsigned"
|
|
b "(phaseBitNb-1 DOWNTO 0)"
|
|
o 6
|
|
suid 27,0
|
|
)
|
|
)
|
|
uid 444,0
|
|
)
|
|
*20 (LogPort
|
|
port (LogicalPort
|
|
decl (Decl
|
|
n "triangle"
|
|
t "unsigned"
|
|
b "(signalBitNb-1 DOWNTO 0)"
|
|
o 7
|
|
suid 28,0
|
|
)
|
|
)
|
|
uid 446,0
|
|
)
|
|
]
|
|
)
|
|
pdm (PhysicalDM
|
|
displayShortBounds 1
|
|
editShortBounds 1
|
|
uid 115,0
|
|
optionalChildren [
|
|
*21 (Sheet
|
|
sheetRow (SheetRow
|
|
headerVa (MVa
|
|
cellColor "49152,49152,49152"
|
|
fontColor "0,0,0"
|
|
font "Tahoma,10,0"
|
|
)
|
|
cellVa (MVa
|
|
cellColor "65535,65535,65535"
|
|
fontColor "0,0,0"
|
|
font "Tahoma,10,0"
|
|
)
|
|
groupVa (MVa
|
|
cellColor "39936,56832,65280"
|
|
fontColor "0,0,0"
|
|
font "Tahoma,10,0"
|
|
)
|
|
emptyMRCItem *22 (MRCItem
|
|
litem &1
|
|
pos 7
|
|
dimension 20
|
|
)
|
|
uid 117,0
|
|
optionalChildren [
|
|
*23 (MRCItem
|
|
litem &2
|
|
pos 0
|
|
dimension 20
|
|
uid 118,0
|
|
)
|
|
*24 (MRCItem
|
|
litem &3
|
|
pos 1
|
|
dimension 23
|
|
uid 119,0
|
|
)
|
|
*25 (MRCItem
|
|
litem &4
|
|
pos 2
|
|
hidden 1
|
|
dimension 20
|
|
uid 120,0
|
|
)
|
|
*26 (MRCItem
|
|
litem &14
|
|
pos 0
|
|
dimension 20
|
|
uid 435,0
|
|
)
|
|
*27 (MRCItem
|
|
litem &15
|
|
pos 1
|
|
dimension 20
|
|
uid 437,0
|
|
)
|
|
*28 (MRCItem
|
|
litem &16
|
|
pos 2
|
|
dimension 20
|
|
uid 439,0
|
|
)
|
|
*29 (MRCItem
|
|
litem &17
|
|
pos 3
|
|
dimension 20
|
|
uid 441,0
|
|
)
|
|
*30 (MRCItem
|
|
litem &18
|
|
pos 4
|
|
dimension 20
|
|
uid 443,0
|
|
)
|
|
*31 (MRCItem
|
|
litem &19
|
|
pos 5
|
|
dimension 20
|
|
uid 445,0
|
|
)
|
|
*32 (MRCItem
|
|
litem &20
|
|
pos 6
|
|
dimension 20
|
|
uid 447,0
|
|
)
|
|
]
|
|
)
|
|
sheetCol (SheetCol
|
|
propVa (MVa
|
|
cellColor "0,49152,49152"
|
|
fontColor "0,0,0"
|
|
font "Tahoma,10,0"
|
|
textAngle 90
|
|
)
|
|
uid 121,0
|
|
optionalChildren [
|
|
*33 (MRCItem
|
|
litem &5
|
|
pos 0
|
|
dimension 20
|
|
uid 122,0
|
|
)
|
|
*34 (MRCItem
|
|
litem &7
|
|
pos 1
|
|
dimension 50
|
|
uid 123,0
|
|
)
|
|
*35 (MRCItem
|
|
litem &8
|
|
pos 2
|
|
dimension 100
|
|
uid 124,0
|
|
)
|
|
*36 (MRCItem
|
|
litem &9
|
|
pos 3
|
|
dimension 50
|
|
uid 125,0
|
|
)
|
|
*37 (MRCItem
|
|
litem &10
|
|
pos 4
|
|
dimension 100
|
|
uid 126,0
|
|
)
|
|
*38 (MRCItem
|
|
litem &11
|
|
pos 5
|
|
dimension 100
|
|
uid 127,0
|
|
)
|
|
*39 (MRCItem
|
|
litem &12
|
|
pos 6
|
|
dimension 50
|
|
uid 128,0
|
|
)
|
|
*40 (MRCItem
|
|
litem &13
|
|
pos 7
|
|
dimension 80
|
|
uid 129,0
|
|
)
|
|
]
|
|
)
|
|
fixedCol 4
|
|
fixedRow 2
|
|
name "Ports"
|
|
uid 116,0
|
|
vaOverrides [
|
|
]
|
|
)
|
|
]
|
|
)
|
|
uid 101,0
|
|
)
|
|
genericsCommonDM (CommonDM
|
|
ldm (LogicalDM
|
|
emptyRow *41 (LEmptyRow
|
|
)
|
|
uid 131,0
|
|
optionalChildren [
|
|
*42 (RefLabelRowHdr
|
|
)
|
|
*43 (TitleRowHdr
|
|
)
|
|
*44 (FilterRowHdr
|
|
)
|
|
*45 (RefLabelColHdr
|
|
tm "RefLabelColHdrMgr"
|
|
)
|
|
*46 (RowExpandColHdr
|
|
tm "RowExpandColHdrMgr"
|
|
)
|
|
*47 (GroupColHdr
|
|
tm "GroupColHdrMgr"
|
|
)
|
|
*48 (NameColHdr
|
|
tm "GenericNameColHdrMgr"
|
|
)
|
|
*49 (TypeColHdr
|
|
tm "GenericTypeColHdrMgr"
|
|
)
|
|
*50 (InitColHdr
|
|
tm "GenericValueColHdrMgr"
|
|
)
|
|
*51 (PragmaColHdr
|
|
tm "GenericPragmaColHdrMgr"
|
|
)
|
|
*52 (EolColHdr
|
|
tm "GenericEolColHdrMgr"
|
|
)
|
|
*53 (LogGeneric
|
|
generic (GiElement
|
|
name "signalBitNb"
|
|
type "positive"
|
|
value "16"
|
|
)
|
|
uid 180,0
|
|
)
|
|
*54 (LogGeneric
|
|
generic (GiElement
|
|
name "phaseBitNb"
|
|
type "positive"
|
|
value "10"
|
|
)
|
|
uid 182,0
|
|
)
|
|
*55 (LogGeneric
|
|
generic (GiElement
|
|
name "clockFrequency"
|
|
type "real"
|
|
value "60.0E6"
|
|
)
|
|
uid 374,0
|
|
)
|
|
]
|
|
)
|
|
pdm (PhysicalDM
|
|
displayShortBounds 1
|
|
editShortBounds 1
|
|
uid 143,0
|
|
optionalChildren [
|
|
*56 (Sheet
|
|
sheetRow (SheetRow
|
|
headerVa (MVa
|
|
cellColor "49152,49152,49152"
|
|
fontColor "0,0,0"
|
|
font "Tahoma,10,0"
|
|
)
|
|
cellVa (MVa
|
|
cellColor "65535,65535,65535"
|
|
fontColor "0,0,0"
|
|
font "Tahoma,10,0"
|
|
)
|
|
groupVa (MVa
|
|
cellColor "39936,56832,65280"
|
|
fontColor "0,0,0"
|
|
font "Tahoma,10,0"
|
|
)
|
|
emptyMRCItem *57 (MRCItem
|
|
litem &41
|
|
pos 3
|
|
dimension 20
|
|
)
|
|
uid 145,0
|
|
optionalChildren [
|
|
*58 (MRCItem
|
|
litem &42
|
|
pos 0
|
|
dimension 20
|
|
uid 146,0
|
|
)
|
|
*59 (MRCItem
|
|
litem &43
|
|
pos 1
|
|
dimension 23
|
|
uid 147,0
|
|
)
|
|
*60 (MRCItem
|
|
litem &44
|
|
pos 2
|
|
hidden 1
|
|
dimension 20
|
|
uid 148,0
|
|
)
|
|
*61 (MRCItem
|
|
litem &53
|
|
pos 0
|
|
dimension 20
|
|
uid 181,0
|
|
)
|
|
*62 (MRCItem
|
|
litem &54
|
|
pos 1
|
|
dimension 20
|
|
uid 183,0
|
|
)
|
|
*63 (MRCItem
|
|
litem &55
|
|
pos 2
|
|
dimension 20
|
|
uid 375,0
|
|
)
|
|
]
|
|
)
|
|
sheetCol (SheetCol
|
|
propVa (MVa
|
|
cellColor "0,49152,49152"
|
|
fontColor "0,0,0"
|
|
font "Tahoma,10,0"
|
|
textAngle 90
|
|
)
|
|
uid 149,0
|
|
optionalChildren [
|
|
*64 (MRCItem
|
|
litem &45
|
|
pos 0
|
|
dimension 20
|
|
uid 150,0
|
|
)
|
|
*65 (MRCItem
|
|
litem &47
|
|
pos 1
|
|
dimension 50
|
|
uid 151,0
|
|
)
|
|
*66 (MRCItem
|
|
litem &48
|
|
pos 2
|
|
dimension 100
|
|
uid 152,0
|
|
)
|
|
*67 (MRCItem
|
|
litem &49
|
|
pos 3
|
|
dimension 100
|
|
uid 153,0
|
|
)
|
|
*68 (MRCItem
|
|
litem &50
|
|
pos 4
|
|
dimension 50
|
|
uid 154,0
|
|
)
|
|
*69 (MRCItem
|
|
litem &51
|
|
pos 5
|
|
dimension 50
|
|
uid 155,0
|
|
)
|
|
*70 (MRCItem
|
|
litem &52
|
|
pos 6
|
|
dimension 80
|
|
uid 156,0
|
|
)
|
|
]
|
|
)
|
|
fixedCol 3
|
|
fixedRow 2
|
|
name "Ports"
|
|
uid 144,0
|
|
vaOverrides [
|
|
]
|
|
)
|
|
]
|
|
)
|
|
uid 130,0
|
|
type 1
|
|
)
|
|
VExpander (VariableExpander
|
|
vvMap [
|
|
(vvPair
|
|
variable "HDLDir"
|
|
value "C:\\dev\\sem-labs\\02-SplineInterpolator\\Prefs\\..\\SplineInterpolator_test\\hdl"
|
|
)
|
|
(vvPair
|
|
variable "HDSDir"
|
|
value "C:\\dev\\sem-labs\\02-SplineInterpolator\\Prefs\\..\\SplineInterpolator_test\\hds"
|
|
)
|
|
(vvPair
|
|
variable "SideDataDesignDir"
|
|
value "C:\\dev\\sem-labs\\02-SplineInterpolator\\Prefs\\..\\SplineInterpolator_test\\hds\\sine@gen_tester\\interface.info"
|
|
)
|
|
(vvPair
|
|
variable "SideDataUserDir"
|
|
value "C:\\dev\\sem-labs\\02-SplineInterpolator\\Prefs\\..\\SplineInterpolator_test\\hds\\sine@gen_tester\\interface.user"
|
|
)
|
|
(vvPair
|
|
variable "SourceDir"
|
|
value "C:\\dev\\sem-labs\\02-SplineInterpolator\\Prefs\\..\\SplineInterpolator_test\\hds"
|
|
)
|
|
(vvPair
|
|
variable "appl"
|
|
value "HDL Designer"
|
|
)
|
|
(vvPair
|
|
variable "arch_name"
|
|
value "interface"
|
|
)
|
|
(vvPair
|
|
variable "asm_file"
|
|
value "beamer.asm"
|
|
)
|
|
(vvPair
|
|
variable "concat_file"
|
|
value "concatenated"
|
|
)
|
|
(vvPair
|
|
variable "config"
|
|
value "%(unit)_%(view)_config"
|
|
)
|
|
(vvPair
|
|
variable "d"
|
|
value "C:\\dev\\sem-labs\\02-SplineInterpolator\\Prefs\\..\\SplineInterpolator_test\\hds\\sine@gen_tester"
|
|
)
|
|
(vvPair
|
|
variable "d_logical"
|
|
value "C:\\dev\\sem-labs\\02-SplineInterpolator\\Prefs\\..\\SplineInterpolator_test\\hds\\sineGen_tester"
|
|
)
|
|
(vvPair
|
|
variable "date"
|
|
value "28.04.2023"
|
|
)
|
|
(vvPair
|
|
variable "day"
|
|
value "ven."
|
|
)
|
|
(vvPair
|
|
variable "day_long"
|
|
value "vendredi"
|
|
)
|
|
(vvPair
|
|
variable "dd"
|
|
value "28"
|
|
)
|
|
(vvPair
|
|
variable "designName"
|
|
value "$DESIGN_NAME"
|
|
)
|
|
(vvPair
|
|
variable "entity_name"
|
|
value "sineGen_tester"
|
|
)
|
|
(vvPair
|
|
variable "ext"
|
|
value "<TBD>"
|
|
)
|
|
(vvPair
|
|
variable "f"
|
|
value "interface"
|
|
)
|
|
(vvPair
|
|
variable "f_logical"
|
|
value "interface"
|
|
)
|
|
(vvPair
|
|
variable "f_noext"
|
|
value "interface"
|
|
)
|
|
(vvPair
|
|
variable "graphical_source_author"
|
|
value "axel.amand"
|
|
)
|
|
(vvPair
|
|
variable "graphical_source_date"
|
|
value "28.04.2023"
|
|
)
|
|
(vvPair
|
|
variable "graphical_source_group"
|
|
value "UNKNOWN"
|
|
)
|
|
(vvPair
|
|
variable "graphical_source_host"
|
|
value "WE7860"
|
|
)
|
|
(vvPair
|
|
variable "graphical_source_time"
|
|
value "14:41:39"
|
|
)
|
|
(vvPair
|
|
variable "group"
|
|
value "UNKNOWN"
|
|
)
|
|
(vvPair
|
|
variable "host"
|
|
value "WE7860"
|
|
)
|
|
(vvPair
|
|
variable "language"
|
|
value "VHDL"
|
|
)
|
|
(vvPair
|
|
variable "library"
|
|
value "SplineInterpolator_test"
|
|
)
|
|
(vvPair
|
|
variable "library_downstream_ModelSimCompiler"
|
|
value "$SCRATCH_DIR/SplineInterpolator_test"
|
|
)
|
|
(vvPair
|
|
variable "mm"
|
|
value "04"
|
|
)
|
|
(vvPair
|
|
variable "module_name"
|
|
value "sineGen_tester"
|
|
)
|
|
(vvPair
|
|
variable "month"
|
|
value "avr."
|
|
)
|
|
(vvPair
|
|
variable "month_long"
|
|
value "avril"
|
|
)
|
|
(vvPair
|
|
variable "p"
|
|
value "C:\\dev\\sem-labs\\02-SplineInterpolator\\Prefs\\..\\SplineInterpolator_test\\hds\\sine@gen_tester\\interface"
|
|
)
|
|
(vvPair
|
|
variable "p_logical"
|
|
value "C:\\dev\\sem-labs\\02-SplineInterpolator\\Prefs\\..\\SplineInterpolator_test\\hds\\sineGen_tester\\interface"
|
|
)
|
|
(vvPair
|
|
variable "package_name"
|
|
value "<Undefined Variable>"
|
|
)
|
|
(vvPair
|
|
variable "project_name"
|
|
value "hds"
|
|
)
|
|
(vvPair
|
|
variable "series"
|
|
value "HDL Designer Series"
|
|
)
|
|
(vvPair
|
|
variable "task_AsmPath"
|
|
value "$HEI_LIBS_DIR/NanoBlaze/hdl"
|
|
)
|
|
(vvPair
|
|
variable "task_HDSPath"
|
|
value "$HDS_HOME"
|
|
)
|
|
(vvPair
|
|
variable "task_ISEBinPath"
|
|
value "$ISE_HOME"
|
|
)
|
|
(vvPair
|
|
variable "task_ISEPath"
|
|
value "$ISE_WORK_DIR"
|
|
)
|
|
(vvPair
|
|
variable "task_ModelSimPath"
|
|
value "$MODELSIM_HOME/modeltech/bin"
|
|
)
|
|
(vvPair
|
|
variable "this_ext"
|
|
value "<TBD>"
|
|
)
|
|
(vvPair
|
|
variable "this_file"
|
|
value "interface"
|
|
)
|
|
(vvPair
|
|
variable "this_file_logical"
|
|
value "interface"
|
|
)
|
|
(vvPair
|
|
variable "time"
|
|
value "14:41:39"
|
|
)
|
|
(vvPair
|
|
variable "unit"
|
|
value "sineGen_tester"
|
|
)
|
|
(vvPair
|
|
variable "user"
|
|
value "axel.amand"
|
|
)
|
|
(vvPair
|
|
variable "version"
|
|
value "2019.2 (Build 5)"
|
|
)
|
|
(vvPair
|
|
variable "view"
|
|
value "interface"
|
|
)
|
|
(vvPair
|
|
variable "year"
|
|
value "2023"
|
|
)
|
|
(vvPair
|
|
variable "yy"
|
|
value "23"
|
|
)
|
|
]
|
|
)
|
|
LanguageMgr "Vhdl2008LangMgr"
|
|
uid 100,0
|
|
optionalChildren [
|
|
*71 (SymbolBody
|
|
uid 8,0
|
|
optionalChildren [
|
|
*72 (CptPort
|
|
uid 399,0
|
|
ps "OnEdgeStrategy"
|
|
shape (Triangle
|
|
uid 400,0
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "0,65535,0"
|
|
)
|
|
xt "28625,5250,29375,6000"
|
|
)
|
|
tg (CPTG
|
|
uid 401,0
|
|
ps "CptPortTextPlaceStrategy"
|
|
stg "RightVerticalLayoutStrategy"
|
|
f (Text
|
|
uid 402,0
|
|
ro 270
|
|
va (VaSet
|
|
font "Verdana,12,0"
|
|
)
|
|
xt "28300,7000,29700,10800"
|
|
st "clock"
|
|
ju 2
|
|
blo "29500,7000"
|
|
tm "CptPortNameMgr"
|
|
)
|
|
)
|
|
dt (MLText
|
|
uid 403,0
|
|
va (VaSet
|
|
font "Courier New,8,0"
|
|
)
|
|
xt "44000,5200,61000,6000"
|
|
st "clock : OUT std_ulogic ;
|
|
"
|
|
)
|
|
thePort (LogicalPort
|
|
m 1
|
|
decl (Decl
|
|
n "clock"
|
|
t "std_ulogic"
|
|
o 1
|
|
suid 22,0
|
|
)
|
|
)
|
|
)
|
|
*73 (CptPort
|
|
uid 404,0
|
|
ps "OnEdgeStrategy"
|
|
shape (Triangle
|
|
uid 405,0
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "0,65535,0"
|
|
)
|
|
xt "30625,5250,31375,6000"
|
|
)
|
|
tg (CPTG
|
|
uid 406,0
|
|
ps "CptPortTextPlaceStrategy"
|
|
stg "RightVerticalLayoutStrategy"
|
|
f (Text
|
|
uid 407,0
|
|
ro 270
|
|
va (VaSet
|
|
font "Verdana,12,0"
|
|
)
|
|
xt "30300,7000,31700,11100"
|
|
st "reset"
|
|
ju 2
|
|
blo "31500,7000"
|
|
tm "CptPortNameMgr"
|
|
)
|
|
)
|
|
dt (MLText
|
|
uid 408,0
|
|
va (VaSet
|
|
font "Courier New,8,0"
|
|
)
|
|
xt "44000,6000,61000,6800"
|
|
st "reset : OUT std_ulogic ;
|
|
"
|
|
)
|
|
thePort (LogicalPort
|
|
m 1
|
|
decl (Decl
|
|
n "reset"
|
|
t "std_ulogic"
|
|
o 2
|
|
suid 23,0
|
|
)
|
|
)
|
|
)
|
|
*74 (CptPort
|
|
uid 409,0
|
|
ps "OnEdgeStrategy"
|
|
shape (Triangle
|
|
uid 410,0
|
|
ro 180
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "0,65535,0"
|
|
)
|
|
xt "60625,5250,61375,6000"
|
|
)
|
|
tg (CPTG
|
|
uid 411,0
|
|
ps "CptPortTextPlaceStrategy"
|
|
stg "RightVerticalLayoutStrategy"
|
|
f (Text
|
|
uid 412,0
|
|
ro 270
|
|
va (VaSet
|
|
font "Verdana,12,0"
|
|
)
|
|
xt "60300,7000,61700,13800"
|
|
st "sawtooth"
|
|
ju 2
|
|
blo "61500,7000"
|
|
tm "CptPortNameMgr"
|
|
)
|
|
)
|
|
dt (MLText
|
|
uid 413,0
|
|
va (VaSet
|
|
font "Courier New,8,0"
|
|
)
|
|
xt "44000,2000,72500,2800"
|
|
st "sawtooth : IN unsigned (signalBitNb-1 DOWNTO 0) ;
|
|
"
|
|
)
|
|
thePort (LogicalPort
|
|
decl (Decl
|
|
n "sawtooth"
|
|
t "unsigned"
|
|
b "(signalBitNb-1 DOWNTO 0)"
|
|
o 3
|
|
suid 24,0
|
|
)
|
|
)
|
|
)
|
|
*75 (CptPort
|
|
uid 414,0
|
|
ps "OnEdgeStrategy"
|
|
shape (Triangle
|
|
uid 415,0
|
|
ro 180
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "0,65535,0"
|
|
)
|
|
xt "54625,5250,55375,6000"
|
|
)
|
|
tg (CPTG
|
|
uid 416,0
|
|
ps "CptPortTextPlaceStrategy"
|
|
stg "RightVerticalLayoutStrategy"
|
|
f (Text
|
|
uid 417,0
|
|
ro 270
|
|
va (VaSet
|
|
font "Verdana,12,0"
|
|
)
|
|
xt "54300,7000,55700,10400"
|
|
st "sine"
|
|
ju 2
|
|
blo "55500,7000"
|
|
tm "CptPortNameMgr"
|
|
)
|
|
)
|
|
dt (MLText
|
|
uid 418,0
|
|
va (VaSet
|
|
font "Courier New,8,0"
|
|
)
|
|
xt "44000,2800,72500,3600"
|
|
st "sine : IN unsigned (signalBitNb-1 DOWNTO 0) ;
|
|
"
|
|
)
|
|
thePort (LogicalPort
|
|
decl (Decl
|
|
n "sine"
|
|
t "unsigned"
|
|
b "(signalBitNb-1 DOWNTO 0)"
|
|
o 4
|
|
suid 25,0
|
|
)
|
|
)
|
|
)
|
|
*76 (CptPort
|
|
uid 419,0
|
|
ps "OnEdgeStrategy"
|
|
shape (Triangle
|
|
uid 420,0
|
|
ro 180
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "0,65535,0"
|
|
)
|
|
xt "58625,5250,59375,6000"
|
|
)
|
|
tg (CPTG
|
|
uid 421,0
|
|
ps "CptPortTextPlaceStrategy"
|
|
stg "RightVerticalLayoutStrategy"
|
|
f (Text
|
|
uid 422,0
|
|
ro 270
|
|
va (VaSet
|
|
font "Verdana,12,0"
|
|
)
|
|
xt "58300,7000,59700,12200"
|
|
st "square"
|
|
ju 2
|
|
blo "59500,7000"
|
|
tm "CptPortNameMgr"
|
|
)
|
|
)
|
|
dt (MLText
|
|
uid 423,0
|
|
va (VaSet
|
|
font "Courier New,8,0"
|
|
)
|
|
xt "44000,3600,72500,4400"
|
|
st "square : IN unsigned (signalBitNb-1 DOWNTO 0) ;
|
|
"
|
|
)
|
|
thePort (LogicalPort
|
|
decl (Decl
|
|
n "square"
|
|
t "unsigned"
|
|
b "(signalBitNb-1 DOWNTO 0)"
|
|
o 5
|
|
suid 26,0
|
|
)
|
|
)
|
|
)
|
|
*77 (CptPort
|
|
uid 424,0
|
|
ps "OnEdgeStrategy"
|
|
shape (Triangle
|
|
uid 425,0
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "0,65535,0"
|
|
)
|
|
xt "22625,5250,23375,6000"
|
|
)
|
|
tg (CPTG
|
|
uid 426,0
|
|
ps "CptPortTextPlaceStrategy"
|
|
stg "RightVerticalLayoutStrategy"
|
|
f (Text
|
|
uid 427,0
|
|
ro 270
|
|
va (VaSet
|
|
font "Verdana,12,0"
|
|
)
|
|
xt "22300,7000,23700,10600"
|
|
st "step"
|
|
ju 2
|
|
blo "23500,7000"
|
|
tm "CptPortNameMgr"
|
|
)
|
|
)
|
|
dt (MLText
|
|
uid 428,0
|
|
va (VaSet
|
|
font "Courier New,8,0"
|
|
)
|
|
xt "44000,6800,71000,7600"
|
|
st "step : OUT unsigned (phaseBitNb-1 DOWNTO 0)
|
|
"
|
|
)
|
|
thePort (LogicalPort
|
|
m 1
|
|
decl (Decl
|
|
n "step"
|
|
t "unsigned"
|
|
b "(phaseBitNb-1 DOWNTO 0)"
|
|
o 6
|
|
suid 27,0
|
|
)
|
|
)
|
|
)
|
|
*78 (CptPort
|
|
uid 429,0
|
|
ps "OnEdgeStrategy"
|
|
shape (Triangle
|
|
uid 430,0
|
|
ro 180
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "0,65535,0"
|
|
)
|
|
xt "56625,5250,57375,6000"
|
|
)
|
|
tg (CPTG
|
|
uid 431,0
|
|
ps "CptPortTextPlaceStrategy"
|
|
stg "RightVerticalLayoutStrategy"
|
|
f (Text
|
|
uid 432,0
|
|
ro 270
|
|
va (VaSet
|
|
font "Verdana,12,0"
|
|
)
|
|
xt "56300,7000,57700,12600"
|
|
st "triangle"
|
|
ju 2
|
|
blo "57500,7000"
|
|
tm "CptPortNameMgr"
|
|
)
|
|
)
|
|
dt (MLText
|
|
uid 433,0
|
|
va (VaSet
|
|
font "Courier New,8,0"
|
|
)
|
|
xt "44000,4400,72500,5200"
|
|
st "triangle : IN unsigned (signalBitNb-1 DOWNTO 0) ;
|
|
"
|
|
)
|
|
thePort (LogicalPort
|
|
decl (Decl
|
|
n "triangle"
|
|
t "unsigned"
|
|
b "(signalBitNb-1 DOWNTO 0)"
|
|
o 7
|
|
suid 28,0
|
|
)
|
|
)
|
|
)
|
|
]
|
|
shape (Rectangle
|
|
uid 9,0
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "0,65535,0"
|
|
lineColor "0,32896,0"
|
|
lineWidth 2
|
|
)
|
|
xt "15000,6000,69000,14000"
|
|
)
|
|
biTextGroup (BiTextGroup
|
|
uid 10,0
|
|
ps "CenterOffsetStrategy"
|
|
stg "VerticalLayoutStrategy"
|
|
first (Text
|
|
uid 11,0
|
|
va (VaSet
|
|
font "Verdana,8,1"
|
|
)
|
|
xt "35600,9000,48400,10000"
|
|
st "SplineInterpolator_test"
|
|
blo "35600,9800"
|
|
)
|
|
second (Text
|
|
uid 12,0
|
|
va (VaSet
|
|
font "Verdana,8,1"
|
|
)
|
|
xt "35600,10000,43700,11000"
|
|
st "sineGen_tester"
|
|
blo "35600,10800"
|
|
)
|
|
)
|
|
gi *79 (GenericInterface
|
|
uid 13,0
|
|
ps "CenterOffsetStrategy"
|
|
matrix (Matrix
|
|
uid 14,0
|
|
text (MLText
|
|
uid 15,0
|
|
va (VaSet
|
|
font "Verdana,8,0"
|
|
)
|
|
xt "15000,6000,29400,11000"
|
|
st "Generic Declarations
|
|
|
|
signalBitNb positive 16
|
|
phaseBitNb positive 10
|
|
clockFrequency real 60.0E6 "
|
|
)
|
|
header "Generic Declarations"
|
|
showHdrWhenContentsEmpty 1
|
|
)
|
|
elements [
|
|
(GiElement
|
|
name "signalBitNb"
|
|
type "positive"
|
|
value "16"
|
|
)
|
|
(GiElement
|
|
name "phaseBitNb"
|
|
type "positive"
|
|
value "10"
|
|
)
|
|
(GiElement
|
|
name "clockFrequency"
|
|
type "real"
|
|
value "60.0E6"
|
|
)
|
|
]
|
|
)
|
|
portInstanceVisAsIs 1
|
|
portInstanceVis (PortSigDisplay
|
|
sTC 0
|
|
sF 0
|
|
)
|
|
portVis (PortSigDisplay
|
|
sTC 0
|
|
sF 0
|
|
)
|
|
)
|
|
*80 (Grouping
|
|
uid 16,0
|
|
optionalChildren [
|
|
*81 (CommentText
|
|
uid 18,0
|
|
shape (Rectangle
|
|
uid 19,0
|
|
sl 0
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "65280,65280,46080"
|
|
)
|
|
xt "32000,50000,49000,51000"
|
|
)
|
|
oxt "18000,70000,35000,71000"
|
|
text (MLText
|
|
uid 20,0
|
|
va (VaSet
|
|
fg "0,0,32768"
|
|
bg "0,0,32768"
|
|
font "Verdana,8,0"
|
|
)
|
|
xt "32200,50000,46600,51000"
|
|
st "
|
|
by %user on %dd %month %year
|
|
"
|
|
tm "CommentText"
|
|
wrapOption 3
|
|
visibleHeight 1000
|
|
visibleWidth 17000
|
|
)
|
|
position 1
|
|
ignorePrefs 1
|
|
titleBlock 1
|
|
)
|
|
*82 (CommentText
|
|
uid 21,0
|
|
shape (Rectangle
|
|
uid 22,0
|
|
sl 0
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "65280,65280,46080"
|
|
)
|
|
xt "49000,46000,53000,47000"
|
|
)
|
|
oxt "35000,66000,39000,67000"
|
|
text (MLText
|
|
uid 23,0
|
|
va (VaSet
|
|
fg "0,0,32768"
|
|
bg "0,0,32768"
|
|
font "Verdana,8,0"
|
|
)
|
|
xt "49200,46000,52900,47000"
|
|
st "
|
|
Project:
|
|
"
|
|
tm "CommentText"
|
|
wrapOption 3
|
|
visibleHeight 1000
|
|
visibleWidth 4000
|
|
)
|
|
position 1
|
|
ignorePrefs 1
|
|
titleBlock 1
|
|
)
|
|
*83 (CommentText
|
|
uid 24,0
|
|
shape (Rectangle
|
|
uid 25,0
|
|
sl 0
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "65280,65280,46080"
|
|
)
|
|
xt "32000,48000,49000,49000"
|
|
)
|
|
oxt "18000,68000,35000,69000"
|
|
text (MLText
|
|
uid 26,0
|
|
va (VaSet
|
|
fg "0,0,32768"
|
|
bg "0,0,32768"
|
|
font "Verdana,8,0"
|
|
)
|
|
xt "32200,48000,44700,49000"
|
|
st "
|
|
<enter diagram title here>
|
|
"
|
|
tm "CommentText"
|
|
wrapOption 3
|
|
visibleHeight 1000
|
|
visibleWidth 17000
|
|
)
|
|
position 1
|
|
ignorePrefs 1
|
|
titleBlock 1
|
|
)
|
|
*84 (CommentText
|
|
uid 27,0
|
|
shape (Rectangle
|
|
uid 28,0
|
|
sl 0
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "65280,65280,46080"
|
|
)
|
|
xt "28000,48000,32000,49000"
|
|
)
|
|
oxt "14000,68000,18000,69000"
|
|
text (MLText
|
|
uid 29,0
|
|
va (VaSet
|
|
fg "0,0,32768"
|
|
bg "0,0,32768"
|
|
font "Verdana,8,0"
|
|
)
|
|
xt "28200,48000,30800,49000"
|
|
st "
|
|
Title:
|
|
"
|
|
tm "CommentText"
|
|
wrapOption 3
|
|
visibleHeight 1000
|
|
visibleWidth 4000
|
|
)
|
|
position 1
|
|
ignorePrefs 1
|
|
titleBlock 1
|
|
)
|
|
*85 (CommentText
|
|
uid 30,0
|
|
shape (Rectangle
|
|
uid 31,0
|
|
sl 0
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "65280,65280,46080"
|
|
)
|
|
xt "49000,47000,69000,51000"
|
|
)
|
|
oxt "35000,67000,55000,71000"
|
|
text (MLText
|
|
uid 32,0
|
|
va (VaSet
|
|
fg "0,0,32768"
|
|
bg "0,0,32768"
|
|
font "Verdana,8,0"
|
|
)
|
|
xt "49200,47200,60800,48200"
|
|
st "
|
|
<enter comments here>
|
|
"
|
|
tm "CommentText"
|
|
wrapOption 3
|
|
visibleHeight 4000
|
|
visibleWidth 20000
|
|
)
|
|
ignorePrefs 1
|
|
titleBlock 1
|
|
)
|
|
*86 (CommentText
|
|
uid 33,0
|
|
shape (Rectangle
|
|
uid 34,0
|
|
sl 0
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "65280,65280,46080"
|
|
)
|
|
xt "53000,46000,69000,47000"
|
|
)
|
|
oxt "39000,66000,55000,67000"
|
|
text (MLText
|
|
uid 35,0
|
|
va (VaSet
|
|
fg "0,0,32768"
|
|
bg "0,0,32768"
|
|
font "Verdana,8,0"
|
|
)
|
|
xt "53200,46000,55100,47000"
|
|
st "
|
|
%project_name
|
|
"
|
|
tm "CommentText"
|
|
wrapOption 3
|
|
visibleHeight 1000
|
|
visibleWidth 16000
|
|
)
|
|
position 1
|
|
ignorePrefs 1
|
|
titleBlock 1
|
|
)
|
|
*87 (CommentText
|
|
uid 36,0
|
|
shape (Rectangle
|
|
uid 37,0
|
|
sl 0
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "65280,65280,46080"
|
|
)
|
|
xt "28000,46000,49000,48000"
|
|
)
|
|
oxt "14000,66000,35000,68000"
|
|
text (MLText
|
|
uid 38,0
|
|
va (VaSet
|
|
fg "32768,0,0"
|
|
)
|
|
xt "33350,46400,43650,47600"
|
|
st "
|
|
<company name>
|
|
"
|
|
ju 0
|
|
tm "CommentText"
|
|
wrapOption 3
|
|
visibleHeight 2000
|
|
visibleWidth 21000
|
|
)
|
|
position 1
|
|
ignorePrefs 1
|
|
titleBlock 1
|
|
)
|
|
*88 (CommentText
|
|
uid 39,0
|
|
shape (Rectangle
|
|
uid 40,0
|
|
sl 0
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "65280,65280,46080"
|
|
)
|
|
xt "28000,49000,32000,50000"
|
|
)
|
|
oxt "14000,69000,18000,70000"
|
|
text (MLText
|
|
uid 41,0
|
|
va (VaSet
|
|
fg "0,0,32768"
|
|
bg "0,0,32768"
|
|
font "Verdana,8,0"
|
|
)
|
|
xt "28200,49000,30900,50000"
|
|
st "
|
|
Path:
|
|
"
|
|
tm "CommentText"
|
|
wrapOption 3
|
|
visibleHeight 1000
|
|
visibleWidth 4000
|
|
)
|
|
position 1
|
|
ignorePrefs 1
|
|
titleBlock 1
|
|
)
|
|
*89 (CommentText
|
|
uid 42,0
|
|
shape (Rectangle
|
|
uid 43,0
|
|
sl 0
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "65280,65280,46080"
|
|
)
|
|
xt "28000,50000,32000,51000"
|
|
)
|
|
oxt "14000,70000,18000,71000"
|
|
text (MLText
|
|
uid 44,0
|
|
va (VaSet
|
|
fg "0,0,32768"
|
|
bg "0,0,32768"
|
|
font "Verdana,8,0"
|
|
)
|
|
xt "28200,50000,31600,51000"
|
|
st "
|
|
Edited:
|
|
"
|
|
tm "CommentText"
|
|
wrapOption 3
|
|
visibleHeight 1000
|
|
visibleWidth 4000
|
|
)
|
|
position 1
|
|
ignorePrefs 1
|
|
titleBlock 1
|
|
)
|
|
*90 (CommentText
|
|
uid 45,0
|
|
shape (Rectangle
|
|
uid 46,0
|
|
sl 0
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "65280,65280,46080"
|
|
)
|
|
xt "32000,49000,49000,50000"
|
|
)
|
|
oxt "18000,69000,35000,70000"
|
|
text (MLText
|
|
uid 47,0
|
|
va (VaSet
|
|
fg "0,0,32768"
|
|
bg "0,0,32768"
|
|
font "Verdana,8,0"
|
|
)
|
|
xt "32200,49000,43200,50000"
|
|
st "
|
|
%library/%unit/%view
|
|
"
|
|
tm "CommentText"
|
|
wrapOption 3
|
|
visibleHeight 1000
|
|
visibleWidth 17000
|
|
)
|
|
position 1
|
|
ignorePrefs 1
|
|
titleBlock 1
|
|
)
|
|
]
|
|
shape (GroupingShape
|
|
uid 17,0
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "65535,65535,65535"
|
|
lineStyle 2
|
|
lineWidth 2
|
|
)
|
|
xt "28000,46000,69000,51000"
|
|
)
|
|
oxt "14000,66000,55000,71000"
|
|
)
|
|
]
|
|
bg "65535,65535,65535"
|
|
grid (Grid
|
|
origin "0,0"
|
|
isVisible 1
|
|
isActive 1
|
|
xSpacing 1000
|
|
xySpacing 1000
|
|
xShown 1
|
|
yShown 1
|
|
color "26368,26368,26368"
|
|
)
|
|
packageList *91 (PackageList
|
|
uid 48,0
|
|
stg "VerticalLayoutStrategy"
|
|
textVec [
|
|
*92 (Text
|
|
uid 49,0
|
|
va (VaSet
|
|
font "Verdana,8,1"
|
|
)
|
|
xt "0,0,6900,1000"
|
|
st "Package List"
|
|
blo "0,800"
|
|
)
|
|
*93 (MLText
|
|
uid 50,0
|
|
va (VaSet
|
|
font "Verdana,8,0"
|
|
)
|
|
xt "0,900,13600,3900"
|
|
st "LIBRARY ieee;
|
|
USE ieee.std_logic_1164.all;
|
|
USE ieee.numeric_std.ALL;"
|
|
tm "PackageList"
|
|
)
|
|
]
|
|
)
|
|
windowSize "59,33,1075,723"
|
|
viewArea "-500,-500,85152,57543"
|
|
cachedDiagramExtent "0,0,72500,51000"
|
|
hasePageBreakOrigin 1
|
|
pageBreakOrigin "0,0"
|
|
defaultCommentText (CommentText
|
|
shape (Rectangle
|
|
layer 0
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "65280,65280,46080"
|
|
lineColor "0,0,32768"
|
|
)
|
|
xt "0,0,15000,5000"
|
|
)
|
|
text (MLText
|
|
va (VaSet
|
|
fg "0,0,32768"
|
|
font "Verdana,8,0"
|
|
)
|
|
xt "200,200,2500,1200"
|
|
st "
|
|
Text
|
|
"
|
|
tm "CommentText"
|
|
wrapOption 3
|
|
visibleHeight 4600
|
|
visibleWidth 14600
|
|
)
|
|
)
|
|
defaultRequirementText (RequirementText
|
|
shape (ZoomableIcon
|
|
layer 0
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "59904,39936,65280"
|
|
lineColor "0,0,32768"
|
|
)
|
|
xt "0,0,1500,1750"
|
|
iconName "reqTracerRequirement.bmp"
|
|
iconMaskName "reqTracerRequirement.msk"
|
|
)
|
|
autoResize 1
|
|
text (MLText
|
|
va (VaSet
|
|
fg "0,0,32768"
|
|
font "Verdana,8,0"
|
|
)
|
|
xt "450,2150,1450,3150"
|
|
st "
|
|
Text
|
|
"
|
|
tm "RequirementText"
|
|
wrapOption 3
|
|
visibleHeight 1350
|
|
visibleWidth 1100
|
|
)
|
|
)
|
|
defaultPanel (Panel
|
|
shape (RectFrame
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "65535,65535,65535"
|
|
lineColor "32768,0,0"
|
|
lineWidth 3
|
|
)
|
|
xt "0,0,20000,20000"
|
|
)
|
|
title (TextAssociate
|
|
ps "TopLeftStrategy"
|
|
text (Text
|
|
va (VaSet
|
|
font "Verdana,8,1"
|
|
)
|
|
xt "1000,1000,4000,1900"
|
|
st "Panel0"
|
|
blo "1000,1700"
|
|
tm "PanelText"
|
|
)
|
|
)
|
|
)
|
|
parentGraphicsRef (HdmGraphicsRef
|
|
libraryName "SplineInterpolator_test"
|
|
entityName "sineGen_tb"
|
|
viewName "struct.bd"
|
|
)
|
|
defaultSymbolBody (SymbolBody
|
|
shape (Rectangle
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "0,65535,0"
|
|
lineColor "0,32896,0"
|
|
lineWidth 2
|
|
)
|
|
xt "15000,6000,39000,26000"
|
|
)
|
|
biTextGroup (BiTextGroup
|
|
ps "CenterOffsetStrategy"
|
|
stg "VerticalLayoutStrategy"
|
|
first (Text
|
|
va (VaSet
|
|
font "Verdana,8,1"
|
|
)
|
|
xt "24750,15100,29250,16000"
|
|
st "<library>"
|
|
blo "24750,15800"
|
|
)
|
|
second (Text
|
|
va (VaSet
|
|
font "Verdana,8,1"
|
|
)
|
|
xt "24750,16000,27750,16900"
|
|
st "<cell>"
|
|
blo "24750,16700"
|
|
)
|
|
)
|
|
gi *94 (GenericInterface
|
|
ps "CenterOffsetStrategy"
|
|
matrix (Matrix
|
|
text (MLText
|
|
va (VaSet
|
|
font "Verdana,8,0"
|
|
)
|
|
xt "0,12000,9700,13000"
|
|
st "Generic Declarations"
|
|
)
|
|
header "Generic Declarations"
|
|
showHdrWhenContentsEmpty 1
|
|
)
|
|
elements [
|
|
]
|
|
)
|
|
portInstanceVisAsIs 1
|
|
portInstanceVis (PortSigDisplay
|
|
sIVOD 1
|
|
)
|
|
portVis (PortSigDisplay
|
|
sIVOD 1
|
|
)
|
|
)
|
|
defaultCptPort (CptPort
|
|
ps "OnEdgeStrategy"
|
|
shape (Triangle
|
|
ro 90
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "0,65535,0"
|
|
)
|
|
xt "0,0,750,750"
|
|
)
|
|
tg (CPTG
|
|
ps "CptPortTextPlaceStrategy"
|
|
stg "VerticalLayoutStrategy"
|
|
f (Text
|
|
va (VaSet
|
|
font "Verdana,8,0"
|
|
)
|
|
xt "0,750,1500,1650"
|
|
st "In0"
|
|
blo "0,1450"
|
|
tm "CptPortNameMgr"
|
|
)
|
|
)
|
|
dt (MLText
|
|
va (VaSet
|
|
font "Verdana,8,0"
|
|
)
|
|
)
|
|
thePort (LogicalPort
|
|
lang 11
|
|
decl (Decl
|
|
n "In0"
|
|
t "std_logic_vector"
|
|
b "(15 DOWNTO 0)"
|
|
o 0
|
|
)
|
|
)
|
|
)
|
|
defaultCptPortBuffer (CptPort
|
|
ps "OnEdgeStrategy"
|
|
shape (Diamond
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "65535,65535,65535"
|
|
bg "0,0,0"
|
|
)
|
|
xt "0,0,750,750"
|
|
)
|
|
tg (CPTG
|
|
ps "CptPortTextPlaceStrategy"
|
|
stg "VerticalLayoutStrategy"
|
|
f (Text
|
|
va (VaSet
|
|
font "Verdana,8,0"
|
|
)
|
|
xt "0,750,3500,1650"
|
|
st "Buffer0"
|
|
blo "0,1450"
|
|
tm "CptPortNameMgr"
|
|
)
|
|
)
|
|
dt (MLText
|
|
va (VaSet
|
|
font "Verdana,8,0"
|
|
)
|
|
)
|
|
thePort (LogicalPort
|
|
lang 11
|
|
m 3
|
|
decl (Decl
|
|
n "Buffer0"
|
|
t "std_logic_vector"
|
|
b "(15 DOWNTO 0)"
|
|
o 0
|
|
)
|
|
)
|
|
)
|
|
DeclarativeBlock *95 (SymDeclBlock
|
|
uid 1,0
|
|
stg "SymDeclLayoutStrategy"
|
|
declLabel (Text
|
|
uid 2,0
|
|
va (VaSet
|
|
font "Verdana,8,1"
|
|
)
|
|
xt "42000,0,49000,1000"
|
|
st "Declarations"
|
|
blo "42000,800"
|
|
)
|
|
portLabel (Text
|
|
uid 3,0
|
|
va (VaSet
|
|
font "Verdana,8,1"
|
|
)
|
|
xt "42000,1000,45400,2000"
|
|
st "Ports:"
|
|
blo "42000,1800"
|
|
)
|
|
externalLabel (Text
|
|
uid 4,0
|
|
va (VaSet
|
|
font "Verdana,8,1"
|
|
)
|
|
xt "42000,7600,45000,8600"
|
|
st "User:"
|
|
blo "42000,8400"
|
|
)
|
|
internalLabel (Text
|
|
uid 6,0
|
|
va (VaSet
|
|
isHidden 1
|
|
font "Verdana,8,1"
|
|
)
|
|
xt "42000,0,49600,1000"
|
|
st "Internal User:"
|
|
blo "42000,800"
|
|
)
|
|
externalText (MLText
|
|
uid 5,0
|
|
va (VaSet
|
|
font "Verdana,8,0"
|
|
)
|
|
xt "44000,8600,44000,8600"
|
|
tm "SyDeclarativeTextMgr"
|
|
)
|
|
internalText (MLText
|
|
uid 7,0
|
|
va (VaSet
|
|
isHidden 1
|
|
font "Verdana,8,0"
|
|
)
|
|
xt "42000,0,42000,0"
|
|
tm "SyDeclarativeTextMgr"
|
|
)
|
|
)
|
|
lastUid 447,0
|
|
activeModelName "Symbol:GEN"
|
|
)
|