2248 lines
28 KiB
Plaintext
2248 lines
28 KiB
Plaintext
DocumentHdrVersion "1.1"
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Header (DocumentHdr
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version 2
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dialect 11
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dmPackageRefs [
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(DmPackageRef
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library "ieee"
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unitName "std_logic_1164"
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)
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(DmPackageRef
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library "ieee"
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unitName "numeric_std"
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)
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(DmPackageRef
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library "AhbLite"
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unitName "ahbLite"
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)
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]
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libraryRefs [
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"ieee"
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"AhbLite"
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]
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)
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version "26.1"
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appVersion "2018.1 (Build 12)"
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model (Symbol
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commonDM (CommonDM
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ldm (LogicalDM
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ordering 1
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suid 2020,0
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usingSuid 1
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emptyRow *1 (LEmptyRow
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)
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uid 201,0
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optionalChildren [
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*2 (LogPort
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port (LogicalPort
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m 1
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decl (Decl
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n "outX"
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t "std_ulogic"
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o 1
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suid 3,0
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)
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)
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uid 203,0
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)
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*3 (LogPort
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port (LogicalPort
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decl (Decl
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n "selSinCos"
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t "std_ulogic"
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o 5
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suid 13,0
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)
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)
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uid 204,0
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)
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*4 (LogPort
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port (LogicalPort
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decl (Decl
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n "hClk"
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t "std_ulogic"
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o 13
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suid 1,0
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)
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)
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uid 206,0
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)
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*5 (LogPort
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port (LogicalPort
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decl (Decl
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n "hWData"
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t "std_ulogic_vector"
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b "(ahbDataBitNb-1 downto 0)"
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o 4
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suid 11,0
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)
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)
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uid 207,0
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)
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*6 (LogPort
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port (LogicalPort
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decl (Decl
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n "hAddr"
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t "unsigned"
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b "(ahbAddressBitNb-1 downto 0)"
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o 2
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suid 2,0
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)
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)
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uid 209,0
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)
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*7 (LogPort
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port (LogicalPort
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m 1
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decl (Decl
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n "outY"
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t "std_ulogic"
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o 3
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suid 5,0
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)
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)
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uid 210,0
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)
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*8 (LogPort
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port (LogicalPort
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decl (Decl
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n "hReset_n"
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t "std_ulogic"
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o 14
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suid 4,0
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)
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)
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uid 211,0
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)
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*9 (RefLabelRowHdr
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)
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*10 (TitleRowHdr
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)
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|
*11 (FilterRowHdr
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)
|
|
*12 (RefLabelColHdr
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|
tm "RefLabelColHdrMgr"
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)
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|
*13 (RowExpandColHdr
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tm "RowExpandColHdrMgr"
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)
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|
*14 (GroupColHdr
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|
tm "GroupColHdrMgr"
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)
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*15 (NameColHdr
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tm "NameColHdrMgr"
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)
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|
*16 (ModeColHdr
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|
tm "ModeColHdrMgr"
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)
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|
*17 (TypeColHdr
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|
tm "TypeColHdrMgr"
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)
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*18 (BoundsColHdr
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|
tm "BoundsColHdrMgr"
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)
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*19 (InitColHdr
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|
tm "InitColHdrMgr"
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)
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|
*20 (EolColHdr
|
|
tm "EolColHdrMgr"
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)
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*21 (LogPort
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|
port (LogicalPort
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|
m 1
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decl (Decl
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|
n "testOut"
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t "std_ulogic_vector"
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b "(1 TO testOutBitNb)"
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o 6
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suid 2014,0
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)
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)
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uid 548,0
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)
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*22 (LogPort
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port (LogicalPort
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m 1
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decl (Decl
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n "hRData"
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t "std_ulogic_vector"
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b "(ahbDataBitNb-1 downto 0)"
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o 7
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suid 2015,0
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)
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)
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uid 745,0
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)
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*23 (LogPort
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port (LogicalPort
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|
decl (Decl
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n "hTrans"
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t "std_ulogic_vector"
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b "(ahbTransBitNb-1 downto 0)"
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o 8
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suid 2016,0
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)
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)
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uid 747,0
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)
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*24 (LogPort
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port (LogicalPort
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decl (Decl
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n "hWrite"
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t "std_ulogic"
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o 9
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suid 2017,0
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)
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)
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uid 749,0
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)
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|
*25 (LogPort
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port (LogicalPort
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|
decl (Decl
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|
n "hSel"
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|
t "std_ulogic"
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|
o 10
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suid 2018,0
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)
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)
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|
uid 751,0
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)
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|
*26 (LogPort
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port (LogicalPort
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|
m 1
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|
decl (Decl
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|
n "hReady"
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|
t "std_ulogic"
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|
o 11
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suid 2019,0
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)
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)
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|
uid 753,0
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)
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|
*27 (LogPort
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|
port (LogicalPort
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|
m 1
|
|
decl (Decl
|
|
n "hResp"
|
|
t "std_ulogic"
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|
o 12
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|
suid 2020,0
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)
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)
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|
uid 755,0
|
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)
|
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]
|
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)
|
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pdm (PhysicalDM
|
|
displayShortBounds 1
|
|
editShortBounds 1
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|
uid 215,0
|
|
optionalChildren [
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|
*28 (Sheet
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|
sheetRow (SheetRow
|
|
headerVa (MVa
|
|
cellColor "49152,49152,49152"
|
|
fontColor "0,0,0"
|
|
font "courier,10,0"
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|
)
|
|
cellVa (MVa
|
|
cellColor "65535,65535,65535"
|
|
fontColor "0,0,0"
|
|
font "courier,10,0"
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|
)
|
|
groupVa (MVa
|
|
cellColor "39936,56832,65280"
|
|
fontColor "0,0,0"
|
|
font "courier,10,0"
|
|
)
|
|
emptyMRCItem *29 (MRCItem
|
|
litem &1
|
|
pos 14
|
|
dimension 20
|
|
)
|
|
uid 132,0
|
|
optionalChildren [
|
|
*30 (MRCItem
|
|
litem &9
|
|
pos 0
|
|
dimension 20
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|
uid 135,0
|
|
)
|
|
*31 (MRCItem
|
|
litem &10
|
|
pos 1
|
|
dimension 23
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|
uid 137,0
|
|
)
|
|
*32 (MRCItem
|
|
litem &11
|
|
pos 2
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|
hidden 1
|
|
dimension 20
|
|
uid 139,0
|
|
)
|
|
*33 (MRCItem
|
|
litem &2
|
|
pos 1
|
|
dimension 20
|
|
uid 159,0
|
|
)
|
|
*34 (MRCItem
|
|
litem &3
|
|
pos 5
|
|
dimension 20
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|
uid 160,0
|
|
)
|
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*35 (MRCItem
|
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litem &4
|
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pos 6
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dimension 20
|
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uid 162,0
|
|
)
|
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*36 (MRCItem
|
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litem &5
|
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pos 4
|
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dimension 20
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uid 163,0
|
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)
|
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*37 (MRCItem
|
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litem &6
|
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pos 0
|
|
dimension 20
|
|
uid 165,0
|
|
)
|
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*38 (MRCItem
|
|
litem &7
|
|
pos 2
|
|
dimension 20
|
|
uid 166,0
|
|
)
|
|
*39 (MRCItem
|
|
litem &8
|
|
pos 3
|
|
dimension 20
|
|
uid 167,0
|
|
)
|
|
*40 (MRCItem
|
|
litem &21
|
|
pos 7
|
|
dimension 20
|
|
uid 547,0
|
|
)
|
|
*41 (MRCItem
|
|
litem &22
|
|
pos 8
|
|
dimension 20
|
|
uid 746,0
|
|
)
|
|
*42 (MRCItem
|
|
litem &23
|
|
pos 9
|
|
dimension 20
|
|
uid 748,0
|
|
)
|
|
*43 (MRCItem
|
|
litem &24
|
|
pos 10
|
|
dimension 20
|
|
uid 750,0
|
|
)
|
|
*44 (MRCItem
|
|
litem &25
|
|
pos 11
|
|
dimension 20
|
|
uid 752,0
|
|
)
|
|
*45 (MRCItem
|
|
litem &26
|
|
pos 12
|
|
dimension 20
|
|
uid 754,0
|
|
)
|
|
*46 (MRCItem
|
|
litem &27
|
|
pos 13
|
|
dimension 20
|
|
uid 756,0
|
|
)
|
|
]
|
|
)
|
|
sheetCol (SheetCol
|
|
propVa (MVa
|
|
cellColor "0,49152,49152"
|
|
fontColor "0,0,0"
|
|
font "courier,10,0"
|
|
textAngle 90
|
|
)
|
|
uid 133,0
|
|
optionalChildren [
|
|
*47 (MRCItem
|
|
litem &12
|
|
pos 0
|
|
dimension 20
|
|
uid 141,0
|
|
)
|
|
*48 (MRCItem
|
|
litem &14
|
|
pos 1
|
|
dimension 50
|
|
uid 145,0
|
|
)
|
|
*49 (MRCItem
|
|
litem &15
|
|
pos 2
|
|
dimension 100
|
|
uid 147,0
|
|
)
|
|
*50 (MRCItem
|
|
litem &16
|
|
pos 3
|
|
dimension 50
|
|
uid 149,0
|
|
)
|
|
*51 (MRCItem
|
|
litem &17
|
|
pos 4
|
|
dimension 100
|
|
uid 151,0
|
|
)
|
|
*52 (MRCItem
|
|
litem &18
|
|
pos 5
|
|
dimension 100
|
|
uid 153,0
|
|
)
|
|
*53 (MRCItem
|
|
litem &19
|
|
pos 6
|
|
dimension 50
|
|
uid 155,0
|
|
)
|
|
*54 (MRCItem
|
|
litem &20
|
|
pos 7
|
|
dimension 80
|
|
uid 157,0
|
|
)
|
|
]
|
|
)
|
|
fixedCol 4
|
|
fixedRow 2
|
|
name "Ports"
|
|
uid 131,0
|
|
vaOverrides [
|
|
]
|
|
)
|
|
]
|
|
)
|
|
uid 200,0
|
|
)
|
|
genericsCommonDM (CommonDM
|
|
ldm (LogicalDM
|
|
emptyRow *55 (LEmptyRow
|
|
)
|
|
uid 217,0
|
|
optionalChildren [
|
|
*56 (RefLabelRowHdr
|
|
)
|
|
*57 (TitleRowHdr
|
|
)
|
|
*58 (FilterRowHdr
|
|
)
|
|
*59 (RefLabelColHdr
|
|
tm "RefLabelColHdrMgr"
|
|
)
|
|
*60 (RowExpandColHdr
|
|
tm "RowExpandColHdrMgr"
|
|
)
|
|
*61 (GroupColHdr
|
|
tm "GroupColHdrMgr"
|
|
)
|
|
*62 (NameColHdr
|
|
tm "GenericNameColHdrMgr"
|
|
)
|
|
*63 (TypeColHdr
|
|
tm "GenericTypeColHdrMgr"
|
|
)
|
|
*64 (InitColHdr
|
|
tm "GenericValueColHdrMgr"
|
|
)
|
|
*65 (PragmaColHdr
|
|
tm "GenericPragmaColHdrMgr"
|
|
)
|
|
*66 (EolColHdr
|
|
tm "GenericEolColHdrMgr"
|
|
)
|
|
*67 (LogGeneric
|
|
generic (GiElement
|
|
name "testOutBitNb"
|
|
type "positive"
|
|
value "16"
|
|
)
|
|
uid 197,0
|
|
)
|
|
*68 (LogGeneric
|
|
generic (GiElement
|
|
name "patternAddressBitNb"
|
|
type "positive"
|
|
value "9"
|
|
)
|
|
uid 476,0
|
|
)
|
|
]
|
|
)
|
|
pdm (PhysicalDM
|
|
uid 218,0
|
|
optionalChildren [
|
|
*69 (Sheet
|
|
sheetRow (SheetRow
|
|
headerVa (MVa
|
|
cellColor "49152,49152,49152"
|
|
fontColor "0,0,0"
|
|
font "courier,10,0"
|
|
)
|
|
cellVa (MVa
|
|
cellColor "65535,65535,65535"
|
|
fontColor "0,0,0"
|
|
font "courier,10,0"
|
|
)
|
|
groupVa (MVa
|
|
cellColor "39936,56832,65280"
|
|
fontColor "0,0,0"
|
|
font "courier,10,0"
|
|
)
|
|
emptyMRCItem *70 (MRCItem
|
|
litem &55
|
|
pos 2
|
|
dimension 20
|
|
)
|
|
uid 172,0
|
|
optionalChildren [
|
|
*71 (MRCItem
|
|
litem &56
|
|
pos 0
|
|
dimension 20
|
|
uid 175,0
|
|
)
|
|
*72 (MRCItem
|
|
litem &57
|
|
pos 1
|
|
dimension 23
|
|
uid 177,0
|
|
)
|
|
*73 (MRCItem
|
|
litem &58
|
|
pos 2
|
|
hidden 1
|
|
dimension 20
|
|
uid 179,0
|
|
)
|
|
*74 (MRCItem
|
|
litem &67
|
|
pos 1
|
|
dimension 20
|
|
uid 199,0
|
|
)
|
|
*75 (MRCItem
|
|
litem &68
|
|
pos 0
|
|
dimension 20
|
|
uid 477,0
|
|
)
|
|
]
|
|
)
|
|
sheetCol (SheetCol
|
|
propVa (MVa
|
|
cellColor "0,49152,49152"
|
|
fontColor "0,0,0"
|
|
font "courier,10,0"
|
|
textAngle 90
|
|
)
|
|
uid 173,0
|
|
optionalChildren [
|
|
*76 (MRCItem
|
|
litem &59
|
|
pos 0
|
|
dimension 20
|
|
uid 181,0
|
|
)
|
|
*77 (MRCItem
|
|
litem &61
|
|
pos 1
|
|
dimension 50
|
|
uid 185,0
|
|
)
|
|
*78 (MRCItem
|
|
litem &62
|
|
pos 2
|
|
dimension 100
|
|
uid 187,0
|
|
)
|
|
*79 (MRCItem
|
|
litem &63
|
|
pos 3
|
|
dimension 100
|
|
uid 189,0
|
|
)
|
|
*80 (MRCItem
|
|
litem &64
|
|
pos 4
|
|
dimension 50
|
|
uid 191,0
|
|
)
|
|
*81 (MRCItem
|
|
litem &65
|
|
pos 5
|
|
dimension 50
|
|
uid 193,0
|
|
)
|
|
*82 (MRCItem
|
|
litem &66
|
|
pos 6
|
|
dimension 80
|
|
uid 195,0
|
|
)
|
|
]
|
|
)
|
|
fixedCol 3
|
|
fixedRow 2
|
|
name "Ports"
|
|
uid 171,0
|
|
vaOverrides [
|
|
]
|
|
)
|
|
]
|
|
)
|
|
uid 216,0
|
|
type 1
|
|
)
|
|
VExpander (VariableExpander
|
|
vvMap [
|
|
(vvPair
|
|
variable " "
|
|
value " "
|
|
)
|
|
(vvPair
|
|
variable "HDLDir"
|
|
value "/home/francois/Documents/HEVs/SEm/SEm_labs/VHDL/SystemOnChip/Prefs/../SystemOnChip/hdl"
|
|
)
|
|
(vvPair
|
|
variable "HDSDir"
|
|
value "/home/francois/Documents/HEVs/SEm/SEm_labs/VHDL/SystemOnChip/Prefs/../SystemOnChip/hds"
|
|
)
|
|
(vvPair
|
|
variable "SideDataDesignDir"
|
|
value "/home/francois/Documents/HEVs/SEm/SEm_labs/VHDL/SystemOnChip/Prefs/../SystemOnChip/hds/ahb@beamer/symbol.sb.info"
|
|
)
|
|
(vvPair
|
|
variable "SideDataUserDir"
|
|
value "/home/francois/Documents/HEVs/SEm/SEm_labs/VHDL/SystemOnChip/Prefs/../SystemOnChip/hds/ahb@beamer/symbol.sb.user"
|
|
)
|
|
(vvPair
|
|
variable "SourceDir"
|
|
value "/home/francois/Documents/HEVs/SEm/SEm_labs/VHDL/SystemOnChip/Prefs/../SystemOnChip/hds"
|
|
)
|
|
(vvPair
|
|
variable "appl"
|
|
value "HDL Designer"
|
|
)
|
|
(vvPair
|
|
variable "arch_name"
|
|
value "symbol"
|
|
)
|
|
(vvPair
|
|
variable "asm_file"
|
|
value "beamer.asm"
|
|
)
|
|
(vvPair
|
|
variable "concat_file"
|
|
value "concatenated"
|
|
)
|
|
(vvPair
|
|
variable "config"
|
|
value "%(unit)_%(view)_config"
|
|
)
|
|
(vvPair
|
|
variable "d"
|
|
value "/home/francois/Documents/HEVs/SEm/SEm_labs/VHDL/SystemOnChip/Prefs/../SystemOnChip/hds/ahb@beamer"
|
|
)
|
|
(vvPair
|
|
variable "d_logical"
|
|
value "/home/francois/Documents/HEVs/SEm/SEm_labs/VHDL/SystemOnChip/Prefs/../SystemOnChip/hds/ahbBeamer"
|
|
)
|
|
(vvPair
|
|
variable "date"
|
|
value "03/13/19"
|
|
)
|
|
(vvPair
|
|
variable "day"
|
|
value "Wed"
|
|
)
|
|
(vvPair
|
|
variable "day_long"
|
|
value "Wednesday"
|
|
)
|
|
(vvPair
|
|
variable "dd"
|
|
value "13"
|
|
)
|
|
(vvPair
|
|
variable "designName"
|
|
value "$DESIGN_NAME"
|
|
)
|
|
(vvPair
|
|
variable "entity_name"
|
|
value "ahbBeamer"
|
|
)
|
|
(vvPair
|
|
variable "ext"
|
|
value "<TBD>"
|
|
)
|
|
(vvPair
|
|
variable "f"
|
|
value "symbol.sb"
|
|
)
|
|
(vvPair
|
|
variable "f_logical"
|
|
value "symbol.sb"
|
|
)
|
|
(vvPair
|
|
variable "f_noext"
|
|
value "symbol"
|
|
)
|
|
(vvPair
|
|
variable "graphical_source_author"
|
|
value "francois"
|
|
)
|
|
(vvPair
|
|
variable "graphical_source_date"
|
|
value "03/13/19"
|
|
)
|
|
(vvPair
|
|
variable "graphical_source_group"
|
|
value "francois"
|
|
)
|
|
(vvPair
|
|
variable "graphical_source_host"
|
|
value "Aphelia"
|
|
)
|
|
(vvPair
|
|
variable "graphical_source_time"
|
|
value "14:40:22"
|
|
)
|
|
(vvPair
|
|
variable "group"
|
|
value "francois"
|
|
)
|
|
(vvPair
|
|
variable "host"
|
|
value "Aphelia"
|
|
)
|
|
(vvPair
|
|
variable "language"
|
|
value "VHDL"
|
|
)
|
|
(vvPair
|
|
variable "library"
|
|
value "SystemOnChip"
|
|
)
|
|
(vvPair
|
|
variable "library_downstream_Generic_1_file"
|
|
value "U:\\SEm_curves\\Synthesis"
|
|
)
|
|
(vvPair
|
|
variable "library_downstream_ModelSim"
|
|
value "D:\\Users\\ELN_labs\\VHDL_comp"
|
|
)
|
|
(vvPair
|
|
variable "library_downstream_ModelSimCompiler"
|
|
value "$SCRATCH_DIR/SystemOnChip"
|
|
)
|
|
(vvPair
|
|
variable "library_downstream_SpyGlass"
|
|
value "U:\\SEm_curves\\Synthesis"
|
|
)
|
|
(vvPair
|
|
variable "mm"
|
|
value "03"
|
|
)
|
|
(vvPair
|
|
variable "module_name"
|
|
value "ahbBeamer"
|
|
)
|
|
(vvPair
|
|
variable "month"
|
|
value "Mar"
|
|
)
|
|
(vvPair
|
|
variable "month_long"
|
|
value "March"
|
|
)
|
|
(vvPair
|
|
variable "p"
|
|
value "/home/francois/Documents/HEVs/SEm/SEm_labs/VHDL/SystemOnChip/Prefs/../SystemOnChip/hds/ahb@beamer/symbol.sb"
|
|
)
|
|
(vvPair
|
|
variable "p_logical"
|
|
value "/home/francois/Documents/HEVs/SEm/SEm_labs/VHDL/SystemOnChip/Prefs/../SystemOnChip/hds/ahbBeamer/symbol.sb"
|
|
)
|
|
(vvPair
|
|
variable "package_name"
|
|
value "<Undefined Variable>"
|
|
)
|
|
(vvPair
|
|
variable "project_name"
|
|
value "systemOnChip"
|
|
)
|
|
(vvPair
|
|
variable "series"
|
|
value "HDL Designer Series"
|
|
)
|
|
(vvPair
|
|
variable "task_ADMS"
|
|
value "<TBD>"
|
|
)
|
|
(vvPair
|
|
variable "task_AsmPath"
|
|
value "$HEI_LIBS_DIR/NanoBlaze/hdl"
|
|
)
|
|
(vvPair
|
|
variable "task_DesignCompilerPath"
|
|
value "<TBD>"
|
|
)
|
|
(vvPair
|
|
variable "task_HDSPath"
|
|
value "$HDS_HOME"
|
|
)
|
|
(vvPair
|
|
variable "task_ISEBinPath"
|
|
value "$ISE_HOME"
|
|
)
|
|
(vvPair
|
|
variable "task_ISEPath"
|
|
value "$ISE_WORK_DIR"
|
|
)
|
|
(vvPair
|
|
variable "task_LeonardoPath"
|
|
value "<TBD>"
|
|
)
|
|
(vvPair
|
|
variable "task_ModelSimPath"
|
|
value "$MODELSIM_HOME/modeltech/bin"
|
|
)
|
|
(vvPair
|
|
variable "task_NC"
|
|
value "<TBD>"
|
|
)
|
|
(vvPair
|
|
variable "task_PrecisionRTLPath"
|
|
value "<TBD>"
|
|
)
|
|
(vvPair
|
|
variable "task_QuestaSimPath"
|
|
value "<TBD>"
|
|
)
|
|
(vvPair
|
|
variable "task_VCSPath"
|
|
value "<TBD>"
|
|
)
|
|
(vvPair
|
|
variable "this_ext"
|
|
value "sb"
|
|
)
|
|
(vvPair
|
|
variable "this_file"
|
|
value "symbol"
|
|
)
|
|
(vvPair
|
|
variable "this_file_logical"
|
|
value "symbol"
|
|
)
|
|
(vvPair
|
|
variable "time"
|
|
value "14:40:22"
|
|
)
|
|
(vvPair
|
|
variable "unit"
|
|
value "ahbBeamer"
|
|
)
|
|
(vvPair
|
|
variable "user"
|
|
value "francois"
|
|
)
|
|
(vvPair
|
|
variable "version"
|
|
value "2018.1 (Build 12)"
|
|
)
|
|
(vvPair
|
|
variable "view"
|
|
value "symbol"
|
|
)
|
|
(vvPair
|
|
variable "year"
|
|
value "2019"
|
|
)
|
|
(vvPair
|
|
variable "yy"
|
|
value "19"
|
|
)
|
|
]
|
|
)
|
|
LanguageMgr "Vhdl2008LangMgr"
|
|
uid 51,0
|
|
optionalChildren [
|
|
*83 (SymbolBody
|
|
uid 8,0
|
|
optionalChildren [
|
|
*84 (CptPort
|
|
uid 52,0
|
|
ps "OnEdgeStrategy"
|
|
shape (Triangle
|
|
uid 72,0
|
|
ro 90
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "0,65535,0"
|
|
)
|
|
xt "42250,27625,43000,28375"
|
|
)
|
|
tg (CPTG
|
|
uid 54,0
|
|
ps "CptPortTextPlaceStrategy"
|
|
stg "VerticalLayoutStrategy"
|
|
f (Text
|
|
uid 55,0
|
|
va (VaSet
|
|
font "courier,9,0"
|
|
)
|
|
xt "44000,27400,46000,28300"
|
|
st "hClk"
|
|
blo "44000,28100"
|
|
tm "CptPortNameMgr"
|
|
)
|
|
)
|
|
dt (MLText
|
|
uid 56,0
|
|
va (VaSet
|
|
font "courier,8,0"
|
|
)
|
|
xt "2000,20200,18500,21100"
|
|
st "hClk : IN std_ulogic ;"
|
|
)
|
|
thePort (LogicalPort
|
|
decl (Decl
|
|
n "hClk"
|
|
t "std_ulogic"
|
|
o 13
|
|
suid 1,0
|
|
)
|
|
)
|
|
)
|
|
*85 (CptPort
|
|
uid 57,0
|
|
ps "OnEdgeStrategy"
|
|
shape (Triangle
|
|
uid 58,0
|
|
ro 90
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "0,65535,0"
|
|
)
|
|
xt "42250,9625,43000,10375"
|
|
)
|
|
tg (CPTG
|
|
uid 59,0
|
|
ps "CptPortTextPlaceStrategy"
|
|
stg "VerticalLayoutStrategy"
|
|
f (Text
|
|
uid 60,0
|
|
va (VaSet
|
|
font "courier,9,0"
|
|
)
|
|
xt "44000,9400,46500,10300"
|
|
st "hAddr"
|
|
blo "44000,10100"
|
|
tm "CptPortNameMgr"
|
|
)
|
|
)
|
|
dt (MLText
|
|
uid 61,0
|
|
va (VaSet
|
|
font "courier,8,0"
|
|
)
|
|
xt "2000,10300,31500,11200"
|
|
st "hAddr : IN unsigned (ahbAddressBitNb-1 downto 0) ;"
|
|
)
|
|
thePort (LogicalPort
|
|
decl (Decl
|
|
n "hAddr"
|
|
t "unsigned"
|
|
b "(ahbAddressBitNb-1 downto 0)"
|
|
o 2
|
|
suid 2,0
|
|
)
|
|
)
|
|
)
|
|
*86 (CptPort
|
|
uid 67,0
|
|
ps "OnEdgeStrategy"
|
|
shape (Triangle
|
|
uid 68,0
|
|
ro 90
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "0,65535,0"
|
|
)
|
|
xt "59000,9625,59750,10375"
|
|
)
|
|
tg (CPTG
|
|
uid 69,0
|
|
ps "CptPortTextPlaceStrategy"
|
|
stg "RightVerticalLayoutStrategy"
|
|
f (Text
|
|
uid 70,0
|
|
va (VaSet
|
|
font "courier,9,0"
|
|
)
|
|
xt "56001,9400,58001,10300"
|
|
st "outX"
|
|
ju 2
|
|
blo "58001,10100"
|
|
tm "CptPortNameMgr"
|
|
)
|
|
)
|
|
dt (MLText
|
|
uid 71,0
|
|
va (VaSet
|
|
font "courier,8,0"
|
|
)
|
|
xt "2000,9400,18500,10300"
|
|
st "outX : OUT std_ulogic ;"
|
|
)
|
|
thePort (LogicalPort
|
|
m 1
|
|
decl (Decl
|
|
n "outX"
|
|
t "std_ulogic"
|
|
o 1
|
|
suid 3,0
|
|
)
|
|
)
|
|
)
|
|
*87 (CptPort
|
|
uid 76,0
|
|
ps "OnEdgeStrategy"
|
|
shape (Triangle
|
|
uid 77,0
|
|
ro 90
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "0,65535,0"
|
|
)
|
|
xt "42250,29625,43000,30375"
|
|
)
|
|
tg (CPTG
|
|
uid 78,0
|
|
ps "CptPortTextPlaceStrategy"
|
|
stg "VerticalLayoutStrategy"
|
|
f (Text
|
|
uid 79,0
|
|
va (VaSet
|
|
font "courier,9,0"
|
|
)
|
|
xt "44000,29400,48000,30300"
|
|
st "hReset_n"
|
|
blo "44000,30100"
|
|
tm "CptPortNameMgr"
|
|
)
|
|
)
|
|
dt (MLText
|
|
uid 80,0
|
|
va (VaSet
|
|
font "courier,8,0"
|
|
)
|
|
xt "2000,21100,17500,22000"
|
|
st "hReset_n : IN std_ulogic "
|
|
)
|
|
thePort (LogicalPort
|
|
decl (Decl
|
|
n "hReset_n"
|
|
t "std_ulogic"
|
|
o 14
|
|
suid 4,0
|
|
)
|
|
)
|
|
)
|
|
*88 (CptPort
|
|
uid 82,0
|
|
ps "OnEdgeStrategy"
|
|
shape (Triangle
|
|
uid 83,0
|
|
ro 90
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "0,65535,0"
|
|
)
|
|
xt "59000,11625,59750,12375"
|
|
)
|
|
tg (CPTG
|
|
uid 84,0
|
|
ps "CptPortTextPlaceStrategy"
|
|
stg "RightVerticalLayoutStrategy"
|
|
f (Text
|
|
uid 85,0
|
|
va (VaSet
|
|
font "courier,9,0"
|
|
)
|
|
xt "56001,11400,58001,12300"
|
|
st "outY"
|
|
ju 2
|
|
blo "58001,12100"
|
|
tm "CptPortNameMgr"
|
|
)
|
|
)
|
|
dt (MLText
|
|
uid 86,0
|
|
va (VaSet
|
|
font "courier,8,0"
|
|
)
|
|
xt "2000,11200,18500,12100"
|
|
st "outY : OUT std_ulogic ;"
|
|
)
|
|
thePort (LogicalPort
|
|
m 1
|
|
decl (Decl
|
|
n "outY"
|
|
t "std_ulogic"
|
|
o 3
|
|
suid 5,0
|
|
)
|
|
)
|
|
)
|
|
*89 (CptPort
|
|
uid 113,0
|
|
ps "OnEdgeStrategy"
|
|
shape (Triangle
|
|
uid 780,0
|
|
ro 90
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "0,65535,0"
|
|
)
|
|
xt "42250,11625,43000,12375"
|
|
)
|
|
tg (CPTG
|
|
uid 115,0
|
|
ps "CptPortTextPlaceStrategy"
|
|
stg "VerticalLayoutStrategy"
|
|
f (Text
|
|
uid 116,0
|
|
va (VaSet
|
|
font "courier,9,0"
|
|
)
|
|
xt "44000,11400,47000,12300"
|
|
st "hWData"
|
|
blo "44000,12100"
|
|
tm "CptPortNameMgr"
|
|
)
|
|
)
|
|
dt (MLText
|
|
uid 117,0
|
|
va (VaSet
|
|
font "courier,8,0"
|
|
)
|
|
xt "2000,12100,34500,13000"
|
|
st "hWData : IN std_ulogic_vector (ahbDataBitNb-1 downto 0) ;"
|
|
)
|
|
thePort (LogicalPort
|
|
decl (Decl
|
|
n "hWData"
|
|
t "std_ulogic_vector"
|
|
b "(ahbDataBitNb-1 downto 0)"
|
|
o 4
|
|
suid 11,0
|
|
)
|
|
)
|
|
)
|
|
*90 (CptPort
|
|
uid 125,0
|
|
ps "OnEdgeStrategy"
|
|
shape (Triangle
|
|
uid 130,0
|
|
ro 270
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "0,65535,0"
|
|
)
|
|
xt "59000,15625,59750,16375"
|
|
)
|
|
tg (CPTG
|
|
uid 127,0
|
|
ps "CptPortTextPlaceStrategy"
|
|
stg "RightVerticalLayoutStrategy"
|
|
f (Text
|
|
uid 128,0
|
|
va (VaSet
|
|
font "courier,9,0"
|
|
)
|
|
xt "53501,15400,58001,16300"
|
|
st "selSinCos"
|
|
ju 2
|
|
blo "58001,16100"
|
|
tm "CptPortNameMgr"
|
|
)
|
|
)
|
|
dt (MLText
|
|
uid 129,0
|
|
va (VaSet
|
|
font "courier,8,0"
|
|
)
|
|
xt "2000,13000,18500,13900"
|
|
st "selSinCos : IN std_ulogic ;"
|
|
)
|
|
thePort (LogicalPort
|
|
decl (Decl
|
|
n "selSinCos"
|
|
t "std_ulogic"
|
|
o 5
|
|
suid 13,0
|
|
)
|
|
)
|
|
)
|
|
*91 (CptPort
|
|
uid 549,0
|
|
ps "OnEdgeStrategy"
|
|
shape (Triangle
|
|
uid 550,0
|
|
ro 90
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "0,65535,0"
|
|
)
|
|
xt "59000,27625,59750,28375"
|
|
)
|
|
tg (CPTG
|
|
uid 551,0
|
|
ps "CptPortTextPlaceStrategy"
|
|
stg "RightVerticalLayoutStrategy"
|
|
f (Text
|
|
uid 552,0
|
|
va (VaSet
|
|
font "courier,9,0"
|
|
)
|
|
xt "54500,27400,58000,28300"
|
|
st "testOut"
|
|
ju 2
|
|
blo "58000,28100"
|
|
tm "CptPortNameMgr"
|
|
)
|
|
)
|
|
dt (MLText
|
|
uid 553,0
|
|
va (VaSet
|
|
font "courier,8,0"
|
|
)
|
|
xt "2000,13900,31500,14800"
|
|
st "testOut : OUT std_ulogic_vector (1 TO testOutBitNb) ;"
|
|
)
|
|
thePort (LogicalPort
|
|
m 1
|
|
decl (Decl
|
|
n "testOut"
|
|
t "std_ulogic_vector"
|
|
b "(1 TO testOutBitNb)"
|
|
o 6
|
|
suid 2014,0
|
|
)
|
|
)
|
|
)
|
|
*92 (CptPort
|
|
uid 715,0
|
|
ps "OnEdgeStrategy"
|
|
shape (Triangle
|
|
uid 716,0
|
|
ro 270
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "0,65535,0"
|
|
)
|
|
xt "42250,19625,43000,20375"
|
|
)
|
|
tg (CPTG
|
|
uid 717,0
|
|
ps "CptPortTextPlaceStrategy"
|
|
stg "VerticalLayoutStrategy"
|
|
f (Text
|
|
uid 718,0
|
|
va (VaSet
|
|
font "courier,9,0"
|
|
)
|
|
xt "44000,19400,47000,20300"
|
|
st "hRData"
|
|
blo "44000,20100"
|
|
tm "CptPortNameMgr"
|
|
)
|
|
)
|
|
dt (MLText
|
|
uid 719,0
|
|
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