1183 lines
15 KiB
Plaintext
1183 lines
15 KiB
Plaintext
DocumentHdrVersion "1.1"
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Header (DocumentHdr
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packageRefs [
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(PackageRef
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library "ieee"
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unitName "std_logic_1164"
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itemName "all"
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)
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(PackageRef
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library "ieee"
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unitName "numeric_std"
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itemName "all"
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version "15.1"
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variable " "
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value " "
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variable "HDLDir"
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value "D:\\Users\\ELN_labs\\VHDL_gen"
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)
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(vvPair
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variable "SideDataDesignDir"
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value "U:\\SEm_curves\\Test\\sine@gen_tester\\interface.info"
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(vvPair
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variable "SideDataUserDir"
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value "U:\\SEm_curves\\Test\\sine@gen_tester\\interface.user"
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(vvPair
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variable "SourceDir"
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value "U:\\SEm_curves\\Test"
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variable "appl"
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value "HDL Designer - Pro"
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variable "d"
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value "U:\\SEm_curves\\Test\\sine@gen_tester"
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variable "d_logical"
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value "U:\\SEm_curves\\Test\\sineGen_tester"
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variable "date"
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value "04/01/08"
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variable "day"
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value "Tue"
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variable "day_long"
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value "Tuesday"
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variable "dd"
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value "01"
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variable "ext"
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value "<TBD>"
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variable "f"
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value "interface"
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variable "host"
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value "WE2636"
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variable "library"
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value "Curves_test"
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variable "library_downstream_ModelSim"
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value "D:\\Users\\ELN_labs\\VHDL_comp"
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(vvPair
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variable "mm"
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value "04"
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(vvPair
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variable "month"
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value "Apr"
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(vvPair
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variable "month_long"
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value "April"
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variable "p"
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value "U:\\SEm_curves\\Test\\sine@gen_tester\\interface"
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)
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(vvPair
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variable "p_logical"
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value "U:\\SEm_curves\\Test\\sineGen_tester\\interface"
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(vvPair
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variable "series"
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value "HDL Designer Series"
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)
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(vvPair
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variable "time"
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value "12:48:44"
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)
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(vvPair
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variable "unit"
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value "sineGen_tester"
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)
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(vvPair
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variable "user"
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value "cof"
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(vvPair
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variable "version"
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value "2002.1a (Build 22)"
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)
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(vvPair
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variable "view"
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value "interface"
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)
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(vvPair
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variable "year"
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value "2008"
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)
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(vvPair
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variable "yy"
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value "08"
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